Design and implementation of a low-noise high-linearity variable gain amplifier for high speed transceivers

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Institutionen för systemteknik

Department of Electrical Engineering

Examensarbete

Design and implementation of a low-noise high-linearity

variable gain amplifier for high speed transceivers

Master Thesis in Division of Electronics Systems

at Linköping Institute of Technology

by

Rehan Azmat

LiTH-ISY-EX--11/4543--SE

21

st

December, 2011

TEKNISKA HÖGSKOLAN

LINKÖPINGS UNIVERSITET

Department of Electrical Engineering Linköping University

S-581 83 Linköping, Sweden

Linköpings tekniska högskola Institutionen för systemteknik 581 83 Linköping

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Master thesis performed in

Fraunhofer Institute for Integrated Circuits (IIS)

Erlangen, Germany

Design and implementation of a low-noise high-linearity

variable gain amplifier for high speed transceivers

Master Thesis in Division of Electronics Systems

at Linköping Institute of Technology

by

Rehan Azmat

LiTH-ISY-EX--11/4543--SE

Supervisor

:

Supervisor:

Conrad Zerna

Dr J. Jacob Wikner

Optical Sensors and Communications

Department of Electrical Engineering

Fraunhofer Institute for Integrated Circuits (IIS)

Linköping University

Erlangen, Germany

Linköping, Sweden

conrad.zerna@iis.fraunhofer.de

jacob.wikner @ liu.se

Examiner

:

Dr. Mark Vesterbacka

Department of Electrical Engineering (ISY)

Linköping University

Linköping, Sweden

mark.vesterbacka @ liu.se

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Presentation Date

2011 – 12 - 21

Publishing Date (Electronic version)

2012 – 02 - 02

Department and Division

Department of Electrical Engineering Division of Electronics Systems Linköping University

SE-581 83, Linkoping, Sweden

URL, Electronic Version

http://www.ep.liu.se

http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-73449

Publication Title

Design and implementation of a low-noise high-linearity variable gain amplifier for high speed

transceivers.

Author(s)

Rehan Azmat

Abstract

The variable gain amplifier (VGA) is utilized in various applications of remote sensing and

communication equipments. Applications of the variable gain amplifier (VGA) include radar,

ultrasound, wireless communication and even speech analysis. These applications use the variable gain

amplifier (VGA) to enhance dynamic performance.

The purpose of the thesis work is to implement a high linearity and low noise variable gain amplifier in

150 nm CMOS technology, for an analog-front-end of a transceiver. Two different amplifier

architectures are designed and compared. First architecture is an amplifier with diode connected load

and second architecture is a source degenerative amplifier. The performance of the amplifier with diode

connected load is lower than the source degenerative amplifier in terms of gain, power, linearity, noise

and bandwidth. So, the source degenerative amplifier is selected for implementation. The three stage

variable gain differential amplifier is implemented with selected architecture.

The implemented three stage variable gain differential amplifier have gain range of -541.5 mdB to

22.46 dB with step size of approximately 0.3 dB and total gain steps are 78. The -3 dB bandwidth

achieved is 953.3 MHz. The third harmonic distortion (HD3) is -45 dBc at 250 mV and the power is 35

mW at 1.8 V supply source.

Keywords

Transceiver, Analog, Amplifier, Linearity, Noise, Gain, Bandwidth, VGA, CMOS, HD3.

Language

English

Other (specify below)

Number of Pages 95 Type of Publication Licentiate thesis Degree thesis Thesis C-level Thesis D-level Report

Other (specify below)

ISBN (Licentiate thesis) ISRN: LiTH-ISY-EX--11/4543--SE

Title of series (Licentiate thesis) Series number/ISSN (Licentiate thesis)

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Abstract

The variable gain amplifier (VGA) is utilized in various applications of remote sensing and communication equipments. Applications of the variable gain amplifier (VGA) include radar, ultrasound, wireless communication and even speech analysis. These applications use the variable gain amplifier (VGA) to enhance dynamic performance.

The purpose of the thesis work is to implement a high linearity and low noise variable gain amplifier in 150 nm CMOS technology, for an analog-front-end of a transceiver. Two dif-ferent amplifier architectures are designed and compared. First architecture is an amplifier with diode connected load and second architecture is a source degenerative amplifier. The performance of the amplifier with diode connected load is lower than the source degenerative amplifier in terms of gain, power, linearity, noise and bandwidth. So, the source degenerative amplifier is selected for implementation. The three stage variable gain differential amplifier is implemented with selected architecture.

The implemented three stage variable gain differential amplifier have gain range of −541.5 mdB to 22.46 dB with step size of approximately 0.3 dB and total gain steps are 78. The −3 dB bandwidth achieved is 953.3 MHz. The third harmonic distortion (HD3) is −45 dBc at 250 mV and the power is 35 mW at 1.8 V supply source.

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Acknowledgement

I owe my deepest gratitude to almighty Allah, who blessed me with strength, determination and devotion to accomplish this thesis.

It is an honour for me to work in Fraunhofer Institute for Integrated Circuits (IIS). I am heartily thankful to my supervisor, Conrad Zerna for giving me this opportunity. He received me at my arrival in Germany and arranged a nice accommodation for me. He also guided me to solve the problems emerged during the thesis. This task would not have been possible without his support, encouragement and guidance.

I would like to thank my supervisor Dr J. Jacob Wikner, whose help, advice and supervision was invaluable throughout the thesis work.

I also wish to thank my friend and colleague Choudhary Jabbar Younis for his encouragement to do a thesis outside Sweden. He also helped me during thesis application process. We worked on same chip but different blocks. We had many cooperative discussions throughout our thesis work.

Finally, words alone cannot express the gratitude I owe to my family, especially my loving parents for their support and prayers.

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List of Abbreviations

VGA: Variable gain amplifier. AFE: Analog front end.

ADC: Analog to digital converter. SNR: Signal to noise ratio. DSP: Digital signal processor. PAM: Pulse amplitude modulation. EMI: Electromagnetic interference. AVGA: Analog variable gain amplifier. DVGA: Digital variable gain amplifier.

MOSFET: Metal oxide semiconductor field effect transistor. DFT: Discrete Fourier transform.

AC: Alternating current. DC: Direct current.

HD3: Third harmonic distortion. CMFB: Common mode feedback. dB: Decibel.

dBc: Carrier normalize decibel.

PMOS: P type metal oxide semiconductor transistor. NMOS: N type metal oxide semiconductor transistor. Vgs: Gate to source voltage.

R: Resistance.

gm: Transconductance.

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List of Figures

1.1 Block diagram of the transceiver. . . 8

1.2 Pulse amplitude modulated signal. . . 9

1.3 Testing of the common mode rejection using cable clamp. . . 10

2.1 Analog front end (AFE). . . 11

2.2 Gain control curves. . . 12

2.3 Thermal Noise. . . 13

2.4 Long channel MOSFET, thermal noise model. . . 14

2.5 Reduction of the gate resistance to minimize the noise. . . 15

2.6 Flicker noise spectrum. . . 15

2.7 Non linearity phenomenon. . . 16

2.8 Common source amplifier with source regeneration. . . 17

2.9 Analog-to-digital converter (ADC) block diagram. . . 21

3.1 Transistor level schematic of the differential amplifier with diode connected load. . . 23

3.2 Small signal model of the differential amplifier with diode connected load. . . 23

3.3 Half circuit, small signal model of the differential amplifier with diode con-nected load. . . 24

3.4 Transistor level schematic of the differential amplifier with diode connected load and CMFB circuit. . . 25

3.5 Gain curves of the differential amplifier with diode connected load and CMFB circuit in the corner analysis. . . 26

3.6 Schematic of the differential amplifier with source degeneration. . . 28

3.7 Small signal model of the differential amplifier with source degeneration. . . . 29

3.8 Half circuit, small signal model of the differential amplifier with source de-generation. . . 29

3.9 Gain curves of the differential amplifier with source degeneration in the corner analysis. . . 31

4.1 Block diagram of the three stage differential amplifier with output buffer. . . 35

4.2 Schematic of the coarse stage. . . 37

4.3 Gain curves of the coarse stage in the corner analysis. . . 38

4.4 Schematic of the fine stage with constant gm biasing. . . 41

4.5 Schematic of the constant transconductance biasing circuit. . . 42

4.6 Schematic of the amplifier used in the constant transconductance biasing circuit. 43 4.7 Schematic of the complete constant transconductance biasing circuit. . . 44

4.8 Gain curves of the fine stage with constant gm biasing in the corner analysis. 47 4.9 Gain setting curves of the fine stage with constant gm biasing in the corner analysis. . . 48

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5

4.10 Bandwidth curve of the fine stage with constant gm biasing in all gain settings. 49

4.11 Schematic of the fine stage with high speed biasing transistors. . . 50

4.12 Gain curves of the fine stage with high speed biasing transistors in the corner analysis. . . 52

4.13 Gain setting curves of the fine stage with high speed biasing transistors in the corner analysis. . . 53

4.14 Schematic of the fine stage with resized switching transistors. . . 54

4.15 Gain curve without resized switching transistors. . . 55

4.16 Gain curve of the fine stage with resized switching transistors. . . 55

4.17 Gain setting curves of the fine stage with resized switching transistors in the corner analysis. . . 56

4.18 Schematic of the output buffer. . . 57

4.19 Gain curves of the output buffer in the corner analysis. . . 58

4.20 Gain setting curves of the three stage variable gain differential amplifier with-out gain setting decoder. . . 60

4.21 Gain setting curves of the three stage variable gain differential amplifier with gain setting decoder. . . 60

4.22 Schematic of the offset compensation circuit. . . 61

4.23 Schematic of the first stage offset compensation amplifier. . . 62

4.24 Gain curves of the first stage offset compensation amplifier in the corner analysis. . . 63

4.25 Schematic of the second stage offset compensation amplifier. . . 65

4.26 Gain curves of the second stage offset compensation amplifier in the corner analysis. . . 66

4.27 Gain curves of the three stage variable gain differential amplifier with im-provements in the corner analysis. . . 68

4.28 Gain setting curves of the three stage variable gain differential amplifier with improvements in the corner analysis. . . 69

4.29 Bandwidth curve of the three stage variable gain differential amplifier with improvements. . . 70

5.1 Layout of the coarse stage. . . 72

5.2 Gain curves of the coarse stage layout in the corner analysis. . . 73

5.3 Layout of the fine stage. . . 74

5.4 Gain curves of the fine stage layout in the corner analysis. . . 75

5.5 Layout of the output buffer. . . 77

5.6 Gain curves of the output buffer layout in the corner analysis. . . 78

5.7 Layout of the three stage variable gain differential amplifier. . . 79

5.8 Gain curves of the three stage variable gain differential amplifier layout in the corner analysis. . . 80

5.9 Gain setting curves of the three stage variable gain differential amplifier layout in the corner analysis. . . 81

5.10 Bandwidth curve of the three stage variable gain differential amplifier layout in the corner analysis. . . 82

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List of Tables

3.1 Simulation results of the differential amplifier with diode connected load and

CMFB circuit in the corner analysis. . . 26

3.2 Simulation results of the differential amplifier with diode connected load and CMFB circuit in the montecarlo analysis. . . 27

3.3 Simulation results of the differential amplifier with source degeneration in the corner analysis. . . 30

3.4 Simulation results of the differential amplifier with source degeneration in the montecarlo analysis. . . 32

3.5 Comparison of the simulation results of two differential amplifiers. . . 33

4.1 Gain settings with corresponding bandwidth of the coarse stage. . . 37

4.2 Simulation results of the coarse stage in the corner analysis. . . 38

4.3 Simulation results of the coarse stage in the montecarlo analysis. . . 39

4.4 Simulation results of the constant gm biasing circuit in the corner analysis. . 45

4.5 Comparison of simulation results of the fine stage with and without the con-stant transconductance biasing circuit in the corner analysis. . . 45

4.6 Comparison of simulation results of the fine stage with and without the con-stant transconductance biasing circuit in the montecarlo analysis. . . 46

4.7 Simulation results of the fine stage with constant gm biasing in the corner analysis. . . 47

4.8 Simulation results of the fine stage with constant gm biasing in the montecarlo analysis. . . 48

4.9 Simulation results of the fine stage with high speed biasing transistors in the corner analysis. . . 51

4.10 Simulation results of the fine stage with high speed biasing transistors in the montecarlo analysis. . . 53

4.11 Simulation results of the fine stage with high speed biasing transistors in the montecarlo analysis. . . 56

4.12 Simulation results of the output buffer in the corner analysis. . . 58

4.13 Simulation results of the output buffer in the montecarlo analysis. . . 59

4.14 Simulation results of the first stage offset compensation amplifier in the corner analysis. . . 63

4.15 Simulation results of the first stage offset compensation amplifier in the mon-tecarlo analysis. . . 64

4.16 Simulation results of the second stage offset compensation amplifier in the corner analysis. . . 66

4.17 Simulation results of the second stage offset compensation amplifier in the montecarlo analysis. . . 67

4.18 Simulation results of the three stage variable gain differential amplifier with improvements in the corner analysis. . . 68

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4.19 Simulation results of the three stage variable gain differential amplifier with improvements in the montecarlo analysis. . . 69 5.1 Comparison of simulation results of the coarse stage schematic and layout in

the corner analysis. . . 72 5.2 Comparison of simulation results of the coarse stage schematic and layout in

the montecarlo analysis. . . 73 5.3 Comparison of simulation results of the fine stage schematic and layout in the

corner analysis. . . 75 5.4 Comparison of simulation results of the fine stage schematic and layout in the

montecarlo analysis. . . 76 5.5 Comparison of simulation results of the output buffer schematic and layout

in the corner analysis. . . 77 5.6 Comparison of simulation results of the output buffer schematic and layout

in the montecarlo analysis. . . 78 5.7 Comparison of simulation results of the three stage variable gain differential

amplifier schematic and layout in the corner analysis. . . 80 5.8 Comparison of simulation results of the three stage variable gain differential

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Chapter 1 Introduction

This master thesis presents the design of a variable gain amplifier (VGA) for an analog front end (AFE) of a high speed transceiver. The variable gain amplifier (VGA) is designed to keep the input amplitude of the analog-to-digital converter (ADC) in range. The designer keeps the linearity of the variable gain amplifier (VGA) high. The Variable gain amplifier (VGA) should also have low noise figure, so that the performance of the analog-to-digital converter (ADC) should not be degraded. Two amplifier architectures are designed on transistor level. The architecture with higher performance in terms of linearity, noise and bandwidth is chosen for implementation.

1.1 Overview of system

The block diagram of the system is shown in figure 1.1. The system consists of the following main building blocks.

• Transmitter. • Channel. • Receiver. PAM8 Transmitter AFE DSP Receiver Channel PAM8 6

Figure 1.1: Block diagram of the transceiver.

A digital signal is transmitted over the twisted copper pair channel and the noisy signal is received at the receiver by the analog front end (AFE). This noise is inserted by the channel. The analog front end (AFE) processes the received noisy signal to convert it into pure digital signal again and send it to the digital signal processor (DSP) for processing of the information. These blocks are discussed further in the following sections.

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CHAPTER 1. INTRODUCTION 9

1.2 Transmitter

The pulse amplitude modulated signal is transmitted over the channel by the transmitter. The pulse amplitude modulation is a technique of encoding information signal into amplitude of pulses. The differential pulse amplitude modulated signal (PAM-8) transmitted over the channel is shown in figure 1.2. This signal is called PAM-8, as it consists of eight different amplitude levels of a pulse. PAM-8 encodes three bits in a single pulse.

Figure 1.2: Pulse amplitude modulated signal. Bandwidth required for PAM-8 signal is given by the following equation 1.1.

BWP AM =

1 2Tsym

, (1.1)

where Tsym is the time period for one symbol. It is chosen for this system as it gives

efficient design with the 6-bit analog-to-digital converter (ADC). With increase in the levels of PAM signal, the SNR decreases and data rate increases. This increases the specification requirement on the variable gain amplifier (VGA) and the analog-to-digital converter (ADC).

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CHAPTER 1. INTRODUCTION 10

1.3 Channel

The channel is a twisted-pair copper wire. The twisted-pair cable have the ability to sig-nificantly cancel out the electromagnetic interference (EMI) induced in the channel from the external sources. This is called differential-mode transmission because the twisted-pair consist of equal and opposite signals, which are differential. The receiver detects that signal. The noise and EMI sources induces noise in the channel by coupling the electric or magnetic field, which induce same noise signal in both wires of the twisted-pair. Thus, the noise induced is common signal in the channel, which is suppressed by the differential receiver. This suppression of the common signal depends on the common mode rejection ratio of the input amplifier.

The common mode rejection ability of the receiver is tested by the cable clamp, as shown in figure 1.3. The cable clamp is a 300 mm long clamp used to induce wide band common mode voltage of amplitude 1 V and frequency 1 MHz to 1.6 GHz in the channel [1]. This common mode voltage is generated by the sweeping frequency of the signal generator, from 1 MHz to 1.6 GHz, connected to the cable clamp shown in figure 1.3.

Cable Clamp Twisted Pair T R A N S M I T T E R Twisted Pair Signal Generator 1 to 200 MHz @ 1V R E C E I V E R

Figure 1.3: Testing of the common mode rejection using cable clamp.

1.4 Receiver

The receiver consists of the following main building blocks shown in figure 1.1. • Analog Front End (AFE).

• Digital Signal Processor (DSP).

Analog front end (AFE) is an electronic circuit between the channel and the digital sig-nal processor (DSP). The AFE conditions the asig-nalog sigsig-nal received from the channel and performs the analog-to-digital (A/D) conversion. It is used in this project, to pro-duce every bit of the analog-to-digital converter (ADC) in the middle of the symbolic period. It consists of two main building blocks: A variable gain amplifier (VGA) and an analog-to-digital converter (ADC).

Digital signal processor (DSP) is a digital processor which is used to process the infor-mation received from the conditioned digital signal of the analog front end (AFE). It is used for equalization, non-linearity compensation, decoding, descrambling and for-ward error correction of the digital signal received from the analog-to-digital converter (ADC).

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Chapter 2 Analog Front End

The receiver consists of the analog front end (AFE) and the digital signal processor (DSP). The analog front end (AFE) conditions the analog signal received from the channel and converts it into a digital signal, for the digital signal processing (DSP).

V

G

A AD

C

Analog Front End

Receiver 5 6 Differential Input Digital Output Gain Control DSP

Figure 2.1: Analog front end (AFE).

Following are the main building blocks of the analog front end (AFE) shown in figure 2.1. • Variable gain amplifier (VGA)

• Analog-to-digital converter (ADC)

Variable gain amplifier (VGA) conditions the signal received from the channel to utilize full dynamic range of the analog-to-digital converter (ADC).

Analog-to-digital converter (ADC) converts this conditioned signal received from the variable gain amplifier (VGA) into the digital signal for the digital signal processing.

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CHAPTER 2. ANALOG FRONT END 12

2.1 Variable gain amplifier (VGA)

The variable gain amplifier (VGA) is utilized in many applications for decades, which in-cludes radar, ultrasound and wireless communication. The purpose of the variable gain amplifier (VGA) is to improve the dynamic performance. Broadly speaking, the variable gain amplifier (VGA) is used in two different situations. The first is to match the input signal level to full scale input level of a device like an analog-to-digital converter (ADC) or a FM-discriminator. The second in which the fixed input voltage is scaled to compensate variable losses, like transmission line voltage level adjustment.

The variable gain amplifier (VGA) is a signal conditioning circuit with adjustable gain. De-pending upon the nature of the gain control signal, the variable gain amplifier (VGA) is divided into two categories.

• Analog variable gain amplifier (AVGA) • Digital variable gain amplifier (DVGA)

The gain control in the analog variable gain amplifier (AVGA) is controlled by the analog voltage and the gain is linear function of the analog control voltage signal. The gain levels are continuous, as shown in figure 2.2(a).

The gain control in the digital variable gain amplifier (DVGA) is controlled by the digital control word and the gain levels are stepped as shown in figure 2.2(b).

0 0.2 0.4 0.6 0.8 1 1.2 15 10 5 0 5 10 15 20 Gain Linear in dB VGain (V) G ai n (d B) 0 1 2 3 4 5 6 15 10 5 0 5 10 15 Gain in discrete steps Gain Code G ai n (d B) 00001 00010 00011 00100 00101 00110 00000

(a) Gain versus Gain control voltage

0 0.2 0.4 0.6 0.8 1 1.2 15 10 5 0 5 10 15 20 Gain Linear in dB VGain (V) G ai n (d B) 0 1 2 3 4 5 6 15 10 5 0 5 10 15 Gain in discrete steps Gain Code G ai n (d B) 00001 00010 00011 00100 00101 00110 00000

(b) Gain versus Gain control code

Figure 2.2: Gain control curves.

The analog variable gain amplifier (AVGA) is compact in size as compared to the digital variable gain amplifier (DVGA). Whereas, in the digital variable gain amplifier (DVGA) different parameters of the gain control could be observed.

This project implements the digital variable gain amplifier (DVGA), which is used to adjust the level of the signal received from the channel.

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2.1.1 Design Challenges

In this project, there are few challenges, which the designer has to take care of during designing and implementation of the variable gain amplifier (VGA). These parameters are discussed following.

2.1.1.1 Noise

The noise is an unwanted signal, which degrades the performance of the system. It limits the signal level which could be processed by the system with acceptable quality. The noise is important for the analog design because it provides the trade-off between power dissipation, speed and linearity. Noise also degrades the dynamic range of the receiver [2]. The total noise figure, in a multi stage amplifier, is given by the Friis formula given below.

N F T = N F1+

N Fr+ 1

Av1

, (2.1)

where NFT is the total noise figure, N F1is the noise figure of the first amplifier, N Fris the

noise figure of rest of the amplifiers and Av1 is the gain of the first amplifier. This equation

shows that the gain of the first amplifier should be low for lower noise figure.

The analog signal in the variable gain amplifier (VGA) is corrupted by two types of noise. • Electronic device noise

• Environmental Noise

The electronic device noise is generated by resistors, transistors and other electronic devices. The environmental noise is random disturbance, which is experienced by the electronic

circuit through the supply lines or the substrate. 1. Thermal Noise

• Resistor thermal noise is generated due to the random motion of the electrons, which produces the fluctuation in the voltage across the resistor even in zero av-erage current [2]. The spectrum of the thermal noise is shown in figure 2.3(b). The thermal noise generated by the resistor can be modelled, by a voltage source in series as shown in figure 2.3(a).

- +

R Vn

2

Noiseless Resistor

(a) Equivalent resistive thermal noise source.

4KTR

f (Hz) Sv (f)

(b) Spectrum of the resistance thermal noise.

Figure 2.3: Thermal Noise.

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The thermal noise voltage of the resistor is given by the following formula [2]. ¯

Vn= 4kT R (V2/Hz), (2.2)

where k is the Boltzmann constant of value 1.38∗10−23J/K, T is the temperature in Kelvin and R is the resistance in ohms.

• MOSFET thermal noise is generated mostly by the channel. The noise model for a long channel device is shown in figure 2.4.

In2

logf (Hz)

20logV_n2

Figure 2.4: Long channel MOSFET, thermal noise model. The formula of the noise current source is [2]:

In= 4kRT γgm, (2.3)

where k is the Boltzmann constant of value 1.38x10−23 J/K, T is the tempera-ture in Kelvin, R is the channel resistance in ohms, γ is 2/3 for the long channel devices and approximately 2.3 for the sub-micron devices and gmis the

transcon-ductance of the MOSFET in 1/ohm. The channel noise can only be controlled by the transconductance of the MOSFET. As given by the formula that Inis directly

proportional to gm. The gate, drain and source terminals have finite resistivity

which also introduce the noise in the electronic circuits. In the wide transistors, the source and the drain resistances are negligible while the gate resistance may remain significant.

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The noise generated by the gate resistance is improved by the proper layout. An example is shown in figure 2.5. In figure 2.5(a) the gate resistance is reduced by connecting the gate terminal on both sides and in figure 2.5(b) the gate resis-tance is reduced by using the folded transistor. Each technique reduces the gate resistance by two times [2].

(a) Reduction of the gate resistance by connecting the gate terminals on both sides.

(b) Reduction of the gate resistance by the folded transistor.

Figure 2.5: Reduction of the gate resistance to minimize the noise.

2. Flicker Noise

The interface between the gate oxide and the substrate consists of many dangling bonds at extra energy state [2]. The charges moving at this interface, is trapped ran-domly and released, causing the flicker noise. This is believed that the trapping is not the only phenomenon for the flicker noise. The flicker noise is modelled by a series voltage source at the gate terminal of the MOSFET. The approximate formula for the flicker noise is [2]:

V_n2= K CoxW L

1

f, (2.4)

where K is the process dependent constant 10−25 V2_{F , C}

ox is the oxide capacitance

in farad, W is the width of the transistor in meters, L is the length of the transistor in meters and f is the frequency in hertz. By the above inverse relationship of the frequency, this noise is also called 1/f noise. This relationship is also shown, in the frequency spectrum of the flicker noise, in figure 2.6. The inverse relation of the WL suggest that to reduce the 1/f noise, the device size should be increased. Therefore, in the low noise circuits, the transistors having large area are used.

I_n2

logf (Hz)

20logV_n2

Figure 2.6: Flicker noise spectrum.

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2.1.1.2 Non Linearity

The phenomenon of the non linearity in the differential amplifier is shown in figure 2.7. As the signal amplitude increases, the non linearity comes into play [2]. At the small signal amplitudes, the output is approximately exact replica of the input but as the signal amplitude increases from certain limit, the amplifier exhibit saturation, which results in the non linearity as shown in figure 2.7.

(a) Small signal response of the dif-ferential amplifier.

(b) Large signal response of the differ-ential amplifier.

Figure 2.7: Non linearity phenomenon.

The analog circuit requires relatively small non linearity. The input/output characteristics of the amplifier could be approximated by the Taylor expansion as:

y(t) = α1x(t) + α2x2(t) + α3x3+ ... (2.5)

At small x,

y(t) = α1x(t), (2.6)

where α1is the small signal gain, in the vicinity of x ≈ 0. The non linearity of the amplifier

is also determined by measuring the harmonics of the output signal at the sinusoidal input. y(t) = α1Acosωt + α2A2cos2ωt + α3A3cos3ωt + ... (2.7)

By the above equation it is observed that the higher order terms results in the higher harmonics. These terms are cause of the harmonic distortion, which is quantified by the total harmonic distortion (THD). The total harmonic distortion is determined by summing all the harmonics and normalize the result with the power of the fundamental.

The input/output characteristics of the differential amplifier shows the odd symmetric and the Taylor expansion results in only the odd order terms, all the even order terms are zero as shown in the following equation.

y(t) = α1Acosωt + α3A2cos2ωt + α5A3cos3ωt + ... (2.8)

This is very important property of the differential amplifier, which shows that, it produces lower distortion then the common source amplifier.

For higher linearity of the multi stage amplifiers, the gain of the first stage should be low. This will secure the following amplifiers to be saturated and degrades the linearity of the circuit. But as discussed earlier, in the previous section 2.1.1.1, that higher the gain of the first stage, the lower the noise figure. So, there is a trade off in setting the gain of the multi stage amplifiers.

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• Linearisation Technique

The principle of the linearisation is to reduce the gain dependency of the amplifier on the input amplitude, by making the gain independent of the bias current. For high speed applications, the simplest method for the linearisation is the source degeneration. The source degeneration utilizes a linear resistor at the source terminal as shown in figure 2.8. This resistor reduces the swing at the gate to source, making the input/output characteristics more linear. R D R S Vout Vin VDD

Figure 2.8: Common source amplifier with source regeneration. The overall transconductance of the amplifier shown in figure 2.8 is :

Gm=

gm

1 + gmRs

, (2.9)

where the body effect is neglected.

Note that the linearisation depends upon gmRs not on Rs alone.

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2.1.1.3 Mismatch

The two identical MOSFETs during the fabrication suffers from the mismatch, due to un-certainty in the manufacturing process. This mismatch results in the random variations in the implant density and the oxide thickness [4]. These parameters result in variations in the lengths, widths, charge mobility, threshold voltage and oxide capacitance. The drain current of the MOSFET in the saturation is given by the following equation [2].

ID= 1 2µCox W L(VGS− VT H) 2 _(2.10)

The mismatch causes change in the drain current or the gate to source voltage of the identical transistors. It results in the following three phenomenons in the differential amplifiers.

1. DC offset.

2. Finite even order harmonic distortion. 3. Lower common mode rejection.

The mismatch can be reduced by increasing the length and the width. This decrease is due to the reduction in the relative mismatch with the increment in the length and the width. The decrease of the relative mismatch is due to the fact that with the increase of the area, the averaging of the random variation is higher. The mismatch could also be reduced by biasing the transistors in the weak inversion. In the weak inversion, the change of the output current, due to the input voltage, is small. So, the effect of the mismatch will be small. 2.1.1.4 Transistor type

The NMOS transistors are used as the input transistors. These transistors are high speed as compared to the PMOS. The 1/f noise produces by the NMOS does not effect this high speed design, because it has low amplitude at high frequencies. This is shown in figure 2.6. The bulk variations also does not degrade the performance in this design, as the bulks are connected to the supply voltage.

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2.1.2 Simulation Plan

The testing of the variable gain amplifier (VGA) is planned in the initial phase of this project, in which, the types of the test signal, the simulations to test the different parameters and the formula for these parameters are finalized.

After completing the circuit, ten simulations are performed in the nominal, corner and montecarlo with the different gain settings. The corner analysis is performed in the ten different corners. These corners use the supply voltage of 1.6, 1.7, 1.8 and 1.9 Volts. The temperature values used in the corners are: -40, 25 and 125. Different transistors, resistors and capacitors models are used in the different corners.

Following are the simulations used to test the variable gain amplifier (VGA). 2.1.2.1 Normal Operation Simulation

The following simulations use the sinusoidal test signal for the normal operation of the variable gain amplifier (VGA).

1. DC Simulation

The following parameters will be checked by the DC simulation.

• Power consumption is measured by multiplying, the value of the DC supply voltage source with the current drawn from that source by the amplifier. • Output common mode voltage is measured by taking the average of the

differential output voltage.

• Output offset voltage is measured by taking the difference of the output DC voltage.

• Operating regions of transistors is measured by the saved OP parameters, to check the correct overdrive and reserve voltages.

2. Transient simulation

The following parameters will be checked by the transient simulation.

• Third harmonic distortion is measured by using the DFT on the output signal at the input sine with frequency of 500 MHz and amplitude of 10 mV. Determines the magnitude of the third harmonic and subtracts it from the fundamental. • Output differential voltage is measured by taking the maximum difference of

the output voltage.

3. Transient and DC simulation

The following parameter requires the transient and the DC simulation during the testing.

• Input referred offset voltage is measured by dividing the output offset voltage by the gain of the amplifier.

4. AC simulation

The following parameters will be checked by the AC simulation.

• Bandwidth is measured by the −3 dB crossing of the output signal at high frequency.

• Lower cut-off frequency is measured by the −3 dB crossing of the output signal at low frequency.

• Transfer function is measured by the AC sweep from 0 to 10 GHz. 2.1. VARIABLE GAIN AMPLIFIER (VGA)

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• AC gain is measured by the sine input of amplitude 500 mV and frequency 10 MHz.

5. Noise simulation

The following parameter will be checked by the noise simulation.

• Input referred noise power is measured by integrate the noise spectrum over the normalized transfer function of the amplifier.

6. Parametric Transient

The following parameter will be checked by the parametric transient simulation. • Transient gain is measured by applying the input sine wave at frequencies: 100,

400 and 800 MHz with amplitudes: of 50, 350 and 600 mV. 7. Parametric Transient and DC

The following parameters will be checked by the parametric, the transient and the DC simulations.

• Output differential voltage is measured to check the waveform of the output voltage for the spikes.

• Gain is measured by changing the five bits digital control signal and apply the small DC input signal. This simulation is performed to check the output for the monotonicity, the step size and the gain range.

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2.2 Analog-to-digital converter

The analog-to-digital converter (ADC) is a device, which is used to convert the continues time analog signal into a digital signal. In this project, the analog-to-digital converter (ADC) is used to reproduce the digital signal transmitted over the channel by the transmitter. It is main building block of the analog front end (AFE). The signal conditioned by the variable gain amplifier (VGA) is received by the analog-to-digital converter (ADC) and is converted into a digital signal in such a way, that each bit is taken at the middle of its symbol period. This signal is then send to the digital signal processor (DSP).

Track And Hold _Com Encoder p ar at o r P re a m p li fi er A rr ay

Analog to Digital Converter Input conditioned

signal from VGA ₆₃ ₆₃ Digital output

Figure 2.9: Analog-to-digital converter (ADC) block diagram.

The analog-to-digital converter consists of the following main building blocks, also shown in figure 2.9:

• Track and Hold (TnH). • Pre-amplifier Array. • Comparator. • Encoder.

Track and Hold is a circuit, which track the input continues time analog signal for specific time period called tracking period and then hold its value after the tracking period for specified time period called hold period. The purpose of the track and hold in the analog-to-digital converter is to eliminate the variations in the input analog signal which corrupt the conversion process.

Preamplifier Array is an amplifier array, which includes the averaging and the interpo-lation. It is used to reduce the offset. It increases, the difference between the input sampled signal and the reference voltage, so that the comparator operation will not be in the metastable state.

Comparator is a circuit, which compares two signals and switches its output to show that which is greater. It receives the signal from the pre-amplifier array and produces one bit digital signal.

Encoder is a digital circuit, which converts one form of the code into another. It is used in the analog-to-digital converter (ADC) for the space saving.

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Chapter 3 Variable Gain Amplifier

Architectures

3.1 Introduction

There are two approaches, widely used to design the variable gain amplifier (VGA) [3]. • Translinear amplifiers.

• Exponential amplifiers.

Translinear amplifiers uses the diode equation, which gives the relationship between the junction current and the base voltage in a bipolar device. This is an exponential current-voltage relationship which is called translinear.

Exponential amplifiers consists of a precision-matched R-xR ladder attenuator and an interpolator, followed by a fixed gain amplifier. The relationship of the input and the output voltage is exponential.

3.2 Selected Architectures

Different research papers are studied and two differential amplifier architectures are selected for implementation on transistor level. These architectures are selected by observing different parameters of the variable gain amplifier (VGA). These parameters include: bandwidth, linearity, gain range, gain step, noise, gain error, power consumption and area. Higher priority is given to: bandwidth, linearity and gain range.

The two selected architectures are:

1. Differential amplifier with diode connected load. 2. Differential amplifier with source degeneration.

The first architecture is a translinear amplifier and the second is an exponential amplifier. These architectures are discussed in the subsequent sections.

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CHAPTER 3. VARIABLE GAIN AMPLIFIER ARCHITECTURES 23

3.3 Differential amplifier with diode connected load

First architecture designed is a differential amplifier with diode connected load. The differ-ential amplifier with diode connected is shown in figure 3.1.

Figure 3.1: Transistor level schematic of the differential amplifier with diode connected load. The biasing current is produced by the external biasing circuit. This amplifier provides the voltage gain, which is ideally independent of the temperature and the process variations [5]. The small signal model of the differential amplifier is shown in figure 3.2.

Figure 3.2: Small signal model of the differential amplifier with diode connected load.

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By the half circuit concept, above small signal model can be reduced to the following small signal model, shown in figure 3.3.

Figure 3.3: Half circuit, small signal model of the differential amplifier with diode connected load.

The voltage gain is determined by the small signal model, which is [5]:

Av= gm−input gm−load = s (W/L)_input (W/L)_load IC1 IC2 , (3.1)

where gm−input is the transconductance of the input transistors, gm−load is the

transcon-ductance of the load transistors, IC1is current in the input transistors and IC1 is current in

the diode connected load transistors. By above equation, it is noted that the voltage gain is ideally independent of the process and the temperature variations, but still, it depends upon the transistor size and the biasing currents. The transistor size and the current, changes with the process or the temperature. Also, by the above equation, it is observed that to in-crease the voltage gain, the diode connected load should have smaller size and lower current then the input transistors.

The linearity of the amplifier depends upon the current density. Linearity of this differential amplifier is low at small gain values because of the small current densities of the input and the load transistors.

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The differential amplifier with diode connected load is implemented on transistor level. This architecture has a drawback that the common mode output voltage level varies in the corner analysis. The gain variations are also increased by these changes of the common mode output voltage level over the corners. To solve this problem, the common mode feed-back (CMFB) circuit is used with this architecture. This differential amplifier with common mode feedback (CMFB) circuit is shown in figure 3.4.

Figure 3.4: Transistor level schematic of the differential amplifier with diode connected load and CMFB circuit.

In the above figure 3.4, there is an ideal amplifier used in the CMFB circuit. This ideal element is used to check the behaviour of the amplifier with the CMFB circuit.

The common mode feedback (CMFB) circuit utilizes a high gain amplifier, to keep the com-mon mode output voltage level within limit over all corners. The comcom-mon mode feedback (CMFB) circuit amplifies the difference between the average of the differential output and the reference voltage, which is “Vcm“ in this case [7], as shown in figure 3.4. The Vcm is the common mode voltage at the output of the differential amplifier. For the averaging of the differential output voltage, a resistor divider is used. Any change in the common mode output voltage is compensated by changing the biasing voltage of the PMOS transistors. In this way, the variations in the common mode output voltage are reduced.

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The simulation results of the differential amplifier with common mode feedback (CMFB) circuit in the corner analysis are given in the following table 3.1.

Table 3.1: Simulation results of the differential amplifier with diode connected load and CMFB circuit in the corner analysis.

Parameters Min Typ Max Stddev

Power consumption (W) 5.73 m 7.83 m 10.27 m 1.449 m

Output common mode voltage (V) 1.407 1.409 1.411 1.325 m

Transient Gain (Linear) 2.679 4.64 6.023 1.196

AC Gain (dB) 9.006 12.51 14.03 1.306

Bandwidth (Hz) 2.231 G 3.064 G 3.809 G 465.4 M

Third harmonic distortion (dBc) −45.76 −32.91 −25.98 7.586 Input referred noise power (dBc) −150 −145.1 −140.4 2.952

The gain curves in the corner analysis are shown in the following figure 3.5

Wed Nov 9 17:24:05 2011

Transfer_Function

Name Corner Vsupply temperature cornerNr Transfer_Function Transfer_Function C10 1.9 -40 10 Transfer_Function C09 1.6 125 9 Transfer_Function C08 1.7 125 8 Transfer_Function C07 1.9 -40 7 Transfer_Function C06 1.7 125 6 Transfer_Function C05 1.9 -40 5 Transfer_Function C04 1.9 -40 4 Transfer_Function C03 1.7 -40 3 Transfer_Function C02 1.7 125 2 Transfer_Function C01 1.8 25 1 ( d B ) -2.5 0.0 2.5 5.0 7.5 10.0 12.5 15.0 freq (Hz) 100 101 102 103 104 105 106 107 108 109 1010 Page 1 of 1

Figure 3.5: Gain curves of the differential amplifier with diode connected load and CMFB circuit in the corner analysis.

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The simulation results of the differential amplifier with common mode feedback (CMFB) circuit in the montecarlo analysis are given in the following table 3.2.

Table 3.2: Simulation results of the differential amplifier with diode connected load and CMFB circuit in the montecarlo analysis.

Parameters Min Mean Max Sigma

Power consumption (W) 6.334 m 7.253 m 8.325 m 373.9 u

Output common mode voltage (V) 1.41 1.41 1.41 40.3 u

Output Offset (V) −31.09 m −1.124 m 25.75 m 12.89 m

Transient Gain (Linear) 4.078 4.497 4.997 203.5

AC Gain (dB) 12.81 13.05 13.23 82.2 m

Third harmonic distortion (dBc) −31.51 −30.76 −30.21 241.5 m Input referred noise power (dBc) −149.7 −148.7 −148.8 349.2 m

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3.4 Differential amplifier with source degeneration

Second architecture designed is the differential amplifier with source degeneration. The dif-ferential amplifier with source degeneration is shown in the following figure 3.6.

Figure 3.6: Schematic of the differential amplifier with source degeneration. The source degeneration improves the linearity of the differential amplifier by reducing the gate to source voltage swing and making input/output characteristics more linear [2]. This differential amplifier with source degeneration have two tail current sources. One extra cur-rent source reduces the voltage headroom by the source resistor. It also increases the noise generated by the differential amplifier, which is a disadvantage of this architecture. Increase in the noise is due to the differential error produced by the two tail current sources.

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The small signal model of the differential amplifier with source degeneration is shown in figure 3.7.

Figure 3.7: Small signal model of the differential amplifier with source degeneration. Using the half circuit concept, above small signal model can be reduced into the following small signal model, shown in figure 3.8.

Figure 3.8: Half circuit, small signal model of the differential amplifier with source degen-eration.

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The voltage gain of the differential amplifier with source degeneration is derived from above small signal model, shown in figure 3.8. This voltage gain is given by the following formula by neglecting roof the input transistor:

Gm= gm 1 + gmRs . (3.2) Av= GmRD= gmRD 1 + gmRs , (3.3)

where gm is the transconductance of the input transistor, Rs is the source degeneration

resistance, RDis the drain resistance.

The above gain equation shows that, if the value of the resistance Rsand RDis large enough

then gain will depend only upon the ratio of RD/Rs. This makes the differential amplifier

independent of the process or the temperature changes. But in this thesis, Rs is not high

enough to use this approximation. This differential amplifier with source degeneration is implemented on transistor level.

Simulation results of this architecture in the corner analysis are given in the following ta-ble 3.3.

Table 3.3: Simulation results of the differential amplifier with source degeneration in the corner analysis.

Power consumption (W) 1.437 m 1.816 m 2.575 m 361.6 u Output common mode voltage (V) 1.118 1.401 1.554 142.7 m

Transient Gain (Linear) 2.582 3.672 4.593 753.4 m

AC Gain (dB) 8.524 11.47 13.71 1.961

Bandwidth (Hz) 5.635 G 6.943 G 9.185 G 1.131 G

Third harmonic distortion (dBc) −62.17 −55.12 −48.98 4.444 Input referred noise power (dBc) −146.1 −142.7 −137.7 3.13

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The gain curves in the corner analysis are shown in the following figure 3.9.

Thu Nov 10 12:23:35 2011 Transfer_Function Name Corner Transfer_Function Transfer_Function C01 Transfer_Function C02 Transfer_Function C03 Transfer_Function C04 Transfer_Function C05 Transfer_Function C06 Transfer_Function C07 Transfer_Function C08 Transfer_Function C09 Transfer_Function C10 5.0 10.0 15.0 ( d B ) -10.0 -5.0 0.0 101 102 103 104 105 106 107 108 109 1010 1011 freq (Hz) 100 Page 1 of 1

Figure 3.9: Gain curves of the differential amplifier with source degeneration in the corner analysis.

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Simulation results of this architecture in the montecarlo analysis are given in the following table 3.4.

Table 3.4: Simulation results of the differential amplifier with source degeneration in the montecarlo analysis.

Parameters Min Mean Max Sigma

Power consumption (W) 1.587 m 1.822 m 2.097 m 101.7 u Output common mode voltage (V) 1.341 1.4 1.452 22.33 m

Output Offset (V) -40.48 m -2.59 m 51.04 m 18.43 m

Transient Gain (Linear) 2.861 3.72 4.781 365.4 m

AC Gain (dB) 10.94 11.47 11.85 184.9 m

Third harmonic distortion (dBc) −60.2 −25.36 −11.34 9.624 Input referred noise power (dBc) −143 −142.7 −142.3 129.6 m

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3.5 Comparison of differential amplifier with diode

con-nected load and differential amplifier with source

degeneration

Following is the table for comparison of the two architectures, implemented on transistor level. In table 3.5, all values are for the worse case in the corner analysis, except the output offset which is the sigma value in the montecarlo analysis.

Table 3.5: Comparison of the simulation results of two differential amplifiers.

Parameters Architecture 1 Architecture 2

Power consumption (W) 10.27 m 2.575 m

Output common mode voltage (V) 1.407 1.118

Transient Gain (Linear) 2.679 2.582

AC Gain (dB) 9.006 8.524

Bandwidth (Hz) 2.231 G 5.635 G

Third harmonic distortion (dBc) −25.98 −48.98

Output offset (V) −31.09 m −40.48 m

Power Consumption is higher in the differential amplifier with diode connected load be-cause of an extra circuit for the common mode feedback (CMFB), as shown in fig-ure 3.4. Whereas, in the differential amplifier with source degeneration does not need the common mode feedback (CMFB). Also, the diode connected load consumes power too, which is not in the case of the differential amplifier with source degeneration. Another reason for increase in the power consumption is that, to get higher band-width and linearity, the biasing current is increased, which results in higher power consumption.

Output common mode voltage is more stable in the differential amplifier with diode connected load as it uses the common mode feedback (CMFB) circuit, shown in fig-ure 3.4. It reduces the variations in the output common mode voltage. This could be observed in the simulation results of table 3.1.

Transient Gain is higher in the differential amplifier with diode connected load as com-pared to the differential amplifier with source degeneration. It has high gain because of the PMOS at the drain terminal of the input transistor, as shown in figure 3.1. But the gain of the differential amplifier can be increased by reducing the bandwidth. Also, higher gain reduces the linearity.

Bandwidth is lower in the differential amplifier with diode connected load because of the loading at the output, by the diode connected transistors and the PMOS. Both reduces the bandwidth by increasing the capacitance at the output terminal.

Third harmonic distortion is higher in the differential amplifier with source degener-ation because of the source resistor used in this architecture. This source resistor reduces the gate to source voltage swing and makes the input/output characteristics more linear [2]. The simulations showed that the linearity of the differential amplifier with diode connected load could be improved by increasing the current density of the amplifier, which results in higher power consumption.

3.5. COMPARISON OF DIFFERENTIAL AMPLIFIER WITH DIODE CONNECTED LOAD AND DIFFERENTIAL AMPLIFIER WITH SOURCE DEGENERATION

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Output offset of the differential amplifier with diode connected load is small, as it have bigger transistors as compared to the differential amplifier with source degeneration. The increase in the size of the transistors, reduces the relative mismatch between the differential pair by increasing the averaging of the random variations.

3.6 Conclusion

The differential amplifier with source degeneration is preferred architecture because it has lower power consumption, higher gain bandwidth product and higher linearity. It is selected for the implementation of the variable gain amplifier (VGA) for the transceiver application. Although, output offset of this architecture is high as compared to the differential amplifier with diode connected load. To compensate this drawback, the offset compensation circuit will be used. It will reduce the offset by subtracting it at the input of the amplifier chain. The cost have to be paid for selecting this architecture is: the common mode voltage variations in the corner analysis and the noise generated by the tail current sources. Both of these values are within limits, so no need for improvement.

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Chapter 4 Three stage differential VGA

with resistive network and

source degeneration

4.1 Introduction

The three stage variable gain differential amplifier with output buffer is implemented in this master thesis. The block diagram of the three stage variable gain differential amplifier is shown in the following figure 4.1.

Offset Compensator

Coarse

Interface Fine 1 Fine 2 Buffer

Gain Setting Decoder

Variable Gain Amplifier

4 7 7 Coeff_valid Input Output 5 Gain_control OC_enable

Figure 4.1: Block diagram of the three stage differential amplifier with output buffer.

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CHAPTER 4. THREE STAGE DIFFERENTIAL VGA WITH RESISTIVE NETWORK

AND SOURCE DEGENERATION 36

It consists of a coarse amplifier stage followed by two fine amplifier stages, as shown in the above figure 4.1. A buffer is also implemented to drive the output load of the sample and hold circuit in the analog-to-digital converter (ADC). The coarse stage is a R-xR ladder attenuator with four gain setting bits. The fine stage is a source degenerative differential amplifier which is discussed in the previous section 3.4. It has seven gain setting bits. The buffer is also a source degenerative differential amplifier with unity gain.

The following circuits are also designed during this master thesis for the improvements of the variable gain amplifier (VGA).

• Constant gm biasing circuit. • Offset compensation circuit. • Gain setting decoder.

Constant gm biasing circuit is designed and implemented to bias the variable gain am-plifier (VGA), such that the gain variations over the corners are as small as possible. Offset compensation circuit is designed and implemented to minimize the offset of the

variable gain amplifier (VGA).

Gain setting decoder is a verilogA code used to map five bits of the input digital control signal to the seven bit digital control signal, for each fine stage. It sets the gain in such a way that it is monotonic and linear in dB.

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4.2 Coarse stage

This is a R-xR ladder based programmable attenuator. It reduces the input signal amplitude and also provides the input impedance matching. It has four gain control bits, which are used to select different attenuations. Each bit gives approximately −3.3 dB of attenuation. Maximum attenuation given by the coarse stage is approximately −9.8 dB. The circuit diagram of the coarse stage is shown in the following figure 4.2.

Figure 4.2: Schematic of the coarse stage.

The gain settings with corresponding bandwidth of the coarse stage are given in the following table 4.1

Table 4.1: Gain settings with corresponding bandwidth of the coarse stage. Sr. No. Din Ac Gain (dB) Transient Gain (Linear) Bandwidth (Hz)

1 1 −617.4 u 959 m 6.334 G

2 2 −3.306 659 m 4.29 G

3 3 −6.62 445.4 m 3.422 G

4 4 −9.848 299.4 m 2.614 G

Note that, at gain setting 1, the attenuation is not zero. This is because of the transistor switch in this path, as shown in figure 4.2.

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The simulation results in the corner analysis at worst case gain setting of Din = 8, are given in the following table 4.2.

Table 4.2: Simulation results of the coarse stage in the corner analysis.

AC Current (A) 10.04 m 11.25 m 12.75 m 936.7 u

Input Impedance (Ohm) 39.22 44.43 49.82 1.87

Output common mode voltage (V) 1.244 1.4 1.478 83.77 m

Transient Gain (Linear) 283.7 m 299.4 m 307 m 7.635 m

AC Gain (dB) −9.848 −9.848 −9.848 160.9 u

Lower cut-off frequency (Hz) 10.21 k 12.82 k 14.37 k 1.65 k Output voltage amplitude (V) 227 m 239.5 m 245.6 m 6.093 m Third harmonic distortion (dBc) −51.71 −50.94 −47.03 1.647 Input referred noise power (dBc) −150.5 −148.2 −145.7 2.017

Common mode rejection ratio (dB) 28.55 48.09 48.83 NA

The AC current is flowing in the differential inputs of the coarse stage. It is observed for the calculation of the input impedance. Also, note that there is a lower cut-off frequency. This is due to the external input coupling capacitance for interfacing the received signal from the channel.

The gain curves in the corner analysis at worst case gain setting of Din = 8, are shown in the following figure 4.3.

Sat Nov 19 18:14:00 2011 Transfer_Function Name Corner Transfer_Function Transfer_Function C01 Transfer_Function C02 Transfer_Function C03 Transfer_Function C04 Transfer_Function C05 Transfer_Function C06 Transfer_Function C07 Transfer_Function C08 Transfer_Function C09 Transfer_Function C10 ( d B ) -100 -75.0 -50.0 -25.0 0.0 104 105 106 107 108 109 1010 1011 freq (Hz) 100 101 102 103 Page 1 of 1 Figure 4.3: Gain curves of the coarse stage in the corner analysis.

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The simulation results in the montecarlo analysis at worst case gain setting of Din = 8, are given in the following table 4.3.

Table 4.3: Simulation results of the coarse stage in the montecarlo analysis.

AC Current (A) 11.24 m 11.25 m 11.26 m 4.182 u

Input Impedance (Ohm) 44.39 44.43 44.49 16.52 m

Output common mode voltage (V) 1.4 1.4 1.4 0

Input referred Offset (V) −743.9 a −29.71 a 743.4 a 348.4 a Transient Gain (Linear) 298.5 m 299.4 m 300.2 m 322.2 u

AC Gain (dB) −9.876 −9.849 −9.823 9.562 m

Lower cut-off frequency (Hz) 11.16 k 12.39 k 13.67 k 561 Output voltage amplitude (V) 238.8 m 239.5 m 240.2 m 257.8 u Third harmonic distortion (dBc) −70.07 −68.78 −67.85 423 m Input referred noise power (dBc) −148.2 −148.2 −148.2 11.03 m

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4.3 Fine stage

It is a differential amplifier with source degeneration. This architecture is discussed in the previous section 3.4. Only addition in the previous architecture is the gain setting network for the different gain settings. This network is at the source terminal of the input transistor, as shown in the following figure 4.4. It makes the gain of the fine stage variable.

Some parameters of the fine stage are improved. These parameters are:

• Minimize the variations of the gain in the corner analysis by the constant gm biasing. • Lower the minimum gain.

The following three versions of the fine stage are designed progressively. • Version 1: Fine stage with constant transconductance biasing. • Version 2: Fine stage with high speed transistors.

• Version 3: Fine stage with resized switching transistors.

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4.3.1 Fine stage version 1

This version of the fine stage improves the gain variations in the corner analysis. To reduce the gain variation, the Vgs over R biasing circuit is replaced by the constant transconduc-tance biasing circuit. This biasing circuit is discussed in the next subsection. The schematic of the fine stage version 1 is shown in the following figure 4.4.

Figure 4.4: Schematic of the fine stage with constant gm biasing.

Transistors in the gain setting network are used as switches to select different gain settings by the digital signal processor (DSP). These resistors and transistors are sized according to the power of two, as shown in the above figure 4.4. Every branch have transistor two times wider than the previous branch and resistors two times smaller than the previous branch.