A built-in current sensor using thin-film transistors
A A Hatzopoulos1, S Siskos2, C A Dimitriadis3, N Papadopoulos1, I Pappas 2 and L Nalpantidis2
Aristotle University of Thessaloniki, 54124 Thessaloniki - Greece
1 Dept. of Electrical and Computer Eng., Electronics Lab.,alkis@vergina.eng.auth.gr
2 Dept. of Physics, Electronics Lab., siskos@physics.auth.gr
3 Dept. of Physics, Microelectronic device characterization and design Lab..,, cdimitri@physics.auth.gr
Abstract. A simple current mirror using TFTs with input terminals which are capacitively coupled to the TFT gate, is used in this work, to design a built-in current sensor (BICS). The important feature in this application is that the voltage drop across the sensing TFT device can be reduced to almost zero value, while preserving transistor operation in the saturation region. This makes the proposed BICS appropriate for TFT applications without affecting the circuit operation. It also results in adequate linearity for the current monitoring, making the structure applicable to digital as well as to analog and mixed-signal circuit testing.
1. Introduction
Supply current testing, known as IDDQ testing in CMOS digital circuits, has been recognized for over 25 years now as an advantageous method supplementary to the conventional logic testing. It can reveal defects that are missed by logic testers. Various designs have been proposed in the last decade, especially for built-in current testing circuits [1-5]. Built-in current sensors (BICS) have certain advantages over the use of the Automatic Test Equipment (ATE): low application cost, high test rates, high resolution, improved circuit-under-test (CUT) observability and avoidance of the I/O parasitic. A major problem with all BICS is their influence to the normal operation and performance of the CUT. The voltage drop across the current sensing device is a considerable drawback of the BICS.
In recent years Thin-Film Transistors (TFTs) have found many applications [6, 7]. In this work the application of TFTs with input terminals, which are capacitively coupled to the TFT gate, in the design of a BICS is proposed. This structure with the capacitively coupled input terminals (CCIT- TFT) can be used as a variable threshold transistor. The first input terminal is used as the signal input of the structure and the second is used to control the threshold voltage. The important benefit from this application is that the voltage drop across the sensing device can be reduced to a small value, while preserving adequate linearity for the current monitoring. This linearity makes the proposed BICS also appropriate for analog and mixed-signal TFT circuit testing.
In the following, the TFT operation and circuit application is initially analyzed and results from the simulation of the proposed CCIT-TFT-BICS design are presented next. Discussion and remarks for further work are concluding the paper.
2. A Current Mirror Configuration
The polysilicon TFT drain current above threshold is given by [8, 9] equation (1), where µFET is the
Institute of Physics Publishing Journal of Physics: Conference Series 10 (2005) 289–292 doi:10.1088/1742-6596/10/1/071 Second Conference on Microelectronics, Microsystems and Nanotechnology
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gate voltage dependent field effect mobility and αsat accounts for the variation of depletion charge across the channel. In our application (AIM-SPICE model level 16) was utilized. The model
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V V L C W
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parameters used (according to ref. [7]) were: a) for the TFTp pmos level=16, CGDO=0.28e-15, CGSO=0.21e-15, vto=-6.4, tox=2.5e-8, asat=0.8, vkink=4.1, mus=5, muo=30; b) for the TFTn nmos level=16, CGDO=0.28e-15, CGSO=0.21e-15, vto=2.5, tox=2.5e-8, asat=0.8, vkink=4.1, mus=10, muo=100.
In case where two capacitively coupled input terminals are connected to the gate of the TFT, the drain current above threshold is proportional to the weighted sum of the input signals, since it will be:
VGS −VT =w1VIN1+w2VIN2 −VS −VT (2) The weight of each input signal is determined by the capacitive coupling ratio of the corresponding input.With proper selection of the coupling ratio w2 and using a corresponding bias voltage VIN2, we can have:
w2VIN2−VS −VT =0 (3)
This means that using the threshold-voltage controlling input IN2 with a proper bias voltage Vbias ≡VIN2, we can compensate for the threshold-voltage. This results in a CCIT-TFT structure, which can be driven by the VIN1 voltage starting from almost zero values. A large required transistor transconductance leads to a selection of a large value for w1. For small values of VIN1 the relation between ID and V IN1 can be considered approximately linear.
Using the 2-input CCIT-TFT we can design a current mirror, as shown in figure 1(a). The first CCIT- TFT1 has one of its inputs connected to its drain and to the corresponding input of the second transistor CCIT-TFT2, forming a current mirror configuration. The input (Iin) and output currents of the mirror are given in fig. 2, for input TFT with W/L=400/5 um and output TFT with W/L=20/5um, and C1=C3=2pF, C2=C4=4pF. The model used for the "floating node" of the gates is shown in figure 1(b) and it was adopted from ref. [10], with voltage-controlled voltage sources in proper configuration to bias the node. In this way, the dc convergence problems were overcome. The voltage drop Vds1 can be as low as 100 mV and it will not affect the CUT operation, when used as a “current sensing device”.
Based on the above, a 2-input CCIT-TFT can be used in current mirror configuration as a current sensing device for built-in current testing application (figure 3). The bias voltage Vbias is calculated to compensate for the threshold voltage. Since VDS1 =VIN1 for the CCIT-TFT1, the value of VDS1 can be kept quite low for the range of the ID current under consideration, by proper selection of the transistor transconductance and of the coupling ratio w1. Therefore, the voltage degradation of the CUT supply will be minimal, making this structure suitable for built-in current sensing applications.
The mirrored current in CCIT-TFT2 can be converted to a voltage by the use of a loading transistor. This voltage output, followed by an appropriate buffer or a latch, may be directly used as a fault indicating flag. The mirrored current can be downscaled for power saving by scaling the sizes of the transistors.
3. Simulation results of the BICS
Simulations were performed using the AIM-SPICE software and the polysilicon TFT model level 16.
A typical differential amplifier was utilized as a CUT. The differential pair was designed with TFTn, W/L=100/15 um and the active load with TFTp, W/L=20/15 um. The voltage drop of VDS1 can be
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kept very low (less than 70 mV), as it can be seen in fig. 4 for a current of about 70 uA, utilizing an aspect ratio of W/L=400um/5um for the TFT1. The supply voltage used was ±10V.
(a) (b)
Figure 1. (a)A simple current mirror using 2- input CCIT-TFTs
Figure 1. (b) The model used for the “floating node”
Iin
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time [sec]
60.0u 65.0u 70.0u 75.0u 80.0u
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Iout
0.0u 5.0u 10.0u 15.0u 20.0u22.0u
time [sec]
14.2u 14.4u 14.6u 14.8u 15.0u 15.2u
Current [A]
(b) Figure 2. Input and output currents of the mirror in figure 1 (a)
Voltage Drop
0.0u 5.0u 10.0u 15.0u 20.0u22.0u time [sec]
-9.940 -9.938 -9.936 -9.934 -9.932
Voltage [V]
Figure 3. The proposed BICS structure with 2- input CCIT-TFTs.
Figure 4. Voltage drop VDS of the “sensing”
TFT1.
Vout-diff (without) Vout-diff (with BICS)
0.0u 5.0u 10.0u 15.0u 20.0u
time [sec]
-3.0 -2.0 -1.0 0.0 1.0 2.0 3.0
Voltage [V]
(a)
Vout-diff (without) Vout-diff (with BICS)
10 4 10 5 10 6 10 7
frequency [Hz]
0.0 2.0 4.0 6.0 8.0
Voltage [V]
(b) Figure 5. a) Time domain response of the diff.
amplifier with and without the BICS,
Figure 5. b) Frequency domain response of the diff. ampl. with and without the BICS.
This voltage drop is mainly responsible for the degradation of the CUT performance. VDS can be kept minimal by proper sizing the TFT1, according to the data taken from V-I characteristics for various aspect ratios W/L. The negative influence to the circuit performance can be reduced by resizing the aspect ratios of the TFTs, at a cost of a larger silicon area, since the use of larger transistorsin
Vbia
Vbia
Out VD
TFT1
TFT2 Rlo
Iin
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C
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TFT1
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VSS VSS
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corporates the drawback of increased silicon area overhead. Comparative responses for the diff.
amplifier with and without the BICS in time domain and in frequency domain are given in fig. 5, showing the negligible influence of the BICS to the circuit performance. The relation between Vout of the BICS and the supply current of the CUT is plotted in figure 6, showing excellent linearity.
With proper calculation of the TFT2 and the loading transistor aspect ratios, and with the use of a window comparator, the value of this voltage can be translated to a pass/fail flag. This flag would indicate whether the quiescent current of the CUT remains within acceptable limits.
'v(15)'
20.0u 40.0u 60.0u 80.0u 100.0u
'id(m5)' [A]
6.725 6.730 6.735 6.740
V(15) [V]
Figure 6. BICS voltage output versus supply current of the CUT.
4. Discussion and Further Work
The proposed CCIT-TFT-BICS has the advantage of a small voltage drop across the sensing device, while preserving transistor operation in the saturation region. This feature makes it applicable to TFT circuit monitoring. It is also appropriate for analog and mixed-signal TFT circuit testing, due to its very good linearity. A fixed resistor can replace the loading transistor, in case of a small resistance value or in case where the output is left as an “open collector” configuration.
Better performance of the current mirror can be achieved by appropriate layout of the devices (for example, using fingering techniques).
The problems with the statistical variation of the VT of the TFTs can be coped with a proper selection of the Vbias voltage, such that to compensate for the worst case of VT (maximum VT), at the cost of a higher power consumption of the BICS structure.
The influence of the component mismatches and of the second-order effects on the performance of the proposed TFT-BICS is currently under investigation.
5. Acknowledgment
The authors would like to thank the Greek Ministry of Education for the partial financial support of this work in the frame of the “PYTHAGORAS” research project.
6. References
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[4] Kim J B, Hong S J and Kim J 1998 IEEE JSSC 33 8 1266-1272
[5] Hatzopoulos A A, Iatrou E, Katsaras C and Papakostas D K 1998 IEE Proc., Pt. G: Circuits, Devices and Systems 319-324
[6] Yang H-G, Fluxman S, Reita C, and Migliorato P 1994 IEEE JSSC 29 6 [7] Lewis A G, Lee D D and Richrdson H B 1992 IEEE JSSC 27 12
[8] Jacunski M D, Shur M S, Owusu A A, Ytterdal T, Hack M and Iniguez B 1999 IEEE TR. on Electron Devices 46 6
[9] Shur M et al 1997 J. Electrochem. Soc. 144, 8, pp 2833-2839
[10] Angulo J R, Altamirano G G and Choi S C 1997 in IEEE Proc. Int. Symp. on Circuits and Syst. (ISCAS'97) pp. 2020-2023
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