Input interface requirements on board mounted DC/DC converters

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This degree project has been carried out on behalf of the department of Power Modules at Ericsson.

Supervisor at Ericsson: Anders Petersson

Krav på ingångsgränssnittet till kortmonterade DC/DC-omvandlare

ALEXANDRA CRONEBÄCK

Degree project, in Electrical engineering, second level Supervisor at KTH: Elias Said Examiner: Thomas Lindh School of Technology and Health TRITA-STH 2013:33 Royal Institute of Technology School of Technology and Health

136 40 Handen, Sweden http://www.kth.se/sth

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Abstract

This thesis has been carried out on behalf of the department of Power Modules at Ericsson.

In a telecom system interface A is a physical point between the power supply system and the telecommunication equipment described in a European standard called ETSI EN 300 132-2. This interface is also described in the American standard ATIS-0600315.2007. For board-mounted products, such as DC/DC converters, a well-defined input interface description is lacking.

The goal of this thesis was to evaluate if the requirements in the standards ETSI EN 300 132-2 and ATIS-0600315.2007 are viable for the input interface of DC/DC converters. A part of this goal was also to investigate and analyze how the systems, in which the DC/DC converters operate, works.

To be able to determine if any of the two standards, ETSI and ATIS, are viable for use for the input interface, both were reviewed and described with focus on voltage levels and transients.

In the information gathering phase it became clear that an extended limitation was needed. Therefore, in order to investigate what happens from interface A to the input interface of DC/DC converters, the system used in this thesis is the EBS LOD (Ericsson Blade System – Low Ohmic Distribution). EBS is one of the systems in Core sites.

The report describes the construction of EBS where in the PFM (Power Fan Module), backplanes and various boards are important parts. Furthermore some key principles within Core sites, such as HOD (High Ohmic Distribution), LOD, Two-wire system and Three-wire system, are also described in order to explain how the EBS system works.

EBS (including PIM (Power Interface Module)) was modeled in OrCad PSpice, with both one board and 26 boards, and was simulated with different transients at an input to the system. The simulation results show that the high voltages never reach the DC/DC converter and that they therefore are well protected from transients in an EBS LOD system.

In order to determine whether the standards ETSI and ATIS are viable for the input interface of DC/DC converters, it is concluded that more investigations, tests and simulations are needed.

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Sammanfattning

Detta examensarbete har utförts på uppdrag av avdelningen Power Modules på Ericsson.

I ett telekommunikationssystem är gränssnitt A en fysisk punkt mellan kraftsystemet och

telekomutrustningen som beskrivs i en europeisk standard som kallas ETSI EN 300 132-2. Detta gränssnitt är också beskrivet i den amerikanska standarden ATIS-0.600.315.2007. För kortmonterade produkter, såsom DC/DC-omvandlare, saknas en beskrivning av ett väldefinierat ingångsgränssnitt.

Målet med detta examensarbete var att utvärdera om kraven i standarderna ETSI EN 300 132-2 och ATIS-0.600.315.2007 är applicerbara på ingångsgränssnittet till DC/DC-omvandlare. En del av detta mål var också att utreda och analysera hur systemen, i vilka DC/DC-omvandlare finns, fungerar.

För att kunna avgöra om de två standarderna ETSI och ATIS var applicerbara, granskades de och beskrevs med fokus på spänningsnivåer och transienter.

I informationsinsamlingsfasen stod det klart att en utökad avgränsning behövdes. Slutsatsen av denna begränsning var att systemet som skulle användas i detta examensarbete var EBS LOD (Ericsson Blade System – Low Ohmic Distribution), för att undersöka vad som händer från gränssnittet A till ingångsgränssnittet av DC/DC omvandlare. EBS är ett av systemen inom Core sites.

I rapporten beskrivs konstruktionen av EBS där PFM (Power Fan Module), backplan och olika kort anges som viktiga delar. Dessutom beskrivs några viktiga principer inom Core sites, såsom HOD (High Ohmic Distribution), LOD, Två-ledar-system och Tre-ledar-system.

EBS (inklusive PIM (Power Interface Module)) modellerades i OrCad Pspice, med både ett kort och 26 kort, och simulerades med olika transienter på en av ingångarna till systemet. Simuleringsresultaten visar att de höga spänningarna aldrig når DC/DC-omvandlaren och att dessa alltså är väl skyddade mot transienter i ett EBS LOD system.

För att kunna avgöra om standarderna ETSI och ATIS är applicerbara på ingångsgränssnittet till DC/DC-omvandlare är slutsatsen att flera utredningar, tester och simuleringar behöver göras.

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Acknowledgements

I would like to thank Anders Petersson, my supervisor at Ericsson, for his support and contribution of knowledge to this thesis. I would also like to thank Åke Ericsson, for contributing valuable

information about Core sites, and Mattias Andersson, for advices and help with simulations. And last but not least I want to thank Elias Said, my supervisor at KTH STH, for giving me advice and guidance during this thesis and feedback to the report.

Alexandra Cronebäck Stockholm, May 2013

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1 Abbreviations

BSC – Base Station Controller

CMXB – Component Main Switch Board DC – Direct Current

EBS – Ericsson Blade System

EGEM2 – Evolved Generic Ericsson Magazine 2

EPDU/PDU – Enclosed Power Distribution Unit/Power Distribution Unit HOD – High Ohmic Distribution

LOD – Low Ohmic Distribution PDF – Power Distribution Frame PFM – Power Fan Module PIM – Power Interface Modules RBS – Radio Base Station RNC – Radio Network Controller SCXB – System Control Switch Board

SGSN-MME – Serving GPRS Support Node – Mobility Management Entity TVS – Transient Voltage Suppression

TLE – Telecommunications Load Equipment

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2 Introduction

This thesis has been carried out on behalf of the department of Power Modules at Ericsson.

2.1 Background

Ericsson is a world-leading provider of telecommunications equipment and related services to mobile and fixed network operators globally.

Ericsson has a department specialized in developing power modules. Their board-mounted products can be divided into DC/DC converters, intermediate bus converters (IBC), Point Of Load (POL) regulators, Power Interface Modules (PIM) and Board Power Management (BPM) supporting product.

The products are primarily designed for telecom and datacom systems, such as radio base stations and switches/routers, but they are also used in medical and industrial applications, among other branches (1).

In a telecom power distribution system different interfaces are described in standards. One of these standards is ETSI EN 300 132-2. The interface described there is called interface A and is a physical point between the power supply system and the power consuming telecommunication equipment, see Figure 1 (2). However, for board-mounted products, such as DC/DC converters, a well-defined input interface description is lacking.

Today, when developing power modules in general and DC/DC converters in particular there are no standards specified for the input interface, instead past developing references combined with specified demands has been used to verify the requirements of each power module.

Figure 1: Where to find interface A and the input interface of a DC/DC converter.

The question mark represents undefined parts of the system. [1]

2.2 Problem definition

This thesis has investigated how the European standards ETSI EN 300 132-2 works and if the requirements in this standard are viable to use also for the input interface for DC/DC converter in telecom and datacom systems. Since Power Modules deals a lot with the American market, the American standard ATIS-0600315.2007 has also been investigated. ATIS and ETSI are the most common standards used for interface A around the world.

DC Power Supply

Telecom equipment Interface A

System block

Telecom equipment

System block Interface A

DC/DC converter Input interface DC power supply conductors

Distribution &

protection

?

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The thesis has been looking into this from different angles regarding relevant requirements such as:

 Power Line Disturbances

 Voltage Spikes

 Current Ripple

 Inrush current

 Relevant steady state voltage requirements

 Earthing and bonding and the difference between two-wire and three-wire distribution system (if any)

 Other aspects that may have been relevant.

2.3 Goals

The goal of this thesis was to evaluate if the requirements in the standard ETSI EN 300 132-2 and the standard ATIS-0600315.2007 are viable for the input interface of DC/DC converters or if there were any other relevant standards that could be used. This information in turn may be used by Ericsson for future designs guidance when developing DC/DC converters and as a reference for an application note.

A part of the goal in this thesis was also to investigate and analyze how the systems, in which the DC/DC converters operate, works. This includes analyzing feeds to the inputs to the DC/DC converters and how well protected the converters are in the systems.

2.4 Delimitations

This thesis has been limited to investigate DC/DC converters in telecom and datacom systems. During the process of working with this thesis further delimitations has been included. These delimitations are described in 7.2 Extended delimitations.

2.5 Methods

To gather information for this thesis following methods has been used.

 Literature studies of the different standards.

 Literature studies of different systems at Ericsson.

 Interviews with relevant co-workers at Ericsson.

When sufficient information has been gathered simulations (in OrCad PSpice) has been executed and results have been analyzed throughout the process.

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3 Standards

As described in the introduction the standards ETSI EN 300 132-2 and ATIS-0600315.2007 plays an important role in this work. This section discusses the key points of these two standards.

3.1 Standard from ETSI

The standard ETSI EN 300 132-2 is a European Standard (EN) and is produced by ETSI Technical Committee Environmental Engineering (EE).

This standard describes the requirements for the interface between telecom and datacom (ICT) equipment and its power supply, also called interface A. The standard is not only used for providing electrical compatibility at this point, it is also used for different system blocks connected to the same power supply.

The reason for a need of a standard for this interface is to secure the usage of the same characteristics for all telecom and datacom equipments. This makes it easier for different load units to interwork and makes the installation, operation and maintenance of equipment/systems from different origins simpler.

3.1.1 Requirements

In ETSI EN 300 132-2 the requirements are defined as followed (2, page 6):

 the output of the power supply equipment or power supply installation of telecommunications centers providing power at the interface "A";

 the power supply input of any type of telecommunications and datacom (ICT) equipment installed at telecommunication centres that are connected to interface "A" powered by DC;

 any type of telecommunications and datacom (ICT) equipment, installed in access networks and customers' premises, the DC interface "A" of which is also used by equipment requiring a supply to the present document.

 any type of telecommunication and datacom (ICT) equipment powered by DC, used in the fixed and mobile networks installed in different locations as building, shelter, street cabinet.

Figure 2: Definition of interface A [2].

Telecom equipment

System block Interface A

DC power supply conductors

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6 3.1.1.1 Voltage levels

In ETSI it is stated that the nominal voltage at interface A shall be -48 VDC, it is negative because the positive conductor is connected to earth.

It is also stated that the normal service voltage range for this system shall be -40.5 VDC to -57.0 VDC at interface A. That is the range where the system operates most of the time and there should not be a degradation of service performance at this range.

The range where the equipment is not expected to maintain normal service but will survive undamaged is called abnormal service voltage range. This voltage range at interface A is found in Table 1.

From (VDC) To (VDC)

0.0 -40.5

-57.0 -60.0

Table 1: Abnormal service voltage range for a -40 V_DC system.

When the supply is back to normal voltage range, the telecommunications and datacom equipment shall resume operating according to its specifications. The power supply shall not have been disconnected by operations of e.g. circuit breakers or fuses.

-60 VDC systems

If a -60 VDC system is used some of the requirements at interface A will change. The nominal value of the supply voltage shall be -60.0 VDC and the normal service voltage range shall be -50.0 VDC to -72.0 VDC.

The abnormal service voltage range is found in Table 2 (2).

From (VDC) To (VDC)

0.0 -50.0

-72.0 -75.0

Table 2: Abnormal service voltage range for a -60 VDC system.

3.1.1.2 Voltage transients

One reason for transients at interface A is when faults occur in the power distribution system, which can be e.g. a short circuit of the negative conductors to any earthed part of the equipment (3). This sort of transients is characterized by a voltage drop in the range: 0 VDC to -40.5 VDC, and then an

overvoltage with a value over the maximum steady state abnormal service voltage range.

If a voltage transient has occurred the equipment shall continue to function, without manual

intervention, within its operational specification and the equipment should not have been disconnected from the power supply by operation of circuit breakers and fuses.

To make the power supply system more secure some minor arrangements may be needed, for

example dual feeding system, high-ohmic distribution system and independent power distribution (2).

The following information about voltage transients are described in a technical report, ETSI TR 100 283, referenced in the ETSI standard.

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7 Power distribution

It is common that the equipment in telecommunication centers has a backup battery in case of a mains failure. A problem with these batteries are that they can store a very large amount of energy, which can result in a delivery of currents far in access of the ratings of fuses and circuit breakers under fault conditions.

In a typical power distribution system (see Figure 3) in a large installation, current is supplied from both the power plant and battery. Furthermore this current is broken down into a number of lower current feeds at each Power Distribution Frame (PDF). Given that the feeds have a lower current, the power cable which supplies the PDFs are sized according to the current they have to carry as well as the voltage drop that can be tolerated. These cables are also protected by suitably rated fuses or breakers in each PDF.

Figure 3: A power distribution with only the negative conductors [3].

Description of transients

In branches of the distribution that is not associated with the fault a voltage transient can occur, it can for example be a branch sharing the same secondary PDF as the branch with the fault. This transient can be divided into two parts, the first part begins when the error occur (t0, see Figure 4) and ends when the protection device clears (t1). The second part begins where the first part ends and finishes when the voltage returns to its value before the fault was applied (t2).

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Figure 4: Waveforms of a voltage transient and a current transient [4].

Part 1 (t0 to t1): Initially there is a large voltage drop, se voltage curve in Figure 4. This drop is caused by inductance in the parts of the fault circuit that are shared with the branch in question and the duration off this drop depends on the value of the inductance. If the value of the inductance is small the voltage will recover quickly. If the inductance value is large then the fault current might not reach the value limited by the resistance in the cables from the battery. If this happens the fuse may clear the fault circuit before it reaches the determined optimal value.

To reduce the fault current and voltage drop, cables with different sizes and resistances can be used to apportioning the resistance.

Part 2 (t1 to t2): When the fault circuit is open there is a higher flow of current in the cables. The energy created by this higher flow of current needs to gradually reduce without harming the equipment connected to the power distribution. This increase in energy is possible to absorb with the capacitances distributed over the power distribution. These capacitances may i.e. be placed in the PDFs or by the entrance to the DC/DC converters. This is made to create a “hold up” function during part one of the transient. Another way to make the energy disperse faster is to use absorbing transients units. These units will then works as zener diodes to quickly absorb the energy. These zener diodes are placed over the positive and negative conductor (3).

3.1.1.3 Protection of a power supply

To protect the power supply at interface A, circuit breakers, fuses and equivalent devices can be used.

These protection devices are defined with a current value of 1.5 times Im (maximum steady state input current, stated by the manufactures). These definitions are made to avoid that the normal service voltage range is affected by the protection devices (2).

A difference between fuses and circuit breakers is the reaction speed to fault currents.

To break a current with a higher value than the stated one, the fuse needs time, and the higher the current the faster the fuse will reach is meltdown and execute. Although even if the values of the current are extremely high the fuse will still have a limited execution time. These execution times may vary between 1 ms to 10 ms depending on design of the fuse and the level of the current.

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Circuit breakers react differently to higher currents than fuses do. In the case of circuit breakers the issues is the inertia of the breakers mechanics and connections which determines the time to clear the higher current. The execution time for the circuit breakers is, compared to fuses, longer and spans between 4 ms to over 15 ms (3).

3.1.1.4 Inrush current

To set a limit for the inrush current a ratio between the inrush current (It) and maximum steady state current (Im) at interface A is used. Figure 5 shows the limits that the ratio shall not exceed when the voltage is within the normal service range. The criteria are summarized in ETSI EN 300 132-2 as followed (2, page 13):

 Below 0.1 ms, the inrush current is not defined.

 Below 0.9 ms the I_t/I_m ratio shall be lower than 48.

 Above 1 ms: the curve corresponds to the maximum tripping limit of majority of existing protective devices.

Figure 5: Ratio of the inrush current (I_t) and the maximum steady state current (I_m) [5].

3.2 Standard from ATIS

The ATIS standard ATIS-0600315.2007 “Voltage levels for DC-powered equipment used in the telecommunications environment” is an American National Standard produced by the Alliance for Telecommunications Industry Solutions (ATIS) and approved by American National Standards Institute, Inc (ANSI).

This standard does not use the expression interface A, instead they refer to telecommunications load equipment (TLE). TLE is an equipment powered by a DC power system with a primary or secondary distribution.

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10 3.2.1 Voltage levels/Voltage requirements

A -48 volts TLE shall meet its operational requirements with following values:

Nominal voltage Maximum VDC Typical VDC Minimum VDC

-48 -40.0 -53.0 -56.7

Table 3: Steady state voltages.

If the TLE is exposed to a voltage between 0 VDC and the maximum voltage level or a voltage between 0 VDC and the minimum voltage level it shall not be permanently damaged or have its performance degraded. The equipment shall restart automatically after the voltage is returned to a level under -48 VDC without manual intervention.

3.2.1.1 Cutoff and recovery

The equipment shall have a built in function that will turn the equipment off if the voltage at the input goes over -38.5 VDC (±1.0 VDC) for more than 10 seconds, or reduce the power that the equipment utilizes with less than 20 % over -38.5 VDC (±1.0 VDC).

The equipment shall remain in these states until the voltage has returned to a level of -45 VDC (±3.0 VDC), unless the voltage is between 0 and -20 VDC for more than 20 ms, then it is allowed to recover at voltages larger than -38.5 VDC (±1.0 VDC).

The cutoff and recovery shall not permanently damage the equipment or degrade the performance of it. It shall also not cause fuses or circuit breakers to operate. The equipment shall recover to normal operation within 30 minutes as a standard without manual intervention.

3.2.1.2 Transients

A TLE with an overvoltage transient of -75 VDC, a reasonable worst case scenario, applied between the input terminals shall continue to operate properly, and shall not be damaged or degraded in

performance. The following requirements shall be met:

 A rise and fall time of 10 VDC/ms (±1.0 VDC)

 Rise and fall rates measured at 10 % and 90 % points.

 A duration of 9.5 ms (±0.5 ms)

Transients from protective device operation

As pointed out in the section of the ETSI standard transients can occur because of operations of protective devices. In ATIS the total protective device operation transient is described with a figure, see Figure 6. At first, the voltage drops from 50 V to 5 V, after around 10 ms there is an impulse transient to the level of 100 V. After 50 µs the voltage drops to 75 V and after around 10 ms the voltage is back to 50 V (4). Notable is that the voltage in the figure is positive, but the same curve can be used for negative values.

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Figure 6: Total protective device operation transient [6].

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4 System

In order to simulate and analyze what happens from interface A to the input interface of Power Modules DC/DC converters, an identification of different systems must be made and an examination of what components the systems contains. Two of the areas where DC/DC converters are used are Radio Base Stations (RBS’s) and Core sites. This thesis has been concentrated on the Core sites.

4.1 Core site

Core site products ranges from cabinet solutions, to secure power supply and cables, where all

products are standardized. This makes the installation for a complete Core site easier and the reliability higher. The products are developed parallel with different network nodes, enabling a support for e.g.

controllers, Base Station Controller (BSC), Radio Network Controller (RNC), EVO, Media Gateways, GPRS nodes and circuit-switched nodes (5).

Ericsson Blade System (EBS) is a system used for several applications in Core. Before the description of the EBS, some important key principles will be explained, that are different distributions and wire arrangements.

4.1.1 HOD & LOD

There are two principles which are mainly used in a -48 VDC telecommunication system, the High Ohmic Distribution (HOD) and the Low Ohmic Distribution (LOD). These systems are quite different in terms of structure, but they both fulfill requirements such as electromagnetic compatibility (EMC), reliability, basic safety requirements etc. Both principles also meets standards such as ETSI and ANSI, and has a full service input voltage range between approximately -40 to -57 VDC .

4.1.1.1 HOD

The HOD principle (see Figure 7) has a 30 mΩ (Rstrip) resistor in series with a circuit breaker (15 A for 500 W and 30 A for 800 W) at the output of the -48 VDC power plant. With the help of Rstrip HOD can maintain the output voltage from the power plant within the normal service range (-40.5 VDC to -57.0 VDC) during the period of a transient before a circuit breaker operates. This means that the HOD- arrangement will make sure that the voltage never will drop below -43 VDC at short circuits and overloads.

Figure 7: The HOD principle [7].

Rstrip 30 m 30 A

RB

AC DC

Cabinet A-feed

B-feed Ω

Ω

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13 More features of the HOD-system:

 The size of a short circuit current is limited to maximum 1 kA.

 A great advantage with HOD is: If a single fault occurs in the system, only a limited part is affected. This means that the part of the system that is not affected can continue to function as usual. The same applies if a part of the system is totally knocked out.

 A HOD system can never be connected directly to a LOD system. This has been solved with an adapter, an EPDU/PDU (Enclosed Power Distribution Unit/Power Distribution Unit), which is placed between the systems and converts LOD to HOD.

 HOD with the power 500 W has been Ericsson's standard power since the 1970s but from year 2000 the power has increased to 800 W. This is an upper limit due to power loss and a large voltage drop across the 30 mΩ resistor.

4.1.1.2 LOD

The LOD principle (see Figure 8) has a hold-up capacitor by the input to the telecommunication equipment. This is needed if there, as an example, is a short circuit, since the voltage from the power plant will drop below -40 VDC in an LOD system. With the help of a blocking diode the hold-up capacitor will maintain the voltage above lower limits during the 10 ms of a transient until the circuit breaker operates. The size of a short circuit current can be 3-5 kA.

More features of the LOD-system:

 Since there are no requirements for a resistor and a circuit breaker at the output of the power plant, there is a larger freedom at this stage.

 A current limiter is needed to keep the inrush current from the capacitor on an acceptable level.

 The overall efficiency will be reduced because of the continuous power loss in the blocking diode during normal service.

Figure 8: The LOD principle [7].

Cabinet 250 A

250 A

60 A

60 A C

RB

AC DC

A-feed B-feed

Hold up capacitor &

blocking diode

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14 4.1.2 Two-wire or three-wire system

The choice between a two-wire or three-wire power arrangement is often determined by the

organizations history, traditions, what is already installed, knowledge and experience, since both of the systems meets electric safety standards and EMC standards.

Figure 9: Two-wire and a three-wire system [8].

4.1.2.1 Two-wire

This system has a common positive return conductor and DC Protective Earth (see Figure 9). The positive conductor is connected to the framework of the subrack.

Some of the advantages with a two-wire power arrangement:

 There are several parameters that make this system more cost efficient compared with the three-wire system. There are no safety requirements for galvanic isolated DC/DC converters, it uses simpler filters, filters are only needed in the negative conductor, and there are no costs for isolation between the positive conductor and the frame of the subrack.

 The positive conductor works as a DC protective earth conductor for fault currents until the circuit breaker operates.

 The total resistance is very low, since all the positive conductors are connected in parallel.

Some of the disadvantages with a two-wire power arrangement:

 There are few outgoing distributions because of small power plants, to keep the voltage drop below a certain level Strengthening Cables must be used. They are often 50 mm² and are routed along and in parallel with the shortest positive conductor to prevent high current in these conductors.

4.1.2.2 Three-wire

The positive conductor in three-wire arrangement is isolated from the frameworks of the subrack and a separate DC Protective Earth is connected to the subrack. The DC/DC converters in the systems must be isolated.

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15 An advantage with a three-wire power arrangement:

 Strengthening cables are not needed.

Some of the disadvantages with a three-wire power arrangement:

 Compared to the 2-wire system, this system requires higher cost since galvanic isolated DC/DC converters is a requirement and costs for the isolation between the positive conductor and the frame on the subrack.

 More complex low frequency and high frequency filters.

4.1.3 Redundancy

To achieve a high reliability, most of Ericsson’s telecom systems have redundant feeds, one A-feed and one B-feed. During normal service the power consumption will be divided equally between the two feeds. An output of 800 W will be divided into 400 W at feed-A and 400 W at feed-B. If one of the feeds would go down, the other one will take over the total power consumption (5).

4.1.4 Ericsson Blade System

Ericsson Blade System (EBS) is a system used for several telecommunication systems with different interfaces and processing capacities. It can be used for different control nodes and the hardware can be changed for desired application. EBS can be configured for example server applications or traditional circuit switching.

4.1.4.1 Construction

The cabinet used is the BYB 501 (see Figure 10), which is the most commonly used cabinet for Core products (6). The cabinet has room for three subracks and one cabinet switch. If the system is supposed to be used with IT-equipment the BYB 504 can be used instead, since it has different dimensions.

The name of the subracks is Evolved Generic Ericsson Magazine 2 (EGEM2) and the EBS components are placed in here. EGEM2 take care of the power, cooling and provides the basic structure for switching and routing (7).

An important part of the subrack is the Power Fan Module (PFM). There are two PFMs in one subrack, one for feed-A and one for feed-B. Every PFM contains a fan unit that controls three fans depending on the temperature in the rack. The PFMs two inputs, with power from the same voltage source, are combined with the help of different power blocks to one output. The output is connected to one of the power rails (A-feed or B-feed) in the backplane. There are different types of PFMs:

 HOD, 2400 W or 3200 W, with a two-wire power distribution.

 LOD, 2400 W or 3200 W, with a two-wire power distribution (8) (9).

The EGEM2 has 24 slots for different kinds of boards, plus two slots dedicated for System Control Switch Board (SCXB) and two slots dedicated for Component Main Switch Board (CMXB). The 24 slots have an Ethernet connection through the backplane to both the SCXBs and the CMCBs, this is called dual star Ethernet topology. The boards have two inputs and get its power from the backplane, from both the A-feed and B-feed.

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There are more devices that can be connected to the EBS but they are not important for this project, these are for example a converter for optical Ethernet connections or boards for other applications. The important devices for the investigation of the input interface are the PFM, the backplane and boards for Core applications. It is on these boards which the DC/DC converters are placed (7).

Figure 10: Ericsson Blade System for SGSN-MME [9].

Cabinet BYB 501

Power & fan module (PFM) x 3

Subrack (EGEM2) x 3

Processing blades/Processor boards

Ethernet switches, SCXB & CMXB

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17 4.1.4.2 Core och EBS

EBS is a system that will be used in the future for some of Core applications. Examples of these are SGSN-MME and Evo Controller. To get an overview of what kind of systems it can be, here are two short descriptions:

SGSN-MME stands for Serving GPRS Support Node – Mobility Management Entity. This system is used in GSM (2G), WCDMA (3G) and LTE (4G) networks for switching packet-data and for management of the mobility (10).

The Evo Controller is a controller used for GSM, CDMA and WCDMA networks. The latest version, Evo Controller 8200, can be used as a multi controller with both BSC (used for GSM) and RNC (used for UMTS) in the same configuration. It can also be used only as a BSC or RNC. The development of the efficiency of the controllers is important, this due to the increasing data traffic caused by the many smart phones used in the world (11).

These two systems differ a bit but the power units are the same, and that are also the important parts for this project.

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5 Simulation

After completing the identification of the system, the next step was to perform a number of

simulations. In order to complete the simulation and make it as reliable as possible, a more detailed analysis of the system parts was needed. The simulation was performed in the program OrCad Pspice.

5.1 System definition

An EBS are either HOD or LOD, the choice between the two is decided by which PFM being used.

The system can also be either HOD or LOD depending on the power distribution used to power it.

HOD systems are slowly being phased out, and will not be used at Ericsson in the future. Therefore, this project has been concentrated on the LOD version of EBS.

With the help from Åke Ericsson, Expert of Site Power and Grounding at Ericsson, a model of EBS was drawn (see Figure 11) containing the following parts:

 PFM

o Current limiter

 Backplane

 A maximum of 28 boards, 24 slots for general boards and 4 dedicated slots for SCXB/CMXB.

o One board:

 Current limiter (PIM)

 DC/DC-converter

In order to make a better visualization of how the system works, in figure 11, the system has been divided in to multiple interfaces where the entrance to the DC/DC-converters was named interface C.

Figure 11: The LOD EBS system from interface A to interface C with only negative conductors.

Boards (max 28)

DC DC PIM

PFM A BP

A B Interface A

Interface C Interface B

Board

PFM B

(29)

19

In order to do a simulation with this system, more technical information was needed for the PFM and the PIM.

5.1.1 PIM

The PIMs main function is to limit high inrush currents. To do this the PIM quickly turns of and then turns on again, but limits the current to the chosen current limit. If the current limit is reached for another 1-3 ms the PIM will shut down again. The PIM is constructed to withhold a transient input up to 100 V.

In this work a PIM with a power of 200 W has been chosen. It has a current limit of 8.3 A and an input voltage of 36-75 V. The PIM has two inputs, an A-feed and a B-feed where the positive pole is earth (12).

Figure 13 is a model of the PIM with a constant load made in PSpice. The main goal when

constructing this model was to make it work as realistic as possible in the simulation. The model was created together with Mattias Andersson, Senior Electrical engineer at Power Modules.

5.1.1.1 Description of the model

Figure 12 shows a voltage source (V7) providing a pulse called Vpulse. It can be replaced by any preferred voltage source. The resistor used represents the impedance in the pulse. The resistance is derived from the test method C2 in ATIS (4).

The component D6 in Figure 12 is a Transient Voltage Suppression (TVS) diode also known as a transorb. The TVS diode protects against high voltage transients by starting conduct current at a particular voltage, in this case at 64 V. The diode can either be uni-directional (one diode) or bi- directional (two diodes in series) (13). In the PIM a bi-directional diode is used, this to protect against reversed polarity. But the component used in the PIM was only available as a uni-directional version for PSpice.

Dbreak D8

Dbreak D9

C1 100u

+ - G2

G

Y X Y X

U4

DIVIDER2 V6

200

0

IN

OUT -5.6

0 I2

8.3Adc

D4

STTH3002G R3

0.5

0

D6 SMCJ64A

D7 SMCJ64A

0 I1

8.3Adc

D1

STTH3002G

0

R2

0.5 V7

TD = 2m TF = 2u PW = 10m PER = 20m V1 = 50

TR = 2u V2 = 75

V8

TD = 2m TF = 2u PW = 10m PER = 20m V1 = 50

TR = 2u V2 = 75

Figure 12:The input to PIM with Vpulse.

(30)

20

Figure 13: Model of PIM with a constant load.

Dbreak D8

Dbreak D9

C1 100u

+ - G2

G

Y XY X

U4

DIVIDER2 V6

200

0

IN

OUT -5.6

0 I2

8.3Adc

D4

STTH3002G R3

0.5

0

D6 SMCJ64A

D7 SMCJ64A

0 I1

8.3Adc

D1

STTH3002G

0 R2

0.5 V7

TD = 2m TF = 2u PW = 10m PER = 20m V1 = 50

TR = 2u V2 = 75

V8

TD = 2m TF = 2u PW = 10m PER = 20m V1 = 50

TR = 2u V2 = 75

Dbreak D8

Dbreak D9

C1 100u

+ - G2

G

Y X Y X

U4

DIVIDER2 V6

200

0

IN

OUT -5.6

0 I2

8.3Adc

D4

STTH3002G R3

0.5

0

D6 SMCJ64A

D7 SMCJ64A

0 I1

8.3Adc

D1

STTH3002G

0 R2

0.5

V7

TD = 2m TF = 2u PW = 10m PER = 20m V1 = 50

TR = 2u V2 = 75

V8

TD = 2m TF = 2u PW = 10m PER = 20m V1 = 50

TR = 2u V2 = 75

V1

(31)

21

Figure 14 shows a current limiter and it uses a current source limited to 8.3 A. When the input voltage is 0 there are no current in the main circuit, but the current limiter (I1) has a flow of 8.3 A. The higher the current in the main circuit, the lesser current will flow through the diode (D8). This is due to the Kirchoffs current law. Given that D8 is a diode the current from the main circuit will take the path through the current source, and this means that the current in the main circuit never can exceed 8.3 A.

The diode used is an ideal diode. If a non-ideal diode were to be used a voltage drop would occur and the output voltage from the PIM would exceed the input voltage, when the opposite is wanted. To make an (almost) ideal diode, Dbreak is used with following text in the model:

.model Dbreak D Is=1e-14 n=0.0001 This results in a voltage drop of 0.0001 V.

In Figure 15 there are two diodes, D1 and D4. These are so called ORing diodes and are used when conductors needs to be connected. The diodes are used as a failsafe for the conductors. If one of the conductors malfunctions, resulting in a current drop, the higher current in the still functioning conductor is prohibited from pushing in to the malfunctioning conductor.

Shown as C1 in Figure 15 is a capacitor, with capacitance that is common used on the output of the PIM or input to the DC/DC converter.

Dbreak D8

Dbreak D9

C1 100u

+ - G2

G

Y X Y X

U4

DIVIDER2 V6

200

0

IN

OUT -5.6

0 I2

8.3Adc

D4

STTH3002G R3

0.5

0

D6 SMCJ64A

D7 SMCJ64A

0 I1

8.3Adc

D1

STTH3002G

0

R2

0.5

V7

TD = 2m TF = 2u PW = 10m PER = 20m V1 = 50

TR = 2u V2 = 100

V8

TD = 2m TF = 2u PW = 10m PER = 20m V1 = 50

TR = 2u V2 = 100

Figure 14: The current limiter.

Figure 15: ORing diodes and output capacitor.

Dbreak D8

Dbreak D9

C1 100u

+ - G2

G

Y X Y X

U4

DIVIDER2 V6

200

0

IN

OUT -5.6

0 I2

8.3Adc

D4

STTH3002G R3

0.5

0

D6 SMCJ64A

D7 SMCJ64A

0 I1

8.3Adc

D1

STTH3002G

0 R2

0.5

V7

TD = 2m TF = 2u PW = 10m PER = 20m V1 = 50

TR = 2u V2 = 100

V8

TD = 2m TF = 2u PW = 10m PER = 20m V1 = 50

TR = 2u V2 = 100

(32)

22

The load of the PIM, shown in Figure 16, is made to represent the DC/DC converter. It is a constant power load, which means that the effect is kept at the same level at all times, in this case at 200 W.

This is an ideal circuit, although in reality the effect cannot be withheld to an exact level at all times.

In Figure 16 the DC-voltage source V6 is divided with the output voltage from the PIM, and the voltage ratio goes out from U4. To limit the voltage and with that the current, a limiter is used. This avoids the circuit from drawing to much current. The smallest amount of voltage in the PIM is 36 V, which means that the highest current will be 5.6 A (200 W/ 36V = 5.6 A). In addition a converter named as G2 in the model, is used to convert the voltage to output current. This means that the effect of the circuit will be 200 W (P = U × I = VOUT_PIM × IOUT_G).

A number of simulations were made to ensure that model was working as realistically accurate to the real PIM as possible. Furthermore a comparison to the verification result was made, see Figure 17 and Figure 18. A voltage step was simulated at the input, the voltage ranged from -50 V down to -75 V and stayed at that level for 10 ms. The current increases as the voltage decreases, but it do not exceed 8.3 A because of the current limit. Then the circuit stabilizes. The most obvious differences between the simulation and the verification are that the current does not stay at the current limit in the simulation as long as in the verification, and also there is no current spike in the simulation. The flanks of VOUT are in a comparison quite alike in both graphs which are due to charging and discharging of the output capacitance.

Figure 17: A simulation of the PIM model.X-axis = 2 ms/div & Y-axis = 40 -/div.

Dbreak D8

Dbreak D9

C1 100u

+ - G2

G

Y X Y X

U4

DIVIDER2 V6

200

0

IN

OUT -5.6

0 I2

8.3Adc

D4

STTH3002G R3

0.5

0

D6 SMCJ64A

D7 SMCJ64A

0

I1

8.3Adc

D1

STTH3002G

0

R2

0.5

V7

TD = 2m TF = 2u PW = 10m PER = 20m V1 = 50

TR = 2u V2 = 100

V8

TD = 2m TF = 2u PW = 10m PER = 20m V1 = 50

TR = 2u V2 = 100

Figure 16: Constant load, representing a DC/DC converter.

Time

0s 2ms 4ms 6ms 8ms 10ms 12ms 14ms 16ms 18ms 20ms

V(V7:-) I(D1) V(G2:3,0) -80.0

-40.0 0 16.6

IIN

VOUT

VIN

(33)

23

Figure 18: Results from verification of PIM. C_O = 100uF, X-axis = 2 ms/div & Y-axis = 50 V/div or 10 A/div.

Notably this is a simplified model and therefore a bit more ideal than a real PIM. An example of this is the current spike in Figure 18. Since the model can limit the current to a desired value faster than the PIM there is no current spike in Figure 17.

5.1.2 PFM

The PFM compares to the PIM quite well. It has two inputs but in the PFM both these inputs comes from the same feed. It has a current limiter, ORing diodes, TVS diodes and an output capacitor (also called a hold up capacitor in the PFM). One difference that it has is smaller capacitors between the current limiter and ORing diodes. Of course the PFM has a lot more components, although these described above are the ones most essential to the simulation.

Some parameters derived from the description of the PFM LOD 2400 W (14):

C ≥ 40 000 uF L ≤ 1 uH

2400 W, 60 A @ -40.1 V.

According to Åke Ericsson, Expert of Site Power and Grounding at Ericsson, the inductance in a cable is typically 0.8 µH per meter. In the simulations it is estimated that there is a cable length of 0.5 meters from the PFM to a board and that is shown with an inductor of 0.4 µH. The PFM model is presented in Figure 19.

VOUT

VIN

IIN

(34)

24

Figure 19: Model of PFM.

-V_A_0

D2

STTH3002G

0

D5

STTH3002G

L2 0.4uH

1 2

D16 SMCJ64A

D17 SMCJ64A

-V_A_OUT D18

SMCJ64A

-V_A_IN_2

-V_A_0 -V_A_IN_1

D19 SMCJ64A

D20 SMCJ64A D21

SMCJ64A

C6 6.6u

C7 6.6u

C8 40m Dbreak

D8 I1

215.8Adc

Dbreak D9 I2

215.8Adc

(35)

25 5.1.3 The system in PSpice

The PFM model and the PIM model was connected and combined to one system in PSpice as shown in Figure 20. To make the model easier to overview, hierarchically blocks where used for the PFM and the PIM. A double click on the PIM+LOAD block will display the model shown in Figure 13 and a double click on the PFM_A or PFM_ B blocks will display the model in Figure 19.

Figure 20: The system with PFMs and PIM+LOAD.

PFM_A

PFM_A -V_A_IN_1

-V_A_OUT

-V_A_0 -V_A_0

-V_A_IN_2

PFM_B

-V_B_OUT -V_B_IN_1

-V_B_0 -V_B_IN_2

-V_B_0 R3

0.05

0

0 0

R2

0.05

Board

PIM+LOAD -V_A_IN

-V_B_IN

-V_B_0 -V_A_0 V1

53Vdc

V2 53Vdc

(36)

26

6 Results

This chapter shows the result of simulations with different scenarios.

6.1 Simulation with -53 V and one board

To see how the voltage changed through the system, a voltage of -53 V was applied on both feeds, see Figure 20. -53 V is used since it is the value stated as a typical value in ATIS. This value is also stated as a typical value in the specification for DC/DC converters.

The first simulation result presented in Figure 21 was made with only one board.

Figure 21: V_IN_A = -53 V, V_INPFM_A = -52.9 V, V_OUT PFM_A/ V_{A_IN} PIM = -52.2 V & V_OUT PIM = -51.5 V.

X-axis = 0.2 ms/div & Y-axis = 0.05 V/div.

The voltage drop over PFM (52.9 V – 52.2 V = 0.7 V) and over PIM (52.2 V – 51.5 V = 0.7 V) depends on the diodes in the models.

The simulated currents in the feeds from the PFMs to the PIM is roughly 1.94 A respectively. In the PIM 0.8 mA per feed goes to the TVS diodes.

6.2 Simulation with -53 V and 26 boards

There are room for 28 boards in a subrack, 24 for general boards and four for dedicated boards. Since only two of the four dedicated boards are mandatory, 26 boards are used in the simulation. All 26 boards will never be used all at the same time, since there is not enough power. The LOD PFM in this thesis has an output power of 2400 W, where the fans uses 200 W which means that there is 2200 W left for the boards. To do a simulation with 26 boards a model was made with 1 + 25 boards (Figure 22). The block 25_PIM+LOAD, which uses 2000 W, is 25 times bigger (see Figure 23) than the PIM+LOAD block which uses 200 W.

Time

0s 1ms 2ms 3ms 4ms 5ms 6ms 7ms 8ms 9ms 10ms 11ms 12ms 13ms 14ms 15ms 16ms 17ms 18ms 19ms 20ms

V(Board.C1:1,Board:-V_A_0) V(V1:-) V(R2:2,0) V(PFM_A:-V_A_OUT,0) -53.0V

-52.8V -52.6V -52.4V -52.2V -52.0V -51.8V -51.6V -51.4V

VOUT PIM

VOUT PFM_A/VA_IN PIM

VIN PFM_A VIN A

(37)

27

Figure 22: A model with 1+25 boards.

Figure 23: The 25_PIM+LOAD block where V6 is 2000 W.

Board

PIM+LOAD -V_A_IN

-V_B_IN

-V_B_0 -V_A_0 PFM_A

PFM_A -V_A_IN_1

-V_A_OUT

-V_A_0 -V_A_0

-V_A_IN_2

0 PFM_B

PFM_B

-V_B_OUT -V_B_IN_1

-V_B_0 -V_B_IN_2

-V_B_0 R3

0.05

0

25_PIM+LOAD

25_PIM+LOAD -V_A_IN

-V_A_0

-V_B_IN

-V_B_0

0 R2

0.05

V1 53Vdc

V2 53Vdc

-V_A_0

-V_B_0

0 C1 2.5m

+ - G2

G

Y XY X

U4

DIVIDER2 V6

2000

IN

OUT -56

0 I2

207.5Adc

D4

STTH3002G D6

SMCJ64A

D7 SMCJ64A

I1

207.5Adc

D1

STTH3002G

-V_B_IN -V_A_IN

(8.3*25)

(8.3*25) Dbreak D8

Dbreak D9

(38)

28 The simulation of the system is shown in Figure 24.

Figure 24: V_IN_A = -53 V, V_INPFM_A = -51.9 V, V_OUT PFM_A/ V_{A_IN} PIM = -51.0 V & V_OUT PIM = -50.3 V.

X-axis = 0.2 ms/div & Y-axis = 0.1 V/div.

The simulated current in the two PFMs is now 21.9 A respectively, the bigger part of these currents goes to the block 25_PIM+LOAD and the smaller part goes to PIM+LOAD, which means a current of 1.99 A per feed.

6.3 Transient simulation with one board

As seen in Figure 6, ATIS has defined a curve that represents a protective device transient, this transient was simulated with a generator VPWL at feed A with the values shown in Figure 25. Feed B where still at -53 V. The result is shown in Figure 26.

Figure 25: VPWL source.

Time

0s 1ms 2ms 3ms 4ms 5ms 6ms 7ms 8ms 9ms 10ms 11ms 12ms 13ms 14ms 15ms 16ms 17ms 18ms 19ms 20ms

V(Board.C1:1,Board:-V_A_0) V(V1:-) V(R2:2,0) V(PFM_A:-V_A_OUT,0) -53.0V

-52.5V -52.0V -51.5V -51.0V -50.5V -50.0V

V3 T1 = 0

T2 = 2m T3 = 2.012m T4 = 12.0035m T5 = 12.0055m

V1 = 50 V2 = 50 V3 = 5 V4 = 5 V5 = 100 T6 = 12.0555m

T7 = 20.805m T8 = 23.305m

V6 = 75 V7 = 75 V8 = 50

0 VOUT PIM

VOUT PFM_A/ VA_IN PIM

VIN PFM_A

VIN_A

(39)

29

Figure 26: V_INPFM_A = -78.5 V @ -100 V input, V_OUT PFM_A/ V_{A_IN} PIM = Start value is -49.6 V and minimum value is -73.7 V & VOUT PIM = Start value is 51.3 V and minimum value is -73.0 V. X-axis = 0.5 ms/div & Y-axis = 50 V/div.

The reason for the input voltage of PIM being lower than the output voltage in the beginning of the pulse is because the transient at feed A starts at -50.0 V and the voltage at feed B at -53.0 V. This is because the ORing diodes will direct the highest voltage to the output. This can also be seen with the current in Figure 27. The voltage from feed B is larger until 12 ms, it is during this time where it is only current from feed B which will flow to the output. When 12 ms is reached (this is also when the input voltage goes to -100 V), the currents will switch because now the voltage from feed A are higher than the one in feed B. The current simulated will reach a maximum at 5.33 A at feed A and 3.90 A at feed B.

As seen in Figure 26 the output voltage of the PIM did not go back to its start value within 30 ms, Figure 28 shows that the voltage is back at -51.3 V around 300 ms.

Figure 27: The current switches when VB_IN PIM gets bigger than VA_IN PIM. X-axis = 0.5 ms/div & Y-axis = 2 -/div.

Time

0s 2ms 4ms 6ms 8ms 10ms 12ms 14ms 16ms 18ms 20ms 22ms 24ms 26ms 28ms 30ms

V(BOARD.C1:1,BOARD:-V_A_0) V(V3:-) V(PFM_A:-V_A_OUT,0) V(PFM_A:-V_A_IN_1,0) -100V

-80V -60V -40V -20V -0V

Time

V(BOARD:-V_A_IN,0) I(BOARD.D1) I(BOARD.D4) V(PFM_B:-V_B_OUT,0) -80

-70 -60 -50 -40 -30 -20 -10 0 10

VIN_A VIN PFM_A

VOUT PFM_A/ VA_IN PIM VOUT PIM

IIN_A

IIN_B

VA_IN PIM VB_IN PIM

(40)

30

Figure 28: VOUT PFM_A/ VA_IN PIM and VOUT PIM recovers at around 300 ms. X-axis = 10 ms/div & Y-axis = 5 V/div.

Figure 29 shows the current in input 1 to PFM_A. In this model the PFM can reduce the current from input to output, in this case from 215.7 A to 4.6 A. Note that the total input current will be two times 215.7 A. Charging of the output capacitor handles the overcurrent.

Time

0s 50ms 100ms 150ms 200ms 250ms 300ms 350ms 400ms 450ms 500ms

V(BOARD.C1:1,BOARD:-V_A_0) V(V3:-) V(BOARD:-V_A_IN,0) -120V

-100V -80V -60V -40V -20V -0V

Time

I(PFM_A.D2) -I(PFM_A.L2) -40A

0A 40A 80A 120A 160A 200A 240A

Figure 29: The current is reduced in the PFM. X-axis = 0.5 ms/div & Y-axis = 10 A/div.

VIN_A

VOUT PFM_A/ VA_INPIM VOUT PIM

IIN PFM_A

IOUT PFM_A

Input interface requirements on board mounted DC/DC converters

Abstract

Sammanfattning

Acknowledgements

Table of contents

1 Abbreviations

2 Introduction

2.1 Background

2.2 Problem definition

2.3 Goals

2.4 Delimitations

2.5 Methods

3 Standards

3.1 Standard from ETSI

3.2 Standard from ATIS

4 System

4.1 Core site

5 Simulation

5.1 System definition

6 Results

6.1 Simulation with -53 V and one board

6.2 Simulation with -53 V and 26 boards

6.3 Transient simulation with one board