Processing and characterization of self-aligned Ni/Al and Co ohmic contacts to 4H-SiC

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IN

DEGREE PROJECT MICROELECTRONICS, SECOND CYCLE, 15 CREDITS

STOCKHOLM SWEDEN 2018,

Processing and characterization of self-aligned Ni/Al and Co ohmic contacts to 4H-SiC.

FERRARIO ANDREA

KTH ROYAL INSTITUTE OF TECHNOLOGY

SCHOOL OF ELECTRICAL ENGINEERING AND COMPUTER SCIENCE

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Processing and characterization of self-aligned Ni/Al and Co ohmic contacts

to 4H-SiC.

ANDREA FERRARIO

Degree project in Microelectronics Electrical Engineering and Computer Science

KTH Royal Institute of Technology Stockholm, Sweden 2018

Supervisor: Mattias Ekström

Examiner: Professor Carl-Mikael Zetterling

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iii

Abstract

New self-aligned silicide processes for the realization of Ni/Al and Co contacts to silicon carbide (4H-SiC) are presented and contacts are characterized using the transfer length method (TLM). Since cobalt silicide formation on 4H-SiC has not been investigated before, interface reaction between Co and 4H-SiC as well as the study on the annealing temperatures consti- tute an essential part of this work. For this purpose x-ray diffraction (XRD) analysis is performed and results on the temperature and time dependency are derived.

Contact fabrication is performed through rapid thermal processing (RTP) in two steps: the first is needed to establish the silicide phase and the second to form an ohmic contact. For what regards Ni/Al contacts, both first step annealing (FSA) and second step annealing (SSA) were performed at 600

◦C. For Co it was found that FSA at 800 ^◦C and SSA at 1000 ^◦C was a good choice to form ohmic contacts to n-type 4H-SiC.

Sheet resistance and specific contact resistivity (ρ_c) are extracted for each kind of contact. The electrical characterization is performed for different temperatures starting from 25^◦C to a maximum of 500^◦C for the Ni/Al contacts and in the range 25-300^◦C for Co contacts. At room temperature (25^◦C), a ρ_cof 5.6 · 10⁻⁴ Ω cm² is found for Ni/Al p-type (> 1 · 10¹⁹ cm^-3) contacts while a ρ_c of 3.6 · 10⁻⁴ Ω cm² is extracted for Co n-type (1 · 10¹⁹ cm^-3) contacts.

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iv

Sammanfattning

Nya självlinjerade silicideringsprocesser för att möjliggöra Ni/Al- och koboltkontakter till kiselkarbid (4H-SiC) presenteras och karaktäriseras via överföringslängdsmetoden (eng. transfer length method, TLM). Eftersom att den självlinjerade koboltmetalliseringen på 4H-SiC var en ny process så blev en viktig del av arbetet att studera gränssnittsreaktionen vid olika värme- behandlingstemperaturer. Röntgendiffraktion (eng. x-ray diffraction, XRD) användes för detta ändamål och temperatur- och tidsberoende bestämdes.

Kontaktformering genomförs via snabb värmebehandling (eng. rapid thermal processing, RTP) i två steg: det första steget bildar en silicid och det andra steget bildar den ohmska kontakten. Både det första och andra värmebehandlingssteget (eng. first step anneal, FSA, och second step anneal, SSA, resp.) gjordes vid 600 ^◦C. Det upptäcktes att kobolt gav ohmska kontakter till n-typ SiC om man gör det första värmebehandlingssteget vid 800^◦C och det andra värmebehandlingssteg vid 1000 ^◦C.

Ytresistivitet och specifik kontaktresistivitet (ρ_c) har extraherats för båda typer av kontakter. Den elektriska karaktäriseringen gjordes vid olika temperaturer, från 25 ^◦C till 500 ^◦C för Ni/Al-kontakterna, och Co- kontakterna mättes i intervallet 25-300^◦C. Ni/Al-kontakterna på p-typ (>

1 · 10¹⁹ cm^-3) gav den specifika kontaktresistiviteten 5.6 · 10⁻⁴ Ω cm² vid rumstemperatur (25 ^◦C), och Co-kontakterna på n-typ (1 · 10¹⁹ cm^-3) gav 3.6 · 10⁻⁴ Ω cm².

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v

Sommario

In questa tesi vengono presentati due nuovi processi di fabbricazione per la realizzazione di contatti auto-allineati al Ni/Al e Co su carburo di silicio (4H-SiC). Degli stessi viene inoltre effettuata la caratterizzatione tramite il metodo TLM (transfer lenght method). Data la mancanza di studi precedenti sulla formazione di siliciuro di cobalto su 4H-SiC, l’ analisi della reazione all’ interfaccia tra Co e 4H-SiC insieme allo studio delle temperature di annealing costituiscono parte fondamentale di questo lavoro. A questo riguardo è stata eseguita un’ analisi XRD che ha permesso di ricavare la dipendenza della reazione dal tempo e al variare della temperatura.

La realizzazione dei contatti viene eseguita tramite rapid thermal processing (RTP) in due fasi: la prima (first step annealing, FSA) è necessaria per la formazione della prima fase del siliciuro mentre la seconda (second step annealing, SSA) serve a stabilire le caratteristiche di bassa resistenza al contatto. Nel caso dei contatti Ni/Al entrambi gli step sono eseguiti a 600 ^◦C mentre nel caso del cobalto è stato ricavato che 800 ^◦C e 1000 ^◦C costituiscono una buona scelta per il primo e il secondo step rispettivamente.

Sono stati ricavati i valori di sheet resistance e resistivitá specifica di contatto (ρ_c) per entrambi i processi. La caratterizzazione è effettuata a temperature differenti: nel caso dei contatti Ni/Al essa è stata eseguita nel range di temperature che va da 25 ^◦C a 500 ^◦C; per i contatti al Co la caratterizzazione è stata effettuata per temperature comprese tra 25 ^◦C e 300 ^◦C. A 25 ^◦C è stata ricavata una ρ_c di 5.6 · 10⁻⁴ Ω cm² per i contatti Ni/Al con substrato p (> 1 · 10¹⁹ cm^-3) mentre un valore di ρ_c uguale a 3.6 · 10⁻⁴ Ω cm² è stato estratto per i contatti al cobalto con substrato n (1 · 10¹⁹ cm^-3).

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Acknowledgements

I would like to thank Prof. Carl-Mikael Zetterling and Prof. Pierpaolo Palestri for giving me the opportunity to be an exchange student at KTH. Without their support this work could have not been possible.

I owe sincere and earnest thankfulness to Mattias Ekström, my supervisor, who guided me through each step of my work. His dedication, patience and help- fulness resulted exemplary and constructive to me but also fundamental for the achievement of the objectives of this thesis.

Many thanks to Laura Žurauskait˙e, without whom it could not have been possible performing the work with the RTA machine. Also, I would like to thank her for her availability when any kind of advice was needed.

Thanks also to Shouben Hou who let me follow his work on Ni/Al fabrication processing and thanks to Sergiy Khartsev that helped me with the XRD analysis.

My master student fellows and office mates, João Pina, Yandi Liu and Corrado Capriata, made every of my days in the office: thank you, I wish you the best.

I thank all my friends from Stockholm and from home with particular reference to Matteo Zavagno who has been like a brother to me.

The final acknowledgements go to my parents, for their support and encour- agement throughout my study. To them I dedicate this thesis.

Andrea Ferrario,

Stockholm, 04/09/2018

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List of Figures

2.1 Tetrahedrical molecule structure of SiC . . . 6

2.2 Fundamental SiC bilayers. Blue atoms represent C and orange atoms represent Si. . . 7

2.3 Occupation sites (A, B, and C) in the hexagonal close-packed system [5]. 8 2.4 Different stacking structures for different SiC polytypes [5]. . . 8

2.5 Properties of different SiC polytypes [5] . . . 9

2.6 Carriers concentration for different temperatures assuming a doping level of 5 · 10¹⁴cm⁻³ . . . 10

2.7 Phase diagram of the Si-C binary system [14] . . . 11

2.8 Schematic illustration of a crucible used for seeded sublimation growth of SiC [5] . . . 12

3.1 Example of a metal and a semiconductor band structure before contact. 16 3.2 Example of metal and semiconductor band structures before and after contact formation. [16] . . . 16

3.3 Accumulation-type contact for n- (a) and p-type (b) [16]. . . 17

3.4 Dominating conduction effect for increasing doping densities for an accumulation-type contact [16]. . . 18

3.5 Sketch of a two-contact structure on a semiconductor showing all the series resistances involved. . . 19

3.6 Sketch of current crowding on a contact. The transfer length of the contacts is less than the total length [16]. . . 21

3.7 Extraction of contact parameters using a TLM structure [24]. . . 22

3.8 Schematic image of a TLM structure [16]. . . 23

4.1 Sketch of all the lithography steps that are generally performed when there is the need of patterning structures on a wafer. . . 26

4.2 Sketch of a simple lithographic exposure system [15]. . . 27

4.3 Mask aligner MA/BA6 Karl Suss used in this project. . . 28

4.4 Resist spinner OPTIspin SST20. . . 29

4.5 HMDS oven IMTEC Star 2000 used in this project. . . 30 ix

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x List of Figures

4.6 PVD machine Endura structure scheme . . . 31

4.7 Photo of the Applied Materials Endura machine. . . 31

4.8 Sketch of a magnetron sputtering machine [15]. . . 32

4.9 "Lesker" magnetron sputtering system used in this project. . . 32

4.10 General structure of a CVD chamber [15]. . . 33

4.11 Photo of the ALD machine BENEQ TFS200 used in this project. . . . 34

4.12 Photo of some chambers composing the RIE machine P5000. . . 35

4.13 RTA machine Mattson 100 RTP Systems used in this project. . . 37

4.14 Example of a self aligned silicide process with TiSi₂ formation [4]. . . 38

4.15 TLM epi-layers structure for pieces with both n- and p-type contacts . 40 4.16 TLM epi-layers structure for pieces with p-type contacts only. . . 40

4.17 Microscope image of a TLM piece before any deposition. On the right structure it is easy to note the presence one more epi-layer with respect to the structure on the left: on this structure will be realized n-type contacts. . . 41

4.18 Generic contact structure after each step of the self-aligned Co ohmic contacts to 4H-SiC process: (a) SiO₂ deposition; (b) SiO₂ patterning through lithography and oxide etching; (c) Co deposition; (d) formation of Co silicides after the FSA; (e) etching of the unreacted cobalt by piranha solution; (f) structure after the SSA. . . 42

4.19 Microscope image of a TLM piece after the lithography step. . . 42

4.20 TLM structures with with contact size 200 µm × 100 µm . . . . 43

4.21 TLM structures with with contact size 100 µm × 50 µm. . . . 43

4.22 Microscope image of a TLM piece Co deposition. . . 44

4.23 SEM image of the top surface of a contact after the first step annealing 44 4.24 TLM structures after FSA and before piranha stripping . . . 45

4.25 TLM structures after FSA and after piranha stripping . . . 45

4.26 Generic structure of a contact during the realization the measurement pads: (a) TiW deposition and patterning; (b) Al deposition and patterning. . . 45

4.27 Microscope image of a TLM structure with pads after full processing. 46 4.28 Scheme of the structure with two isolated mesas and the epilayers . . . 46

4.29 Generic contact structure after each step of the self-aligned Ni/Al ohmic contacts to 4H-SiC process: (a) SiO₂ deposition; (b) SiO₂ patterning through lithography and oxide etching; (c) Ni deposition; (d) formation of Ni silicide after the FSA; (e) etching of the unreacted Ni by piranha solution. . . 47

4.30 Generic contact structure after the FSA in the self-aligned Ni/Al ohmic process: (a) Al deposition; (b) Al patterning through lithography and metal etching; (c) formation of alloy after SSA; . . . 48

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List of Figures xi

4.31 TLM structure after full processing of Ni/Al contacts . . . 49 5.1 XRD spectra obtained after annealing of the pieces with 40 nm of Co

at different temperatures for 60 s. . . 52 5.2 XRD spectra before and after the 800 ^◦C piece was put into piranha. . 53 5.3 XRD spectra obtained for RTA at 800^◦C with different annealing times. 54 5.4 Four probes measurement setup for the characterization of contacts. . 55 5.5 I-V characteristic for p-type (N_a > 10¹⁹cm⁻³) contacts for two different

SSA: Schottky behavior. . . 55 5.6 I-V characteristic for n-type contacts for two different SSA: ohmic be-

havior. . . 55 5.7 TLM total resistance plot for SSA at 850^◦C for different TLM structures. 56 5.8 TLM total resistance plot for SSA at 900^◦C for different TLM structures. 56 5.9 TLM total resistance plot for SSA at 950^◦C for different TLM structures. 57 5.10 TLM total resistance plot for SSA at 1000^◦C for different TLM structures. 57 5.11 Co contacts: ρ_cdependence with the temperature; errorbars correspond

to one standard deviation. . . 59 5.12 Co contacts: R_s dependence with the temperature; errorbars corre-

spond to one standard deviation. . . 59 5.13 Two probes measurement setup for the characterization of contacts. . . 60 5.14 Four probes measurement setup for the characterization of contacts. . . 60 5.15 Plot of total resistance for the same TLM structure for different tem-

peratures of measurement. The markers are the actual data points while the straight lines are the linear fitting of these data points. . . . 61 5.16 Ni/Al contacts: ρ_C dependence with the temperature; errorbars corre-

spond to one standard deviation. . . 61 5.17 Ni/Al contacts: R_s dependence with the temperature; errorbars corre-

spond to one standard deviation. . . 62

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List of Tables

4.1 Chemicals for unreacted metal etching in a salicide process . . . . 39 4.2 Ni/Al wafer epitaxy layers . . . 46 5.1 Specific contact resistivity ρ_c and sheet resistance R_s for Co contacts . 58 5.2 Specific contact resistivity ρ_cand sheet resistance R_sfor Ni/Al contacts

low temperatures . . . 62 5.3 Specific contact resistivity ρ_cand sheet resistance R_sfor Ni/Al contacts

for high temperatures . . . 62 5.4 Examples of metallizations reported for p-type ohmic contacts. Dop-

ing concentrations refers to epitaxial layer, implantation is marked by (impl). . . 64

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List of Acronyms

Al Aluminum

ALD Atomic layer deposition

Co Cobalt

CVD Chemical vapor deposition

DIW De-ionized water

ε Dielectric constant

E_C Critical electric field φ_B Schottky barrier height

φ_m Metal workfunction

FSA First step annealing

h Plank’s constant

HMDS Hexamethyldisilazane

HTCVD High temperature chemical vapor deposition

k_B Boltzmann constant

MERIE Magnetically enhanced reactive ion etching

N_A Donors concentration

N_D Acceptors concentration

Ni Nikel

PVD Physical vapor deposition PVT Physical vapor transport

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xiv LIST OF ACRONYMS

RIE Reactive ion etching RTA Rapid thermal annealing RTP Rapid thermal processing ρ_c Specific contact resistivity ρ_i Specific interfacial resistivity

R_c Contact resistance

R_m Metal resistance

R_s Sheet resistance

R_semi Semiconductor resistance SSA Second step annealing TLM Transfer length method

Ti Titanium

UV Ultraviolet

χ Electronic affinity

V_B Breakdown voltage

W Tungsten

XRD X-ray diffraction

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Chapter 1 Introduction

At the very beginning, electronics was based on the use of vacuum tubes. The invention of the first transistor in 1947 [1] has made a fundamental change in the conception of electronics: thanks to the properties of semiconductor materials it was possible to design and realize small, compact and fast circuits. This fact gave birth to the so called solid state electronics in the sense that the electronic flow and action was now occurring in a solid state and no more in gaseous state.

At this point, it was easy to understand the importance of the knowledge of semiconductor properties and since then several different materials were studied.

Nowadays the most famous and used semiconductor is Si (silicon) but also Ge (germanium) and semiconductor compounds such as GaAs (gallium arsenide) and SiC (silicon carbide) are widely implied.

In particular, the latter compound is the material used as a substrate in this thesis and an overview about its electrical properties is performed in the next chapter. The interest towards SiC is related to its electrical, mechanical and chemical characteristics. In fact, SiC can withstand harsh environments in the sense of high temperature, high voltage and high radiation conditions without the need of particular bulky packaging or dissipating systems. This results in an optimized structure design, smaller dimensions of the circuitry, higher power efficiency as well as reduced cost of production.

Metal contacts are essential elements of every integrated circuit and their presence should not affect the behavior of the devices themselves. Having good metal contacts means that their current-voltage relationship need to be linear and have to show a low series resistance regardless the temperature and the time of use.

The realization of low resistivity ohmic contacts to n- and p-type 4H-SiC is investigated in this thesis and two different salicidation processes are characterized:

one involves the formation of Ni silicide and the other the formation of Co silicide.

In particular, this thesis presents an evaluation of Ni/Al p-type ohmic contacts in the temperature range of 25 ^◦C - 500 ^◦C and of Co n-type ohmic contacts in

1

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2 CHAPTER 1. INTRODUCTION

the interval of temperature 25-300^◦C. The experimental part of the work includes both fabrication processes and the interface reaction analysis of Co with SiC.

1.1 Motivations and research objectives

The realization of ohmic contact to SiC has been a recurring research interest at KTH for all the above mentioned reasons. A self-aligned silicide (salicide) Ni (nickel) process to n-type contacts [2] and semi-salicide nickel-aluminum (Ni-Al) process to p-type silicon carbide (4H-SiC)[3] have been developed.

A silicide technology involves the use of silicides for the formation of low resistive and thermally stable contacts. Initially, the silicide was deposited with the common techniques. Lithography and etching processes were inevitable (see Chap- ter 4 for more details) with the lithography step being highly critical. Over the years, this technique resulted not an easy choice as a consequence of the scaling pushing down the size of the devices.

A new process, called self-aligned process, was then invented and led to the de- velopment of a simplified and remarkably more reliable device fabrication process.

With this technique it was possible to realize contacts without the implication of lithography steps. Furthermore, it was possible to realize multiple contacts on the same device simultaneously and with high precision.

The combination of a self-aligned process with the use of silicides gave birth to the so called self-aligned silicide process or salicide process. Further explanations are given in Section 4.5.

In silicon technology, titanium (Ti) and cobalt (Co) are well-established materials for salicide processing [4]. Ti is frequently used as part of 4H-SiC p-type contact [5], and Co has been demonstrated as a ohmic contact to p-type 6H-SiC [6], but results to 4H-SiC are unclear [7] . Given that the valence bands are at similar energy levels between the two polytypes [8], p-type ohmic contacts on 6H-SiC should also be p-type ohmic contacts to 4H-SiC. Results from [9] indicates that the first phase of CoSix forms around 650 ^◦C - it might be possible to self-align Co to SiC. The ohmic contact formation might occur at a higher temperature, in which case the process uses the same two-step methodology as in [2].

This thesis work investigates the implementation of the silicon technology Co- salicide processes in SiC technology to both p-type and n-type substrates. Is then verified if Co can self-align to SiC and, in that case, if it forms ohmic contacts on one or both opposite doped substrate. Concerning the Ni/Al-contacts, a fabrication process was already developed [3] but an investigation on the contact properties was required. For this purpose, an electrical characterization of these contacts has been performed.

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1.2. THESIS ORGANIZATION 3

1.2 Thesis organization

This thesis is organized in five more chapters: the second chapter is dedicated to the description of SiC structure and properties; the third chapter explains contacts characteristics and definitions together with the presentation of the transfer length method (TLM) used for the characterization of contacts; the fourth chapter covers fabrication technologies and the processing steps through which the structures were realized; the fifth chapter illustrates all the results obtained; in the last chapter conclusions are drawn and suggestions for future work are given.

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Chapter 2 Silicon carbide structure and properties

2.1 Crystal structure

The crystal structure is a description of the ordered arrangement of atoms in a crystalline material. In silicon carbide (SiC) crystals, every silicon (Si) atom is bonded covalently to four carbon (C) atoms so that the unit building block is a tetrahedron in which the distance between carbon atoms is 3.08 Å and the distance between two different types of atoms is 1.89 Å as shown in Figure 2.1.

The distance between Si and C is slightly smaller than the Si bond length and owns quite high energy (4.6 eV): this is the main reason for which SiC has the outstanding properties which will be explained in the next sections.

However, SiC crystallizes in a wide variety of different structures while the molecular structure remains the same. From a crystallographic point of view, in fact, SiC is the best known example of polytypism [5]. Polytypism is the phe- nomenon where a material can adopt different crystal structures which vary in one dimension (that is, in stacking sequence) without changes in chemical composition. To better understand this aspect, it is easier to think in two dimensions. All polytypes are made of an hexagonal frame of SiC bilayers and, in total, there are six different bilayers each consisting of two close packed planes [10] as shown in Figure 2.2(a).

Each bilayer can be described as sheets of spheres with constant radius as illustrated in Figure 2.3. Note that 4 Miller indexes are used in these case; this is due to the fact that SiC is and hexagonal system and then it is easier to indicate the crystal directions using 3 coplanar vector (a₁, a₂, a₃) plus a perpendicular vector c to the plane in which the previous vectors lay.

Three are the possible sites that every atom (both Si and C) is allowed to 5

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6 CHAPTER 2. SILICON CARBIDE STRUCTURE AND PROPERTIES

Figure 2.1: Tetrahedrical molecule structure of SiC

occupy and these are denoted as A, B, and C. Each atom of the same single layer can occupy only one of these sites and two successive layers cannot occupy the same site; the next layer on top of an A layer must occupy either B or C sites (and, similarly, A or C is allowed over B). Therefore, there exist, in principle, almost infinite variations of the stacking sequence when stacking a number of different layers. For most materials, only one stacking structure (often either the zincblende or wurtzite structure) is usually stable and, in particular, SiC crystallizes in almost 250 polytypes [5].

Summarizing, the sheets are the same for all lattice planes but the way in which they are stacked can differ: each plane, consisting of a double layer of carbon and silicon atoms, is shifted according to the adjacent planes. This gives rise to three different positions of the planes, and so to different polytypes according to the specific repetitive order in which the sheets are arranged as depicted in Figure 2.4.

The name of each polytype is characterized by a number and a letter according to the Ramsdell notation [11]: the number indicates how many layers form the basic sequence, and the letter determines the resulting structure of the crystal: C for cubic, H for hexagonal, and R for rhombohedral.

Regardless of polytype, as already said, the chemical composition SiC remains the same and the bond lengths are not significantly affected. However, properties such as band gap and mobility vary depending on polytype due to different number of atoms in the unit cell. Initially 6H-SiC was mostly used due to easier crystal growth. With the development of improved techniques to avoid bulk defects, 4H-SiC (Figure 2.2(b)) has become the dominating substrate featuring wider bandgap, higher mobility and less mobility variation in the different crystal

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2.2. ELECTRICAL PROPERTIES 7

Figure 2.2: Fundamental SiC bilayers. Blue atoms represent C and orange atoms represent Si.

directions compared to 6H-SiC.

2.2 Electrical properties

2.2.1 Bandgap

Because of the short bond length, SiC has a wide energy bandgap. Room temperature values are around three times larger than Si bandgap. The main advantages of this material, such as high critical electric field, the possibility to operate at higher temperature and the radiation hardness, are all related to this very property. This and some other parameters of SiC for different polytypes are summarized in Figure 2.5.

2.2.2 Breakdown electric field

The critical electrical field is defined as the electrical field value at which impact ionization leads to breakdown. For SiC this value is about 10 times higher than that of Si. This property makes SiC more suitable for power electronics applica- tions. For instance, in an abrupt p-n junction, said W the depletion width and E_C the critical electric field, the breakdown voltage V_B is given by:

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Figure 2.3: Occupation sites (A, B, and C) in the hexagonal close-packed system [5].

Figure 2.4: Different stacking structures for different SiC polytypes [5].

V_B = E_CW

2 (2.1)

so that, with the same W , a ten times higher V_B can be achieved. On the other hand, if a non-punch-trough design is desired, i.e. a design for which the depletion region in a PIN diode is fully inside the intrinsic or low doped region, the device can be made ten times thinner keeping the same V_B. Then if we consider a p⁺-n junction the doping of the low-doped region N_D is:

N_D = 2εV_B

qW² = εE_c²

2qV_B (2.2)

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2.2. ELECTRICAL PROPERTIES 9 Figure 2.5: Properties of different SiC polytypes [5]

inferring that the doping can be made one hundred times higher. Hence, since the on-resistance is given by:

R_ON = W qµnND

= 4V_B²

εµnE_C³ (2.3)

and also taking the lower values for mobility and dielectric constant of SiC in account, the final result is that much lower on-resistance can be achieved for the same V_B: roughly a factor between 200 and 400 with respect to Si depending on the polytype [12].

2.2.3 High intrinsic temperature and radiation hardness

An electron-hole (e-h) pair can be created providing energy to the crystal, thermally or by radiation. The p-n junction, the basic device, relies on the fact that on the p-side there are almost only holes and on the n-side there are almost only electrons. This assumption is correct (i.e. the device is extrinsic) and the device works as long as the intrinsic carriers concentration is negligible compared to the doping. At high temperature or under high radiation flux, the intrinsic carriers even outnumber the extrinsic ones: the material becomes intrinsic. When that happens, both the electron and hole concentration equal the intrinsic one, then the junction and hence the devices fail. The intrinsic temperature sets the threshold between these two situations (see Figure 2.6).

The energy bandgap is the minimum energy needed to create an e-h pair.

Because of the wider bandgap, in SiC higher temperature or more intense radiation fluxes compared to silicon are required to create e-h pairs or, equivalently, there are considerably fewer intrinsic carriers at any given temperature. Looking at Figure 2.6, the intrinsic carrier concentration of SiC at 300^◦C is ≈ 10⁴ cm⁻³ while the Si one is ≈ 10¹⁵ cm⁻³: a difference of almost eleven orders of magnitude.

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Figure 2.6: Carriers concentration for different temperatures assuming a doping level of 5 · 10¹⁴cm⁻³

In particular, the intrinsic temperature of SiC falls at around 1000 ^◦C [12]

(depending on polytype and doping), while Si’s one is at about 270^◦C [13].

2.2.4 High thermal conductivity

SiC has a three times higher value for thermal conductivity compared to Si, mean- ing that a three times higher thermal flow is possible for the same thermal increase at the junction. As previously stated, in power electronics the devices can be made thinner, but this on turn implies less heat flow, so that the higher thermal conductivity just mitigates this disadvantage. When it comes to integrated circuits, electric fields are usually much lower than critical electric field, so that for SiC higher thermal conductivity just means better capability to carry heat out of the device.

2.3 Material growth and ion implantation

A look at the SiC phase diagram make it easy to understand that the commonly used techniques adopted for Si crystal growth cannot be exploited. In fact, there is no stoichiometric SiC liquid phase so it is really difficult to carry on a melt growth at relevant system pressures. A technique called top seeded solution growth was developed and consist in the use of a graphite crucible filled with a Si or Si-metal melt with a perfect SiC crystal seed in direct contact with this solution. The crucible and the seed are rotating in opposite directions and the growth temperature

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2.3. MATERIAL GROWTH AND ION IMPLANTATION 11

is maintained at around 1750-2100 ^◦C. This method is quite similar to the ones adopted for Si growth but is definitely more critical since really high temperatures are required (2800 ^◦C): at these temperatures evaporation of Si is significant and a continuous growth is almost impossible. Some improvements have been done with the development of high-pressure solution growth and the solution growth with metal-added solvent techniques. However, these methods are still not mature.

The standard technique adopted now for SiC bulk growth is the so called seeded sublimation method. This method essentially consist in three steps: the first is the sublimation of the SiC source; the second is the mass transport of sublimed species; the third is the surface reaction and crystallization. This method is also known as physical vapor transport or PVT growth. The structure of a crucible used for seeded sublimation is illustrated in Figure 2.8.

Figure 2.7: Phase diagram of the Si-C binary system [14]

The SiC source is SiC powder or sintered polycristalline SiC and it is placed at the bottom of the crucible. The crucible is usually heated up by radio frequency (RF) induction with the seed maintained at a temperature about 100^◦C lower than the source one in order to provide a driving force for growth. Another important

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Figure 2.8: Schematic illustration of a crucible used for seeded sublimation growth of SiC [5]

thing to mention is that the gradient of temperature inside the crucible controls the growth process determining the polytype, the quality and the growth rate of the boule. Finally, the growth is performed in a highly-pure argon (Ar) or helium (He) ambient.

Defects in SiC boule, such as stacking faults [15], have been a major concern also in the determination of the wafer sizes. In fact, nowadays, the size of a SiC can reach six inches while Si wafers are also sold in 11.8 inches stocks.

For what concerns the doping of SiC, this can be done by ion implantation [15].

However, really high temperature are required for the activation of the dopants increasing the probability of damaging the sample more than the implantation itself. In the sublimation growth technique dopant atoms are simply introduced in the growth ambient. In the case of n-type Sic, nitrogen (N₂) is usually introduced together with the inert gas (Ar or He). For p-type SiC, instead, aluminum (Al) is added to the SiC source. Phosphorus (P) and Boron (B) can also be used to get n-type and p-type SiC substrates respectively. Doping concentrations range from 9 · 10¹⁴ to 1 · 10¹⁹ cm⁻³ on Si face for both n- and p-type [7].

Finally, another technique worth to mention is the high-temperature chemical vapor deposition (HTCVD). The structure of a HTCVD reactor is quite similar to the one of the seeded sublimation. In this method the SiC boule growth is performed by the introduction of precursor gasses diluted in a carrier gas like in

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2.3. MATERIAL GROWTH AND ION IMPLANTATION 13

a normal chemical vapor deposition (CVD) system (ref. Chapter 4). Inside the hot zone, the precursors are completely decomposed and several reactions proceed.

As a result, Si and SiC clusters are formed via homogeneous nucleation because of the high supersaturation in the gas phase [5]. These clusters act as a virtual source for SiC boule growth on the seed. Therefore, it is important to establish an appropriate temperature gradient from the gas inlet to the seed. This technique has several advantages over the seeded sublimation one for what regards purity C/Si control to reduce the formation of defects and ability to grow very long boules.

However, reports on HTCVD are still limited compared to sublimation growth and that is the reason why this method is still not commonly adopted.

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Chapter 3 Contacts on semiconductors

Contacts are a fundamental part of every electronic device. Generally, they are metal-semiconductor contacts but there are also semiconductor-semiconductor contacts, where both semiconductors can be single crystal, polycrystalline or amor- phous. In the discussion of ohmic contact resistance, this section will focus on metal-semiconductor contacts because they are the ones used in this case study.

3.1 Band bending for a metal-semiconductor junction: the Schottky barrier

Consider Figure 3.1, which sketches the bands diagrams of a metal and a semiconductor before the contact formation. The two materials have different Fermi levels but, when in contact and in equilibrium, the this one should be flat in both materials.

Assuming an intimate contact between the metal and the semiconductor, what can happen is illustrated in Figure 3.2 and depending on this three possibilities the contact that is formed is referred as accumulation (3.2 (a)), neutral (3.2 (b)) and depletion (3.2 (c)) contact respectively.

According to the Schottky model, whether one configuration should be pre- ferred with respect to another depends on the metal work function Φ_M and on the electronic affinity of the semiconductor χ. The ideal barrier high after contact for this model is:

φ_B = φ_M − χ (3.1)

where φ_B is the height of the Schottky barrier and φ_M is the potential associated to the energy Φ_M. At this point one could think that it should be easy to obtain each of the three different configurations just choosing a metal with an appropriate

15

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16 CHAPTER 3. CONTACTS ON SEMICONDUCTORS

Figure 3.1: Example of a metal and a semiconductor band structure before contact.

Figure 3.2: Example of metal and semiconductor band structures before and after contact formation. [16]

work function. In practice this is not true and the barrier height for the common semiconductors (Si, Ge, GaAs and other III-V materials) shows a small dependence on the work function of the metal and this is generally due to the formation of trap sites at the interface between the two materials [17]. A depletion contact is generally formed in both n- and p-type substrates as shown in Figure 3.3.

In order to have a low resistive contact is then not possible to work on the

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3.1. BAND BENDING FOR A METAL-SEMICONDUCTOR JUNCTION:

THE SCHOTTKY BARRIER 17

Figure 3.3: Accumulation-type contact for n- (a) and p-type (b) [16].

Schottky barrier height. Furthermore, barrier heights for p- and n-type contacts are related to the energy bandgap E_G of the semiconductor through the relation [16]:

Φ_B_n + Φ_B_p = E_G (3.2)

where Φ_B_n and Φ_B_p are the schottky barrier height for a given metal with respect to n-, and p-type substrate respectively.

Therefore, it is easy to understand how it has not been successful for semiconductors with wide bandgap to find a metal that is good for both n- and p-type contacts. However, it is not only the barrier height that plays an important role in the realization of good contacts but also the width of the depletion region. In fact, having a thin depleted region allows the electrons tunnel through it. The width of the depleted region can be then engineered through the use of different doping densities (N_A, N_D) in such a way that (for an n-type semiconductor):

W ∼ 1

√ND

(3.3) Depending on the doping, the effects that dominate the flow of the electrons through the metal-semiconductor junction are depicted in Figure 3.4. So, for lightly doped semiconductor, the electrons can overtake the barrier only as a result of thermionic emission [18] (Figure 3.4 (a)). For an high doping level, the barrier becomes so thin that the electrons can tunnel trough it: this phenomenon is called field emission [19] (Figure 3.4 (c)). Finally, for an intermediate doping density, the electrons are thermally exited to an energy where the barrier is sufficiently narrow for tunneling to take place. This is called thermionic-field emission [19] (Figure 3.4 (b)).

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Figure 3.4: Dominating conduction effect for increasing doping densities for an accumulation-type contact [16].

Which is the dominating mechanism can be determined by the calculation of the value _qE^k^B^T

00 where k_B is the Boltzmann constant, T is the absolute temperature in Kelvin and E₀₀ is given by:

E₀₀ = h 4π

N mε

¹₂

(3.4) where h is the Planck’s constant and m is the effective mass while is the dielectric constant. Thermionic emission is dominating when _qE^k^B^T

00 >> 1 while if _qE^k^B^T

00 << 1 field emission is more common. For the intermediate cases the thermionic field emission mechanism is the one that dominates the electron flow.

3.1.1 Ohmic contacts

The main driver for the continuous improvement in VLSI has been the search for electronic circuits of higher performance at lower cost. In particular, the speed of an electronic circuit is one of the major concerns: parasitic capacitance and series resistance should be minimized. This allows to reduce the resistance-capacitance time delay and increase the clock frequency. Contacts with a linear I-V character- istic and low resistance are needed: these contacts are called ohmic contacts.

To form an ohmic contact, depositing a metal is usually not enough and, indeed, high temperatures of annealing are required for reaction with the substrate. The key-point is creating a good silicide at the metal-semiconductor interface. Metal silicides are the best candidates for the realization of contact metallizations and wiring thanks to their low specific resistivity, low contact resistivity, high thermal stability and perfect compatibility with the standard Si technology [20, 21]. A well-known process called self-aligned silicidation will be explained in the next chapter in section 4.5.

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3.2. ELECTRICAL CHARACTERIZATION 19

High doping densities are also required, and in the case of SiC, at least 5 · 10¹⁸ cm^-3 for n-type and 10¹⁹ cm^-3 for p-type [12].

3.2 Electrical characterization

3.2.1 Model parameters

Let us consider the resistance between contact A and B in Figure 3.5, each lying on an insulator and making ohmic contacts on an n-type substrate.

Figure 3.5: Sketch of a two-contact structure on a semiconductor showing all the series resistances involved.

The total resistance R_T can be written as:

R_T = 2R_m+ 2R_c+ R_semi (3.5)

where R_mis the resistance of the metallic conductor, R_cis the contact resistance and R_semi is the semiconductor resistance.

3.2.1.1 Sheet resistance

The semiconductor resistance is determined by the sheet resistance of the n-layer, i.e. the resistance of a rectangular slab of homogeneous material with equal width and length. Calling t the thickness of the slab and ρ the resistivity of the material, the sheet resistance is:

R_s = ρ

t (3.6)

The advantage in introducing R_s is that it allows to think about resistors in terms of number of squares, since their resistance is simply obtained by multiplying it by Rs, and this is certainly more convenient when one is dealing with layouts.

In practice, the semiconductor is a diffusion or epitaxially grown layer so it can

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hardly be seen as an homogeneous material. In this case, as a first approximation, an average resistivity ρ can be calculated by considering the doping profiles along the layer.

3.2.1.2 Contact resistance and specific contact resistivity

This resistance cannot be clearly defined because it does not only comprise the resistance of the metal-semiconductor interface but also a portion of the metal and of the semiconductor above and below that interface: current crowding effects or interfacial oxide can be both present and need to be considered. In fact, a specific interfacial resistivity ρ_i can be defined as:

ρ_i = ∂V

∂J

_{V =0}

(3.7) where V is the applied voltage and J is the current density that flows through the contact. This quantity is just theoretical and it cannot be measured because of the effect referred to above. The parameter that is actually measured is the specific contact resistivity ρ_c(Ωcm²) which is a quantity that does not depend on the contact area and is an useful parameter when comparing contacts with different sizes.

Again, ρ_i is used only to derive theoretical expressions of metal-semiconductor contacts. In particular, for a field-emission (FE) dominated conduction effect, a simplified expression for the interfacial resistivity can be derived [16]:

ρ_i(F E) ∼ exp( C

√N) (3.8)

where C is a constant and N is the doping concentration. This expression clearly shows that a high doping density has to be adopted in order to have low resistivity contacts.

The specific contact resistance ρ_c can be expressed as:

ρc= R_cAef f (3.9)

where A_{ef f} is the effective contact area. A two-dimensional current flow analysis by Kennedy et al. [22] revealed current crowding at the contact and only a fraction of the total contact length was active during the transfer of current from the metal to the semiconductor and vice versa: this length is called transfer length (L_T).

3.2.1.3 Transfer length

A transmission line model was applied by Murrmann et al. [23] to planar devices in order to model the current transfer and to be able to extract contact resistance and sheet resistance. The transfer length L_T is defined, within this model, as the

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length where the voltage due to current transferring from the semiconductor to the metal or vice versa has dropped to ¹/^e of its maximum value, which is located at the contact edge. A more practical result is that, said L and Z the contact dimensions, if L ≥ 1.5L_T, the effective contact area becomes L_T · Z and, since L can be much higher than L_T , the effective area can be much smaller than the actual one (Figure 3.6).

L

LT

Figure 3.6: Sketch of current crowding on a contact. The transfer length of the contacts is less than the total length [16].

Therefore the current density is much higher than expected in the close proximity of the contacts: this has to be considered when designing the contacts to prevent reliability problems. The transfer length depends on the contact specific resistance and on the sheet resistance of the semiconductor underlying the contact through the relation:

L_T =

rρc

Rs (3.10)

Such formula suggests that the smaller the semiconductor resistance compared to the contact one, the more the current spreads below the contact.

3.2.2 Test structure for contact resistance measurement:

TLM structure

Instead of evaluating full devices or circuits, test structures are use for determining the contact characteristics. A common structure used for this purpose is the well known transfer length method (TLM) structure that is a lateral structure in which the current flows horizontally with respect to the contact (Figure 3.7).

The TLM test structures are used in order to determine parameters R_s and ρ_c. Such structures are named after the transfer length method (TLM), originally conceived by Shockley, but are not unrelated to the transmission line model, since the method, on turn, resorts to the model’s approximations to evaluate the total resistance. In particular, according to the transmission line model, the contact resistance is given by:

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Figure 3.7: Extraction of contact parameters using a TLM structure [24].

R_c=

√R_sρ_c

Z coth(L/L_T) = ρ_c

L_TZcoth(L/L_T) (3.11) where L_T is given by eq. 3.10, and Z and L are respectively the contact width and length. If it is L ≥ 1.5L_T the following approximation holds:

R_c ≈ ρ_c

L_TZ (3.12)

The total resistance R_T between any two adjacent contacts of a TLM structure is given by:

R_T = R_sd

Z + 2R_c≈ R_s

Z (d + 2L_T) (3.13)

The method involves measuring these values and plotting them versus spacing d. Doing so enables to extract: the sheet resistance R_s through the slope of the interpolating line; the contact resistance R_c from the y-axis intercept; the transfer length from the x-axis intercept; the specific contact resistivity as explained before.

For a more direct explanation an example plot of R_T in function of the spacing distance is shown in Figure 3.8.

The total resistance can be measured with a two or a four probes setting.

The latter is usually preferable because less sensitive to parasitics, cable resistance and non-perfect probes contact. That is because current and voltage, which are measured independently, are both unaffected by extra resistances on their own path. In fact, if an extra resistance is added on the current probes an extra applied voltage is needed, but the current is correctly sensed; similarly, if the extra resistance lies on the voltmetric path, it has to be compared to the voltmeter in resistance, hence resulting easily negligible.

Some problems of the transfer length method are worth mentioning: the x- axis intercept is sometimes not very distinct, yielding incorrect values for L_T and ρ_c [16]; the relationship for R_T (eq. 3.13) assumes constant sheet resistance for

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Figure 3.8: Schematic image of a TLM structure [16].

the semiconductor, even under the contacts, where it might be different because of effects due to contact formation. Equations 3.12 and 3.13 should be slightly modified in this case [25]. In addition, Li et al. [26] proved that the sheet resistance is a weak function of the spacing between contacts and observed an error on contact resistance for small contact spacings (< 0.1 µm).

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Chapter 4 Fabrication technologies and processing

This chapter presents a brief background on the fabrication and processing technologies adopted in this work. In each section a general description of the technology is given, followed by the description of the machine used for that purpose. The actual fabrication is then detailed in the last section.

4.1 Optical lithography

The term lithography groups a set of processes used to transfer a pattern from a mask to a photosensitive film, named photoresist, deposited on the substrate of interest. Optical lithography processes commonly rely on ultraviolet (UV) light in order to expose some areas of the photoresist which can be removed creating particular patterns on the substrate. After exposure, the photoresist absorbs radiation and undergo chemical reactions to change its chemical dissolution properties in the developer. The net result is a different dissolution rate (usually around 100:1) between areas that absorbed radiation and areas that did not absorb radiation. Material deposition, etching, plating, doping and other processes can be done on the substrate. Posteriorly, the photoresist can be chemically removed.

Two types of photoresist can be distinguished: positive photoresist in which the exposed part dissolves more quickly while the unexposed regions remain unchanged (ideally) and negative photoresist that has the opposite behavior.

The general process steps followed when doing lithography are summarized in Figure 4.1.

Before performing what displayed in Figure 4.1.1, the wafer has to be baked to evaporate out moisture from the surface of the wafer (this can be done at 150-200

◦C). Then hexamethyldisilazane (HMDS) can be applied to improve the adhesion 25

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26 CHAPTER 4. FABRICATION TECHNOLOGIES AND PROCESSING

Figure 4.1: Sketch of all the lithography steps that are generally performed when there is the need of patterning structures on a wafer.

of the photoresist. The wafer is then mounted on a rotating disk in which the rotation speed and timing are previously determined in order to reach a certain resist thickness. In this phase, the resist is poured on the surface and this step is called spinning. After spinning, the wafer must undergo a soft-bake or pre-bake (Figure 4.1.3) to drive out most of the solvent in the resist and to establish the exposure characteristics: this is done at 90-100 ^◦C for a couple of minutes. The wafer is then exposed to UV light and this can be done in several different ways depending on the characteristics of the target resolution and alignment. Contact lithography, proximity lithography and stepper lithography can be distinguished and will be briefly presented in Section 4.1.1. After exposure the wafer is usually baked in order to eliminate standing waves that can be formed on the edges of the resist due to constructive/destructive interference: like the soft-bake, this one is performed at 90-100 ^◦C for a couple of minutes. At this point the resist is developed (Figure 4.1.6) and a hard-bake used to cross-link the resist and harden it against further energetic processes such as ion implantation and plasma etching (usually done at 110^◦C for more than 10 minutes). The final step is the inspection of the results obtained.

4.1.1 Exposure techniques

As stated in the precedent subsection, several kind of exposures techniques can be carried out and a very general scheme of an optical lithography system is presented in Figure 4.2.

In contact printing, the mask is pressed against the resist-coated wafer during exposure. The main advantage of contact printing is that fairly small features

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4.1. OPTICAL LITHOGRAPHY 27

Figure 4.2: Sketch of a simple lithographic exposure system [15].

can be made using comparatively inexpensive equipment. Vernier screws are then used to move the wafer with respect to the mask. Once the wafer is aligned to the mask, the two are clamped together, the microscope objectives are retracted, and the wafer/mask assembly is wheeled into the exposure station. Because of this contact, the gap between the wafer and the optical disturbance (photomask) goes to zero and diffraction effects are minimized. Actually, due to the finite resist thickness, the gap cannot be zero. Furthermore in real contact printers, the mask contact, varies across the wafer surface. This occurs since neither the wafer nor the mask are perfectly flat. 1:1 contact lithography are susceptible to defect generation due to the contact and clamping between the wafer and the mask.

Defects are generated both on the wafer side and on the mask: anything based on pressing two things together leads to yield issues so that is the reason why 1:1 contact lithography is only limited to research purposes.

An intermediate evolution of contact lithography is the proximity printing that was developed to avoid mechanic defect generation. In this type of exposure tool, the mask floats off the surface of the wafer, typically on a cushion of nitrogen gas.

The gap between the wafer and mask is controlled by the flow of nitrogen into this space. However, the presence of a gap between mask and wafer causes a relevant reduction in the resolution of the machine. A second problem with small gaps is the distance variation along the wafer: this may be caused by wafer or mask non-planarity, dirt particles, resist beads, and unintentional tilt. The combination of all of this factors leads to linewidth variations across the wafer. An attractive alternative to avoid these problems is to reduce the wavelength of the exposing lamp. Systems used to expose fine features, therefore, typically operate deep in

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the UV.

Stepper lithography (based on projection printing) does not require the mask to make contact with the wafer. The mask is held between the condenser and a second set of lenses called projector or objective. The purpose of the projector is to refocus the light onto the wafer. In some cases, the light from the condenser is not collimated but instead is focused on the plane of the projector. In most aligners used in IC manufacturing, however, the optics are sufficiently well made that the resolution is limited by the ability of the optical train to collect and reimage the light.

4.1.1.1 Mask aligner: MA/BA6 Karl Suss

In this work a mask aligner was used to perform all the lithography processes. In particular the tool is the Mask aligner MA/BA6 Karl Suss (https://www.suss.com) and it can perform both contact and proximity lithography by manual alignment of the specimen under process. The MA/BA6 is equipped with a motorized top side alignment system which can reach an alignment accuracy of 0.5 µm. In addition to top side alignment, many applications, such as MEMS, require precise bottom side alignment (BSA). The MA/BA6 can optionally be equipped with bright-field bottom side microscopes. These ones include an optical magnification switch and facilitate 1 µm alignment accuracy. The BSA microscope with single- and split- field features uses high resolution CCD cameras. The MA/BA6 offers various exposure modes to meet any requirements for a broad range of applications. Soft, hard and vacuum contact printing are used to achieve highest resolution down to submicron range. Proximity printing is applied to avoid any mask/wafer contact.

The prevention of mask contamination directly translates into higher yield. An image of the tool is shown in Figure 4.3.

Figure 4.3: Mask aligner MA/BA6 Karl Suss used in this project.

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4.1. OPTICAL LITHOGRAPHY 29

4.1.1.2 Resist Spinner: OPTIspin SST20

In Figure 4.4 the resist spinner OPTIspin SST20 (http://www.atmvision.de/) used in this project is shown. It simply consists of a rotating disc in which vacuum must be applied in order to stick the wafers/pieces to its surface. The spin speed range is 100-6000 rpm and has to be chosen, together with the spin time, in order to obtain the wanted resist thickness. Different programs can be selected through the use of a touch screen display.

Figure 4.4: Resist spinner OPTIspin SST20.

4.1.1.3 HMDS prime oven: IMTEC Star 2000

In Figure 4.5 the HMDS prime oven (https://www.imtecacculine.com/) used in this work is presented. This machine is a vapor primer: the wafers/pieces lie down onto a grid inside the oven where the HMDS liquid is in vapor phase allowing the vapor to coat the whole surface of the wafer. Time and temperature can be programmed through a simple LCD interface depending on the type of process has to be performed. In order to promote a bond to the substrate wafers are completely dehydrated (not only surface moisture, but the chemically bound water molecules as well). To achieve this, a combination of heat with low pressure is needed.

Once dehydrated, wafers are then primed with an HMDS vapor to strengthen the photoresist adhesion.

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Figure 4.5: HMDS oven IMTEC Star 2000 used in this project.

4.2 Deposition

To create a stack or a structure built out of different materials, a fundamental step is the deposition. Different deposition techniques have been developed and still in use depending on the material that has to be deposited, the step coverage that has to be achieved, the deposition rate and several other specifications. Since the number of different techniques is very wide, this section concentrates only on the ones used in this work: physical vapor deposition (PVD); magnetron sputtering;

chemical vapor deposition (CVD) and atomic layer deposition (ALD).

4.2.1 Physical vapor deposition

This technique is mostly used for the deposition of metals when a non-crucial step coverage is required. The wafers are loaded into a high vacuum chamber that is commonly pumped with either a diffusion pump or a cryopump. The charge, or material to be deposited, is loaded into a heated container called the crucible. It can be heated very simply by means of an embedded resistance heater and an external power supply. As the material in the crucible becomes hot, the charge gives off a vapor. Since the pressure in the chamber is much less than 1 mTorr, the atoms of the vapor travel across the chamber in a straight line until they strike a surface, where they accumulate as a film. Evaporation systems may contain several crucibles to allow the deposition of multiple layers without breaking vacuum.

Furthermore, if an alloy is desired, multiple crucibles can be operated simultaneously. To help start and stop the deposition abruptly, mechanical shutters are used in front of the crucibles.

Applied Materials Endura (http://www.appliedmaterials.com/) is the machine used in this work. This machine is made of several chambers each one having a decreasing pressure. The structure and a photo of Endura can be seen in Figure 4.6 and Figure 4.7 respectively.

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4.2. DEPOSITION 31

Figure 4.6: PVD machine En- dura structure scheme

Figure 4.7: Photo of the Applied Materials Endura machine.

At first the wafer is loaded into a Load Lock (LL) at atmospheric pressure.

Then the LL is pumped down in pressure and transferred in the buffer chamber through a robotic arm which picks up the wafer and put it in the degassing chamber(E). In this chamber the wafer is heated just to evaporate off moisture from its surface. Then it is moved in the transfer chamber through A in which the chamber is pumped down. Finally, the wafer is placed in the actual process chamber which is chosen depending on the material that has to be deposited. When the deposition ends the wafer returns back to the LL through the B chamber that is also used to cool down the wafer. The pressure in the transfer chamber and deposition chambers is in the order of 10⁻⁸mTorr.

4.2.2 Magnetron sputtering

Metal layers for all the early semiconductor technologies were deposited by evaporation (Section 4.2.1). However, this deposition technique suffers of poor step coverage and presents serious problems when depositing compounds or alloys [15].

All these problem were solved with the introduction of the sputtering technique.

To give an idea of the working principles, a simple sputtering scheme is drawn in Figure 4.8.

A power supply system (DC or RF) feeds a parallel plate plasma reactor [15]

in a vacuum chamber. The plasma chamber must be arranged so that the high energy ions strike a target containing the material to be deposited. An inert gas is normally used to supply the chamber with a pressure that is held at about 0.1 torr so that the free mean path of the atoms that have to be deposited is higher;