Electrical Characteristics

March 1996

NDS355N

N-Channel Logic Level Enhancement Mode Field Effect Transistor

General Description Features

_______________________________________________________________________________

Absolute Maximum Ratings

Symbol Parameter NDS355N Units

V_DSS Drain-Source Voltage 30 V

V_GSS Gate-Source Voltage - Continuous 20 V

I_D Drain Current - Continuous (Note 1a) ± 1.6 A

- Pulsed ± 10

PD Maximum Power Dissipation ^{(Note 1a)} 0.5 W

(Note 1b) 0.46

T_J,T_STG Operating and Storage Temperature Range -55 to 150 °C

THERMAL CHARACTERISTICS

R_θJA Thermal Resistance, Junction-to-Ambient (Note 1a) 250 °C/W

R_θJC Thermal Resistance, Junction-to -Case (Note 1) 75 °C/W

These N-Channel logic level enhancement mode power field effect transistors are produced using Fairchild's proprietary, high cell density, DMOS technology. This very high density process is especially tailored to minimize on-state resistance.

These devices are particularly suited for low voltage applications in notebook computers, portable phones, PCMICA cards, and other battery powered circuits where fast switching, and low in-line power loss are needed in a very small outline surface mount package.

1.6A, 30V. R_DS(ON) = 0.125Ω ^{@ V}GS = 4.5V.

Proprietary package design using copper lead frame for superior thermal and electrical capabilities.

High density cell design for extremely low R_DS(ON). Exceptional on-resistance and maximum DC current capability.

Compact industry standard SOT-23 surface mount package.

D

G S

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Electrical Characteristics

Symbol Parameter Conditions Min Typ Max Units

OFF CHARACTERISTICS

BV_DSS Drain-Source Breakdown Voltage V_GS = 0 V, I_D = 250 µA 30 V

I_DSS Zero Gate Voltage Drain Current V_DS = 24 V, V_GS = 0 V 1 µA

T_J=125°C 10 µA

I_GSSF Gate - Body Leakage, Forward V_GS = 12 V, V_DS = 0 V 100 nA

I_GSSR Gate - Body Leakage, Reverse V_GS = -12 V, V_DS= 0 V -100 nA

ON CHARACTERISTICS (Note 2)

VGS(th) Gate Threshold Voltage VDS = VGS, ID = 250 µA 1 1.6 2 V

T_J=125°C 0.5 1.3 1.5

R_DS(ON) Static Drain-Source On-Resistance V_GS = 4.5 V, I_D = 1.6 A 0.125 Ω

T_J=125°C 0.25

V_GS = 10 V, I_D = 1.9 A 0.085

I_D(ON) On-State Drain Current V_GS = 4.5 V, V_DS = 5 V 6 A

gFS Forward Transconductance VDS = 5 V, ID = 1.6 A 3.5 S

DYNAMIC CHARACTERISTICS

C_iss Input Capacitance V_DS = 10 V, V_GS = 0 V, f = 1.0 MHz

245 pF

Coss Output Capacitance 130 pF

C_rss Reverse Transfer Capacitance 20 pF

SWITCHING CHARACTERISTICS ^{(Note 2)}

t_D(on) Turn - On Delay Time V_DD = 10 V, I_D = 1 A,

V_GS = 10 V, R_GEN = 6 Ω ^{15 30 ns}

t_r Turn - On Rise Time 14 30 ns

tD(off) Turn - Off Delay Time 12 25 ns

t_f Turn - Off Fall Time 4 10 ns

Q_g Total Gate Charge V_DS = 10 V, I_D = 1.6 A, V_GS = 5 V

3.5 5 nC

Q_gs Gate-Source Charge 1 nC

Q_gd Gate-Drain Charge 2 nC

Electrical Characteristics

Symbol Parameter Conditions Min Typ Max Units

DRAIN-SOURCE DIODE CHARACTERISTICS AND MAXIMUM RATINGS

I_S Maximum Continuous Source Current 0.6 A

ISM Maximum Pulse Source Current (Note 2) 6 A

V_SD Drain-Source Diode Forward Voltage V_GS = 0 V, I_S = 1.6 A 0.8 1.2 V

Notes:

1. R_θJA is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins. R_θJC is guaranteed by

design while R_θCA is determined by the user's board design.

P_D(t) =^T_Rθ^J−TA

J A(t)=_R ^TJ−TA

θJ C+RθCA(t)=I_D²(t) ×R_DS(ON)TJ

Typical R_θJA using the board layouts shown below on 4.5"x5" FR-4 PCB in a still air environment:

a. 250^oC/W when mounted on a 0.02 in² pad of 2oz cpper.

b. 270^oC/W when mounted on a 0.001 in² pad of 2oz cpper.

Scale 1 : 1 on letter size paper

2. Pulse Test: Pulse Width < 300µs, Duty Cycle < 2.0%.

1 a 1b

Typical Electrical Characteristics

Figure 1. On-Region Characteristics Figure 2. On-Resistance Variation with Gate Voltage and Drain Current

0 1 2 3 4

0 3 6 9 12

V , DRAIN-SOURCE VOLTAGE (V)

I , DRAIN-SOURCE CURRENT (A)

6.0 5.0 4.5

4.0

3.5

3.0 V =10V_GS

DS

D

0 3 6 9 12

0.5 1 1.5 2

I , DRAIN CURRENT (A)

DRAIN-SOURCE ON-RESISTANCE

D R , NORMALIZEDDS(on)

6.0 5.0 4.5 4.0

1 0 V =3.5V_GS

-50 -25 0 2 5 5 0 7 5 1 0 0 1 2 5 1 5 0

0.6 0.8 1 1.2 1.4 1.6

T , JUNCTION TEMPERATURE (°C)

DRAIN-SOURCE ON-RESISTANCE

J V =4.5V

GS I = 1.6A_D

R , NORMALIZEDDS(ON)

-50 -25 0 2 5 5 0 7 5 1 0 0 1 2 5 1 5 0

0.6 0.7 0.8 0.9 1 1.1 1.2

T , JUNCTION TEMPERATURE (°C)

GATE-SOURCE THRESHOLD VOLTAGE (V)

J V , NORMALIZEDth

V = V_{DS GS} I = 250µA_D

0 2 4 6 8 1 0 1 2

0.5 1 1.5 2 2.5 3

I , DRAIN CURRENT (A)

DRAIN-SOURCE ON-RESISTANCE

T = 125°CJ

25°C -55°C

D

V = 4.5V

GS

R , NORMALIZEDDS(on)

Figure 3. On-Resistance Variation with Temperature

Figure 4. On-Resistance Variation with Drain Current and Temperature

Figure 5. Transfer Characteristics Figure 6. Gate Threshold Variation with Temperature

1 2 3 4 5 6

0 2 4 6 8 1 0

V , GATE TO SOURCE VOLTAGE (V)

I , DRAIN CURRENT (A)

V = 10V_DS

GS

D

T = -55°CJ 25°C 125°C

-50 -25 0 25 50 75 1 0 0 1 2 5 1 5 0 1 7 5 0.9

0.95 1 1.05 1.1 1.15

T , JUNCTION TEMPERATURE (°C)

DRAIN-SOURCE BREAKDOWN VOLTAGE (V)

I = 250µA_D

BV , NORMALIZEDDSS

J

0.2 0.4 0.6 0.8 1 1.2 1.4

0 . 0 0 1 0 . 0 1 0.1 1 1 0 2 0

V , BODY DIODE FORWARD VOLTAGE (V)

I , REVERSE DRAIN CURRENT (A)

V = 0V_GS

SD

S

T = 125°CJ

25°C

-55°C

0 1 2 3 4 5 6 7

0 2 4 6 8 1 0

Q , GATE CHARGE (nC)

V , GATE-SOURCE VOLTAGE (V)

V = 5V_DS

g

GS

1 0 I = 1.6A

D

1 5

0.1 0.2 0.5 1 2 5 1 0 3 0

3 0 5 0 1 0 0 2 0 0 3 0 0 5 0 0

V , DRAIN TO SOURCE VOLTAGE (V)

CAPACITANCE (pF)

DS

C iss

C oss

C rss f = 1 MHz

V = 0 V_GS

G D

S

V

R

V

V

IN

OUT

V

R

10%

50%

90%

10%

90%

90%

Input, Vin 50%

Output, Vout

t_on t_off

td(off) tf

tr

td(on)

Inverted

10%

Pulse Width Figure 7. Breakdown Voltage Variation

with Temperature

Figure 8. Body Diode Forward Voltage Variation with Current and Temperature

Figure 9. Capacitance Characteristics Figure 10. Gate Charge Characteristics

Figure 11. Switching Test Circuit Figure 12. Switching Waveforms

Typical Electrical Characteristics

0 2 4 6 8 1 0 1 2 0

2 4 6 8

I , DRAIN CURRENT (A)

g , TRANSCONDUCTANCE (SIEMENS)

D

FS V = 5V _DS

T = 125°CJ 25°C -55°C

D

0.1 1 2 5 1 0 2 0 3 0 5 0

0.01 0.1 0.5 1 2 1 0 2 0

V , DRAIN-SOURCE VOLTAGE (V) I , DRAIN CURRENT (A)D

V = 1 0 V SINGLE PULSE

T = 25°CA RDS(ON) Limit

GS DC

DS

1s1 00m s 10s

1 0ms 1 ms

100us

Figure 13. Transconductance Variation with Drain Current and Temperature

Figure 14. Maximum Safe Operating Area

Typical Electrical Characteristics

0 . 0 0 0 1 0.001 0.01 0.1 1 1 0 1 0 0 3 0 0

0.001 0.002 0.005 0.01 0.02 0.05 0.1 0.2 0.5 1

t , TIME (sec)

TRANSIENT THERMAL RESISTANCE

r(t), NORMALIZED EFFECTIVE

1 Single Pulse

D = 0.5

0.1

0.05

0.02

0.01 0.2

Duty Cycle, D = t /t_{1 2} R (t) = r(t) * R

R = 250 °C/WθJA θJA θJA

T - T = P * R (t)J A θJA P(pk)

t 1 t ₂

Figure 15. Transient Thermal Response Curve

Note : Characterization performed using the conditions described in note 1c. Transient thermal response will change depending on the circuit board design.