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How to upload an image to the SRAM on the DE2-115.

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How to upload an image to the SRAM on the DE2-115.

Petter K¨allstr¨om and Mario Garrido TSIU03, August 2019

Process

1. Log in to the computer where the DE2-115 is connected (this is not required for the first steps).

2. Convert the image into .bin format (this can be done on any computer with Matlab).

(a) Copy K:\TSIU03\Projects\Matlab\image converter.m to where your image is.

(b) Start matlab and navigate to the folder of your image.

(c) Run image_converter(’MyImage’,’loadPNG,saveBin’); (if your image name is MyImage.png).

3. Copy the folder K:\TSIU03\DE2 115 Resources\DE2 115 ControlPanel to your TSIU03 folder.

4. You may need to send the DE2_115_ControlPanel.sof file to the FPGA by using the Quartus II Programmer in JTAG mode. This will configure the FPGA to create a connection to the Memory through the USB Blaster.

5. Start the Control Panel application (DE2_Control_Panel.exe) and follow the next instructions:

• Select ”Memory” in the buttons to the left.

• In ”Memory Type” select ”SRAM”. Double check that you have selected the ”SRAM”.

• In the ”Sequential Write” pane check the ”File Length” check box.

• Click on ”Write a File to Memory”.

• Select your .bin file.

• Close the Control Panel application. Now you can test your project on the DE2 board.

Additional Considerations

1. If there are many groups who want to program the SRAM, the group who is logged in at the computer connected to the board, should be prepared to send an image from another group to the DE2-115 board. A file can be easily transmitted by e.g. email or a USB memory.

2. If the sound is not working after loading the image to the SRAM it may be because the

DE2_115_ControlPanel.sof reconfigures the WM8731 sound chip, so it gets another digital interface.

The solution is to reconfigure it again when you upload your project to the board. To do this:

• Copy K:\TSIU03\Projects\VHDL files\i2c_driver.vhd to your project folder.

• Include it in your project’s top module.

• Connect rstn and clk.

• Generate I/O pins for the other signals (remember from Lab 1).

• Assign pins according to comments in the vhd file.

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References

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