Design of a Real-Time Model of a Photovoltaic Panel

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DEGREE PROJECT, IN POWER ELECTRONICS , SECOND LEVEL STOCKHOLM, SWEDEN 2015

Design of a Real-Time Model of a Photovoltaic Panel

MARKUS FJÄLLID

KTH ROYAL INSTITUTE OF TECHNOLOGY

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Design of a Real-Time Model of a Photovoltaic Panel

MARKUS FJÄLLID

Master of Science Thesis in Power Electronics at the School of Electrical Engineering

Royal Institute of Technology Stockholm, Sweden, June 2014

Examiner: Hans-Peter Nee

XR-EE-E2C 2015:001

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Abstract

Photovoltaic panels are widely used to harvest solar energy. In the general application the panels are connected to an inverter that allows the power to be feed to the grid. The possibility to emulate a photovoltaic panel in a laboratory environment simplifies the development of inverters. Existing solutions are either expensive or not performing good enough. This thesis presents a real-time model that has fast enough transient response to be used with the future’s solar panel inverters. The solution is based on an interleaved synchronous buck converter with an analogue current control loop. A micro-controller is utilizing a look up table to steer the power stage to mimic the output of a real panel. The content of the look up table can be exchanged to emulate an arbitrary photovoltaic panel in different environmental conditions.

The emulator output is stable in the load case with a typical inverter connected to it. It is oscillating with a limited amplitude under open circuit. A hardware implementation of the system confirms the func- tionality. The current controller can correct a load step in 20 µs. The output switching ripple is below 1 mA.

Keywords: Power electronics, Photovoltaic panel, Buck con-

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Referat

Fotovoltaiska paneler är ett väl etablerat sätt att ta tillvara på sole- nergi. Den vanligaste tillämpningen är att panelerna är anslutna till en växelriktare för att möjliggöra att energin matas ut på elnätet. Att kunna emulera en solcellspanel i laboratoriemiljö förenklar utvecklingen av växelriktare. Befintliga system är antingen dyra eller presterar inte bra nog. Denna avhandling presenterar en realtidsmodell som kan han- tera transienta förlopp tillräckligt snabbt för att kunna användas med framtidens solpanelsväxelriktare. Lösningen är baserad på en tvåfas syn- kron buck-omvandlare med en analog strömreglering. En mikroproces- sor använder uppslagstabell för att styra effektsteget till att efterlikna utsignalen från en verklig panel. Innehållet i uppslagstabellen kan by- tas ut för att emulera en godtycklig solpanel i olika driftsförhållanden.

Emulatorns utsignal är stabil med en typisk växelriktare ansluten som last. Utsignalen svänger med en begränsad amplitud under öppen krets.

Experimentiella tester bekräftar funktionen. Strömregleringen kan kor- rigera ett belastningssteg inom 20 µs. Utgångens strömrippel är under 1 mA.

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Acknowledgment

Thanks to Prof. Hans-Peter Nee, supervisor and examiner of the thesis. The meetings have been few but inspiring.

Thanks to Anders Lindgren, CEO at Optistring for the opportunity to work with your skilful team. Special thanks to Gustav Bergquist and Joakim Asplund for the support in the technical design and troubleshooting.

Introduction

This document is the technical report of a Master Thesis at the Royal Institute of Technology (KTH). The project is carried out in the course EJ211X at the depart- ment of Electrical Energy Conversion at the school of electrical engineering.

1.1 Project Background

There is a global demand for more renewable energy. One of the major types is solar power. By using photovoltaic (PV) panels, solar power can be converted to electric power. In order to get the most power out of a PV panel a Maximum Power Point Tracking (MPPT) technique is used. The MPPT is adjusting the electrical load the PV panel sees in order put the PV panel in the optimal working point.

Depending on the panel type and environmental conditions the maximum power point will differ. During the development of MPPT techniques it is useful to be able to emulate the behaviour of a PV panel in real-time to support Hardware In the Loop (HIL) simulations. The outcome of this project is intended to be used in a HIL setup as described in figure Figure 1.1, where the output of the PV emulator will be seen as a PV panel by the test object. The PV emulator has to be well isolated from ground in order to behave as a real PV-panel.

Isolated PSU (AC/DC)

Power Stage (DC/DC)

Controller (Model

Data)

Test Object (MPPT, Inverter)

Power Grid Power Grid

Figure 1.1: Test setup for PV inverter

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CHAPTER 1. INTRODUCTION

1.2 Photovoltaic Panel

A PV cell is a diode with a large area constructed to expose the PN-junction to as many photons as possible. Photons that hit the PN-junction generates an electro- motive force. A PV cell has a typical open circuit voltage of V_oc = 0.6 V . A PV panel is a set of series connected PV cells.

The electrical output of a PV panel can be plotted as output current as a function of the output voltage (IV curve).

A typical 54 cell PV panel IV curve is plotted in Figure 1.2. It also contains a curve of the output power as a function of the voltage. It is seen that the panel have a power maximum of around 160 W at 27 V in the specified operating conditions.

0 5 10 15 20 25 30 35

0 5 10

Voltage (V)

Current (A)

1000 W/m² 800 W/m² 600 W/m² 400 W/m² 200 W/m²

0 5 10 15 20 25 30 35

0 50 100 150 200 250

Voltage (V)

Power (W)

1000 W/m² 800 W/m² 600 W/m² 400 W/m² 200 W/m²

Figure 1.2: Typical voltage, current and power output from a 54-cell PV-panel with various insolation at 25° C.

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1.3. MAXIMUM POWER POINT TRACKING

1.3 Maximum Power Point Tracking

MPPT is the technique to adapt the load of the PV-panel in order to put in the MPP and thus gain the most power from it. Many different methods to do this has been proposed[1].

One of the simplest one is the Constant voltage method. It exploits the fact that the MPP of a PV-panel tends to be located at a fixed ratio of the open circuit voltage, V_oc. The problem is that V_oc will change depending on the environmental conditions, for example a cloud shadow. To find the new V_oc the power generation has to be interrupted and some power is lost. This method is seldom used in practice.

One of the most common techniques of MPPT is Perturb and Observe. It is operating by, as the name implies, making an adjustment in the load to change the output voltage and current. Measure the power. If it has increased, keep moving the same direction. If the power has decreased, reverse direction.

The advantage of this method is that it is easy to implement and is constantly adapting to a moving MPP. The drawback is that it will oscillate around the MPP even at steady state and therefore waste a small amount of power. Many methods to handle this problem are proposed[2].

1.4 PV Inverter Development

Traditional inverters operate on a string of series connected solar panels. A problem with this approach is when some panels are shaded others not. It will result in different operating conditions for different panels. Since the MPPT cannot operate individually on the different panels, some power will be wasted due to not operating in the MPP.

The latest progress in the inverter development is to control every panel individually. One technique to do this is called micro inverters. It enables every single panel to operate optimally by having a separate inverter on each panel. The drawback is the increased system cost and lower efficiency.

1.5 Previous Work

There are published work on the topic of PV-emulators and a few commercial products available on the market.

Many commercial emulators are designed to emulate a full string of solar panels with a single output of hundreds of volts. Such as Chroma 62150H-1000S[3]. These products are used in the development of string inverters but not suitable for micro inverters.

Agilent Technologies have a modular series called E4360[4], which has suitable performance for micro inverters. The product is however marketed for the space

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CHAPTER 1. INTRODUCTION

industry and is thus expensive. A setup that can emulate 16 panels costs over 120,000 USD (2014).

Authors have proposed different methods to emulate PV panels in real time.

Some solutions are based on buck converter and look-up table [5][6]. Some uses linear power stages which gives fast system response and no ripple [7][8]. Some have used numerical ways to solve the IV-curve in equation based PV-models[9].

1.6 System Requirements

The objective of this project is to create a real-time model of a PV panel. It should be small and simple enough to be used in a quantity of 10-20 units. This in order to emulate a typical consumer home setup. The dynamic response of the system needs to be fast enough to track the perturbations from the MPPT algorithm in test. The modules need to be well isolated with low leakage current.

The following is the primary goals that were stated before the project started:

1. Develop a method to emulate the I-V curve of a PV panel with a sufficient accuracy

2. Verify the method in a laboratory setup 3. Document the results

The primary goals are considered critical for the project to be successful.

The following are the secondary goals:

1. Ability to set insolation [W/m2]

2. Ability to adjust capacitance to ground 3. Deliver a fully functioning prototype

The secondary goals considered as good to have but not critical for the projects success.

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Chapter 2

System Overview

This chapter introduces the system concept and included components.

Power Supply (AC/DC)

560 µH +50 v

22 µH

10 µF 3 Ω

Driver Logic

560 µH +50 v

Output

Driver Logic

Look-up table

PI controller

Voltage sample

Current sample

Feedback

Insolation Current

Gain SPI interface

Ref

A/D A/D D/A

Voltage

Digital Analog

Figure 2.1: Conceptual diagram of system

A conceptual diagram of the is displayed in Figure 2.1. It serves as an overview of the system components as well as giving a description of the topology.

The power stage is two half bridges acting as a synchronous buck converter with

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CHAPTER 2. SYSTEM OVERVIEW

two interleaved switching legs. The switching of the legs are phase shifted 180°.

The power stage output is current controlled by an analogue PI-controller in a feedback configuration. A Micro control unit (MCU) is preloaded with a typical IV curve in the form of a look up table (LUT). For each output voltage there is a corresponding output current. The MCU is cyclically fed with a sample of the output voltage form an A/D converter. The corresponding current is found in the LUT and set as a reference value for the PI-controller using a D/A converter.

2.1 Current Controller

The output current control is implemented using operational amplifiers (OP-amps).

The control method is Proportional-Integrating (PI) and is implemented around single OP-amp. The control loop is configured in an average current control fashion by measuring the average output current over a shunt resistor and feed it back to the PI controller. A control loop bandwidth of 50 kHz and a phase margin of 45° is aimed for.

2.2 Balancing

A small unbalance between the switching legs can potentially cause a high current.

It is only the DC resistance in the 560 µF inductors that is limiting the DC current between the two switching legs. To solve this problem an active balancing circuit is implemented.

2.3 Power Stage

Each leg in the H-bridge is controlled from integrated circuit (IC). The IC features internal sawtooth-wave generator and comparator that are used to create the PWM signal. The ICs are configured as master and slave in order to synchronize the ramp- wave to 180° phase shift. The desired effect of the phase shift is to reduce the voltage and current ripple and still maintain small enough filter components. The power stage is designed to handle at least 10 A of current.

2.4 A/D Conversion

Two A/D converters are used. One will sample the output current over a shunt resistor and one will sample the output voltage. The sampled values are feed to the micro controller over an SPI bus.

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2.5. D/A CONVERSION

2.5 D/A Conversion

The D/A controller is feed from the MCU using a 14-bit parallel interface. It converts the current reference value that is used in the analogue PI controller.

2.6 MCU

The MCU is an ARM cortex M4 controller. It has hardware support for floating point calculations. A timer output is configured to periodically request sample from the A/D converter. The digital representation of the output current is found in the LUT (Look-up-table) where the corresponding output current is extracted. The current is converted to an analogue representation in the D/A converter.

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Chapter 3

Theory

This chapter contains some theoretical background to the design.

3.1 PV Model

A commonly used circuit model of a PV-cell is described in Figure 3.1. It is based on a current source with an anti parallel diode. The current I_d is proportional to the insolation [W/m²]. The diode is representing the PN junctions in the PV cell.

Rs and R_sh is equivalent series and shunt resistance.

Ipv

Rs

I

+

− V I_d

Rsh

Figure 3.1: Circuit model of PV panel

A mathematical model can be derived from the circuit model using circuit analysis and Shockley’s diode equation[10]. Accordingly,

I = I_pv− I₀

exp

q(V + R_sI) ak_bT

− 1

−V + R_sI

R_sh , (3.1)

where k_B is Boltzmann constant (8, 61734 · 10⁻⁵ eV /K), a is the diode quality factor, I₀ is the reverse bias saturation current of the diode and q is the electron charge (1.60217 · 10¹⁹ C).

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CHAPTER 3. THEORY

3.2 Buck Converter

A simplified buck converter is shown in Figure 3.2. Where the switch is switching between node 1 and 2 with the frequency F_sw and duty ratio D.

To derive a small-signal model of the converter the switching stage can be simplified.

Under the assumption that there is no time delay and no losses in the switches the buck converter can be divided into two parts, a simple gain and an output filter.

The transfer function from D to output voltage of a LC filter has a double complex conjugated pole which causes a 180° phase shift at the cut off frequency.

Thus,

V_o

D = V_d· (1/LC)

s²+ (1/RC) · s + 1/LC. (3.2) The transfer function from duty-ratio to inductor current I_out can then be written as

Io

D = V_d· s + (1/RC)

L · s²+ (L/C) · s + 1/C. (3.3) In this case there is also a zero present that lifts the phase 90°.

The limiting factor in the achievable system bandwidth is the current inertia in the inductor,

v_L= L ·diL

dt . (3.4)

Under the assumption that v_L is constant, a maximum rate of chance in the average inductor current can be derived as,

∆I_L= V_L

L · t = D · V_d− V_o

L · t. (3.5)

+

− V_d

1 L

+ vL −

Io

+

− V_o 2

C

Figure 3.2: Simplified buck converter

3.3 Interleaved Switching

Interleaved switching is the technique to several switching legs that run in parallel with a phase shifted control. It has the effect that the ripple from the different legs

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3.4. LCL FILTER

are cancelling out each other in the output[11]. If two phases are used and V_dis kept constant the ripple rejection can be plotted as in Figure 3.3. Where R(D) is the rejection caused by the duty ratio in the buck converter and K(D) is the rejection caused by the interleaved switching.

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1

Duty

Ripple Rejection

R(D) K(D) R(D)*K(D)

Figure 3.3: Ripple rejection as function of duty ratio under two phased interleaved switching. R(D) is the ripple rejection caused by unsymmetrical switching pulses and K(D) is the effect from two phased switching. The product of R(D) and K(D) is the resulting ripple rejection in the system. The worst case ripple occurs at a duty ratio of 25 % and 75 %.

3.4 LCL Filter

An LCL filter, Figure 3.4, offers more ripple rejection than the LC filter without affecting the achievable system bandwidth. It also reduces the component values.

The trade-off is the introduction of an extra pole that will make the output oscillatory. The oscillations between L1 and C will be attenuated by the control loop.

The oscillations between L2 and C has to be damped i another way, i.e. a series resistor. The damping factor for a LCR circuit is defined as

ζ = R 2 ·

s C

L, (3.6)

Equation 3.6

where ζ = 1 is a critically damped system.

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CHAPTER 3. THEORY

+

− V_in

I_o L₁ L₂

I_out

+

− V_out C

R

Figure 3.4: LCL-filter with resistor damping

3.5 Current Controller

The following is a transfer function model of a PI controller:

F (s) = A

s ·ω_z+ s

ωp+ s (3.7)

The controller can be implemented using in an analogue circuit as shown in Figure 3.5. The values of the passive components can be calculated in the following steps:

1. Select an arbitrary value of R₁. 2. C₂ = _A·R¹

1

3. C₁ = W_p· C₂_W ²

z2−C₂

4. R₂ = _W ¹

z2·C₁

−

+

Vf b

R1

R2

C2

C₁

Vref

VU

Figure 3.5: Analogue PI-controller

In practice the regulator will have protection against wind up due to the limited supply rails of the OP-amp. The static gain is limited buy a resistor in parallel with C₁.

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Chapter 4

Design and Simulations

4.1 Power Stage

The main limiting factor in the control loop bandwidth is the limited control signal.

If the duty ratio is considered as the control signal, the current change rate limit is described in Equation 3.5. The control signal needed to change the output current is proportional to the output filter inductance. The output current ripple is also proportional to the inductance. Therefore, there is a trade-off between ripple and bandwidth.

An inductance L = 560 µF, V_d = 50 V and V_o = 25 V will give a possible current change rate of 44.6 A/ms. Considering that the most important dynamics to follow are caused by the MPPT algorithm, the current deviations that need to be controlled are small in amplitude. It is decided that the theoretical change rate is sufficient.

Starting from the simplest buck converter there are several ways to improve the trade-off relationship. The ones treated in this work are improved output filter and interleaved switching.

4.1.1 Switching Frequency

An easy way to reduce the output ripple is to increase the switching frequency. This will have the side effect to increase the switching losses. The system efficiency is not critical in this design, but for practical reasons such as heat dissipation and gate driver ability the switching frequency has to be limited.

For manufacturing purposes it is preferred that the transistors will not be over- heated using only the printed circuit board (PCB) as heatsink.

A switching frequency of 300 kHz is chosen as an initial design choice. The worst maximum ripple current is caused at a duty ratio of 50%. The peak-to-peak ripple at the inductor current is then 74 mA and is plotted in Figure 4.1.

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CHAPTER 4. DESIGN AND SIMULATIONS

0 2 4 6 8 10 12 14 16 18 20

−40

−30

−20

−10 0 10 20 30 40

Time [µs]

Current [mA]

Figure 4.1: Inductor current in buck converter with D = 50% , L = 560 µF and Vd= 50 V.

4.1.2 Interleaved Switching

To further improve the reduction of output ripple an interleaved switching technique is adapted. In this design two switching legs are used as displayed in Figure 2.1.

The worst case ripple is now at 25% and 75% duty ratio and is reduced to half in amplitude as shown in Figure 3.3. Furthermore it can be noticed that at a duty ratio of 50% the ripple is fully attenuated. A plot of the ripple current in each phase and the sum is plotted in Figure 4.2. The ripple amplitude is reduced to half, 37 mA peak to peak and the frequency of the ripple is doubled to 600 kHz.

4.1.3 LCL Filter

A extra inductor is added to the output filter of the buck converter to form a LCL filter. The effect is a further reduced current and voltage ripple without affecting the achievable bandwidth significantly. Oscillations are damped using a series resistor as described in Figure 3.4. A damping resistor of 3 Wresults in a ζ = 1 using Equation 3.6, L = 22 µH and C = 10 µF.

The resulting ripple current in the added inductor is plotted in Figure 4.3. The amplitude of the ripple is in worst case 1 mA, which is considered good enough.

4.2 Control

The control of the system can be run in reversible direction. The procedure can either be:

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4.2. CONTROL

0 1 2 3 4 5 6 7 8 9 10

−30

−20

−10 0 10 20 30

time [µs]

Current [mA]

L1 L2 L1+L2

Figure 4.2: Inductor ripple current in 2-phase interleaved buck converter with D = 25% , L₁ = L₂ = 560 µF, V_d= 50 V.

1. Sample output voltage 2. Find corresponding current

3. Set current reference to analogue current controller.

or:

1. Sample output current 2. Find corresponding voltage

3. Set voltage reference to analogue voltage controller.

The most convenient way is to control former one. The load of the system is highly capacitive, which means that it will be a smaller control effort to control the output current. From the buck transfer functions, Equation 3.2 and 3.3, it can be seen that it is easier to maintain an acceptable phase margin with the current controller.

The controller is implemented to control the sum of the currents in the two switching inductors as can be understood by Figure 2.1. Control of the output current from the LCL filter is not suitable with the proposed control method, it would cause oscillations that cannot be reduced without a more complex control network.

The main control loop is chosen to have a bandwidth of f_c = 50 kHz with a phase margin of P M = 45 °.

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0 1 2 3 4 5 6 7 8 9 10

−0.6

−0.4

−0.2 0 0.2 0.4 0.6

Current [mA]

time [µs]

Figure 4.3: Output ripple current in buck converter with interleaved switching and LCL filter. D = 25% , L₁ = L₂= 560 µF, L₃ = 22 µF, and V_d= 50 V.

4.2.1 Control Parameters

The control parameters for Figure 3.5 are selected using the K-factor approach[12]

and converted to component values using the equations presented in Equation 3.7.

The calculations are done using only the simple TF model of the buck converter in Equation 3.3 and a gain factor to compensate for the modulation and measurement gains.

First, the phase φ_c is calculated at the intended crossover frequency ω_c. From the phase a boost constant is calculated as

boost = P M − 90^◦− φ_c, (4.1)

which is the phase lift-needed from the controller to meet the design criterion.

From the boost, the K-factor can be calculated[12] as K = tan

45 −boost 2

. (4.2)

The pole and zero of the controller can then be calculated as ω_p = ω_c

K (4.3)

and

ωz = ω_c· K. (4.4)

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4.2. CONTROL

4.2.2 Stability

The stability of the system is investigated using bode analysis. The system is stable if the phase margin and the gain margin is positive. Furthermore, the crossover frequency has to be below half the switching frequency. Bode plots with varying loads are presented in Figure 4.4. The criterion for the system to be stable is fulfilled. The deviations caused by the different loads are not affecting the phase at the crossover frequency. The system is therefore considered robust against changes in the load.

−100

−50 0 50 100 150

Magnitude (dB)

10⁰ 10¹ 10² 10³ 10⁴ 10⁵ 10⁶ 10⁷

−180

−135

−90

−45 0

Phase (deg)

Bode Diagram

Frequency (Hz)

R=5 R=10 R=50 R=100 R=500

Figure 4.4: Bode plot of open loop gain with varying resistive load.

4.2.3 Balancing

The two interleaved phases are actively balanced to ensure equal mean current in the both phases. Unbalance between the phases will increase the ripple and lower the efficiency of the converter. In the worst case it can damage the transistors.

The DC resistance between the two switching nodes are the series resistance in the two inductors, R_L1 and R_L2. If the unbalance current I_ub is defined as the difference of the currents in the two phases, it can be calculated as:

I_ub= V_sw1− V_sw2

R_L1+ R_L2 , (4.5)

where V_sw1 and V_sw2 are the average voltages in the two switching nodes. It is clear from the fact of the relatively small DC resistance in the coils that even a tiny average voltage difference will cause big unbalance currents. Temporary voltage

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differences will, however, not be a problem due to the large AC resistance caused by the inductance.

The concept of the balance circuit can be seen in Appendix A. The operation can be divided into the following steps:

1. Measure the voltage in each switching node.

2. Low-pass filter the signals.

3. Find the difference of the signals using a differentially connected OP-amp.

4. Use the output to offset the control signal in the switching circuit.

The OP-amps are low-pass filtered to achieve an approximately integrating behaviour with a low bandwidth that will only act on the average voltage. The low bandwidth also prevents the balancing circuit from interfering with the current controller and potentially cause instability.

4.2.4 Dynamic Behaviour

The system is simulated in LTspice IV with the setup described in Appendix A. A step response of the output current is plotted in Figure 4.5.

0 10 20 30 40 50 60 70 80 90 100

5 5.02 5.04 5.06 5.08 5.1 5.12 5.14 5.16

Time [µs]

Current [A]

I_out I_L1+L2

Figure 4.5: Step response from 5 to 5.1 A.

A response from a load step is plotted in Figure 4.6.

4.3 Capacitance to Ground

The capacitance to ground is minimized by using a well isolated power supply.

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4.4. LUT

0 10 20 30 40 50 60 70 80 90 100

4.98 4.985 4.99 4.995 5 5.005 5.01

Time [µs]

Current [A]

I_out I_L1+L2

Figure 4.6: Load step

4.4 LUT

The equation describing the relation between current and voltage in a PV-panel, Equation 3.1, is nonlinear and difficult to solve. In this system where the current has to be updated in real-time with a high frequency, the most convenient utilisa- tion is a LUT.

The drawback is the limited achievable resolution. The most important operation area of the emulator is around the maximum power point. The resolution can thus be bettered by using a dynamic step size in the table. Where the highest data density is in the maximum power point area. The resolution can also be increased by real-time interpolation.

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Chapter 5

Implementation

The implementation of the system is limited to the hardware, i.e. power stage, balancing circuit and current controller. The software, i.e. sampling, LUT and logging are postponed for future work.

5.1 Hardware

The hardware is implemented directly on a custom PCB. The system contains both fast switching signals together with sensitive analogue signals. Therefore a breadboard test setup or similar is not convenient. Furthermore most modern ICs are of surface mounted device (SMD) type.

To give room for changes the PCB is designed to be as flexible as possible.

Circuits that are not necessarily needed are added just in case of something is not working as intended.

5.1.1 Component Selection

The components are selected with priority to the performance. Some important factors are listed here:

1. Possibility to hand solder (No BGA) 2. Performance

3. Availability 4. Size

5. Price

ADC

The ADC is AD7689 from Analog devices. It is 16-bit ADC with a sampling frequency of 250 ksps. It is communicating using a Serial Peripheral Interface (SPI) bus. The bus is possible to run at frequency of up to 50 MHz. Two ADCs are used to simultaneously sample both current and voltage.

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CHAPTER 5. IMPLEMENTATION

DAC

The DAC used is AD9764 from Analog devices. It has a 14-bit resolution with a parallel interface. The typical settling time is 35 ns.

Micro Controller

Two ARM Cortex M4 MCUs are drawn into the PCB. One that runs the LUT and one that handles data logging and communication. The model is a K22 from Freescale.

Buck Controller

The implementation of the buck controller is simplified by using a Application Spe- cific Integrated Circuit (ASIC). TPS40170 [13] from Texas Instruments is chosen.

It is a voltage controller for synchronous buck converters. The external feedback makes it possible to modify the circuit into a current controller.

Interleaved switching is utilized by a master slave configuration. The master out- puts a clock signal that is used by the slave to synchronise the switching of two ICs with 180 °phase shift.

It also features built-in dead-time control, MOSFET drivers, sawtooth wave generator, comparator, over current protection etc.

In this design two ICs are used with 180° phase shift as described in subsec- tion 4.1.2. This creates a two leg synchronous buck regulator with interleaved switching.

Transistors

Considering the switching frequency and voltage under operation the most convenient type of transistor is MOSFET.

5.1.2 Schematic

The schematics are drawn using the software Eeschema that is a part of the open source PCB development environment Kicad. The schematics can be seen in Ap- pendix B. The component values stated are not final.

5.1.3 PCB

The PCB is drawn in Pcbnew in Kicad. The PCB is composed on four layers ac- cording to Table 5.1. Analogue, digital and power circuits are separated to minimize problems with disturbances on the low level signals. The ground plane is also split up to further isolate the noisy switching circuits from the analogue ones. Detailed plots of the PCB are available in Appendix C.

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5.1. HARDWARE

Table 5.1: PCB layers Layer Type 1 (top) Signal

2 Ground

3 Supply

4 (bottom) Signal

5.1.4 Soldering

All soldering is done by hand in house. The partly finished product is shown in Figure 5.1.

Figure 5.1: The partly finished PCB.

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5.1.5 Tuning

Switching

The system was modified and tuned to keep an acceptable temperature of the switching MOSFETs.

During initial testing, the MOSFETSs were cooled only by the PCB. The temperature was noticed to be alarmingly high at higher output currents. Current levels above a few amps could only be maintained for seconds without risking to damaging the components.

As a first step to overcome the problem a heatsink was glued directly to the MOSFTEs. A digital thermometer was attached to the heatsink to enable monitor- ing of the temperature.

The temperature of the heatsink was stabilized to 100° C after 10 min of 9 A output current at 36 V. The temperature was reduced to 60° C by adding a cooling fan, see Figure 1.1.

To further reduce the temperature the switching losses are investigated. The gates were driven by a series resistance of 22 W. The rising edge of the switching node is plotted in Figure 5.2. The behaviour is good with no present oscillations.

The rise time is about 20 ns.

Figure 5.2: Rising edge. Channel 1 is the voltage at the switch node of phase 1 and channel 2 is the voltage at the gate of the high side MOSFET. 22 W gate drive resistance.

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5.1. HARDWARE

The gate series resistance is later bypassed with the result of a reduced temperature to 90° C and 56° C with fan. The resulting voltage of the switching node is plotted in Figure 5.3. Some damped oscillations are now present. The rise time is reduced to about 10 ns which explains the reduced temperature.

Figure 5.3: Rising flank. Channel 1 is the voltage at the switch node of phase 1 and channel 2 is the voltage at the gate of the high-side MOSFET. No series gate drive resistance.

Balancing

The balancing circuit was tuned to an acceptable performance.

The system was first tested without the balancing circuit activated. The unbalance current was monitored with a multimeter as shown in Figure 5.4. The circuit was shown to be sensitive to disturbances from the surrounding, i.e. the capacitive coupling from a fingertip. The current was to unstable to give a meaningful numerical notation.

The balancing circuit was added and a more stable value of the unbalance current was observed. The deviation from perfected balance were now constant about 25 %.

It can be understood from the concept of the system that small differences in voltage of the two switching legs give rise to high unbalance currents, see Equa- tion 4.5. Therefore, the OP-amp needs to have a low offset voltage and the resistor dividers that are measuring the voltages needs to be well matched.

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Figure 5.4: Measuring of unbalance current.

The constant deviation implies a static error that were compensated for by tuning one of the resistor dividers.

5.2 Firmware

The firmware is written in C and compliled with the GCC based compiler Arm- None-Eabi. The LUT is generated from the model described in section 3.1. At startup Equation 3.1 is solved for every possible output voltage that can be sampled.

Then, the following sequence is run from a timed interrupt:

1. Sample output current by external ADC 2. Find corresponding output current in LUT 3. Set the DAC to the output current value

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Chapter 6

Results and Discussion

6.1 Test Setup

The power converter and the current controller is set up to verify the design and operation. The setup can be seen in Figure 6.1. The board is fed from a 48 V power supply and the output is connected to a resistive load. The LUT and digital controller are not implemented at this stage, instead the current reference value is set directly by a trim potentiometer. The output DC level is monitored using a multimeter and the AC component is measured using a Pearson current transformer.

6.2 Performance

The performance of the circuit is analysed using an oscilloscope. The output current ripple is plotted in Figure 6.2. The test is done with 25 % duty cycle which is the worst case scenario for the ripple. The result of a 1 mA peak to peak ripple agrees well with the simulations.

The control loop is tested by a load step from 16 W to 4 W. The plots are shown in Figure 6.3. The peak deviation in current reaches 310 mA. The current is back within ±1 % after ~20 µs. The current deviation is mainly caused by the capacitor in the output filter. The current in the inductors before the capacitor is diverging less than what can be measured with the method used. It is confirmed by the simulation in Figure 4.6.

A smaller capacitor would make the system more robust at the cost of higher output ripple.

6.3 Discussion

In the early stages of the project different design paths were investigated and dropped to narrow down the most suitable solution for this problem. Due to the limited time-frame only one prototype could be built and fully evaluated.

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CHAPTER 6. RESULTS AND DISCUSSION

Figure 6.1: Laboratory setup.

6.3.1 Switching Topology

The power stage were decided to be of a switching type due to the relatively high power involved and the wide output range. The main drawback of this has been the struggle to keep down the ripple levels and still maintain enough control bandwidth.

Soft switching topologies have been investigated, i.e. switching with zero switching losses. Lower losses in the transistors enables higher switching frequencies and therefore allows the output ripple be low with reduced output filter. Zero Voltage Switching (ZVS) and Zero Current Switching (ZCS) resonant converters were investigated. But they are both sensitive to dynamic loads and varying load cases and are therefore not suitable in this application. A more promising ZVS topology refereed to as Clamped Voltage topology have been simulated. But again the problem have been to maintain the soft switching in the wide output span and during transients from a dynamic load.

If faster transient response than what was achieved in this project is needed, a class-H design is a good approach, i.e. use a linear current regulation that is feed from variable voltage rails. It would allow the output filter to be eliminated. The drawback is a more complex system and higher losses.

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6.3. DISCUSSION

Figure 6.2: Plots of switch nodes and current ripple. Channel 1 and 2 is the two switching nodes. Channel 3 is the AC component of the output current. The duty ratio is 25 %.

6.3.2 Current Control

In early stages of the project different strategies for the PWM control were considered. Due to the demand of high accuracy and system bandwidth the idea of a digital controller is dropped. To maintain the 50 kHz system bandwidth the rule of thumb suggests a ten times higher sampling frequency of 500 kHz. Sampling with high speed and accuracy is both difficult and expensive, therefore an analogue control approach is adopted. Also, there is no simple MCU that has the computational power needed to process the data in such fast rate. A digital control would offer more flexibility in the choice of control algorithms and is easier to tune and modify.

6.3.3 Implementation

The practical implementation has been the most time consuming part of the project.

Many hours were spent on reading datasheets and comparing active components such as ADCs, OP-amps and gate-drivers. Drawing the circuit board also took some iterations before the design could be considered good enough to be sent to manufacturing. The soldering work went out quite smooth except for some patching work.

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Figure 6.3: Load step from 16 W to 4 W with reference set at 3 A. Channel 4 is the output voltage and channel 3 is the AC component of the output current.

6.3.4 Selecting PWM controller

Even though there is huge range of ICs on the market, it was really difficult to find a suitable integrated PWM controller. Most PWM controllers are constructed to have a fixed output, usually voltage. Where the project needs a dynamic current output.

Also the wide output voltage range caused a lot of trouble since most controllers has built in protection mechanisms that can be falsely triggered by some valid load cases, such as short circuit. Considering all the difficulties to find an appropriate PWM controller one can argue it may have been easier to construct a custom one around generic OP-amps etc, but the circuit would have been unproportionally large considering the construction of the two phase-shifted PWM carriers and dead-time control etc. The final solution using two TPS40170 is an overall acceptable solution for a prototype. But there are a few disadvantages that needs to be mentioned.

Firstly it is the need of the balancing circuit that has to be carefully tuned. Secondly it is the integrated LDO regulator that feeds the gate drivers. It means that higher supply voltage to the IC will result in higher power dissipation. With a 48 V power supply that has been used during testing the temperature raised to about 80°C with an ambient temperature of 25°C. This implies that the circuit has to be fan-cooled.

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6.4. FUTURE WORK

6.3.5 Problem with burned PCB

The PWM controller have been causing some major time delays due to heavy break- down. Under several occasions when TPS40170 have been stressed beyond maximum ratings and the circuit has burned. But in addition to just stop working, it also has tied the supply rail to ground to the extent that the supply trace has started to glow and burnt a hole through two layers of the PCB. In one of the occasions the PCB was damaged so bad, that it could not be repaired. Instead new board had to be soldered from scratch.

6.3.6 Problem with oscillations

Output oscillations have been noticed under certain load cases. Especially with high resistance loads. The oscillations seems to be caused by instabilities in the outer most control loop, i.e. the LUT-loop. The LUT-loop has a non-linear gain due to the non-linear characteristic of a PV-panel, see Figure 1.2. Since the LUT is acting on the output current as function of the output voltage also the load impedance is affecting the gain of the loop. With a resistive load the gain of the load is the actual resistance. This means that in open circuit, the gain is infinite. But due to low pass filters and peaking control signals, the loop gain is kept down to a finite value at the cross over frequency. At high impedance loads the phase margin is low enough to make the output oscillatory.

Under low imedance loads, such as low resistance or high capacitance, the output is stable. This also includes nominal operation, with a PV-inverter connected to the output. But with high impedance loads, such as open circuit, the output oscillates at 1-10 kHz and ˜100 mV peak to peak. One possible way to solve this is to make the LUT firmware more complex by adding detection of high impedance loads, and then control the output voltage based on the output current instead. This would make the gain caused by the load impedance to be inversed and thus lower the loop gain. Another solution would be to further low pass filter the loop. But that is not desired as it would reduce the system bandwidth too much.

6.4 Future Work

The rest of intended features to be implemented and tested are:

• Data logging using the second processor

• Communication using an isolated bus

• Boot loader on processor

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6.5 Conclusion

A concept and design of a solar panel emulator have been created. Initial simulations and laboratory tests shows a promising result in terms of performance. But there are room for improvements to make the system more robust and reliable. The system performance is investigated using custom hardware. The output is oscillating with limited amplitude under certain load cases. For instance open circuit and with purely resistive loads at high resistance. Connected to a typical PV-inverter, i.e.

voltage controlled load or highly capacitive loads, the system is performing well. The active balancing circuit is sensitive to the component tolerances and disturbances.

A load step is regulated within ~20 µs and the output current ripple is below 1 mA.

All primary goals are fulfilled.

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Bibliography

[1] T. Esram and P. L. Chapman, “Comparison of photovoltaic array maximum power point tracking techniques,” IEEE TRANSACTIONS ON ENERGY CONVERSION EC, vol. 22, no. 2, p. 439, 2007.

[2] N. Femia, G. Petrone, G. Spagnuolo, and M. Vitelli, “Optimization of perturb and observe maximum power point tracking method,” Power Electronics, IEEE Transactions on, vol. 20, no. 4, pp. 963–973, 2005.

[3] Chroma, “Programmable DC Power Supply (Solar Array Simulation).”

[Online]. Available: http://www.chromausa.com/pdf/62150H-600S-E.pdf [4] Agilent Technologies, “Agilent E4360 Modular Solar Array Simulators,” 2014.

[Online]. Available: http://cp.literature.agilent.com/litweb/pdf/5989-8485EN.

pdf

[5] F. Yusivar, M. Farabi, R. Suryadiningrat, W. Ananduta, and Y. Syaifudin,

“Buck-converter photovoltaic simulator,” International Journal of Power Elec- tronics and Drive Systems (IJPEDS), vol. 1, no. 2, pp. 156–167, 2011.

[6] R. González-Medina, I. Patrao, G. Garcerá, and E. Figueres, “A low-cost photovoltaic emulator for static and dynamic evaluation of photovoltaic power con- verters and facilities,” Progress in Photovoltaics: Research and Applications, vol. 22, no. 2, pp. 227–241, 2014.

[7] D. Schofield, M. Foster, and D. Stone, “Low-cost solar emulator for evaluation of maximum power point tracking methods,” Electronics Letters, vol. 47, no. 3, pp. 208–209, 2011.

[8] D. Kapoor, P. Sodhi, and D. Deb, “Solar panel simulation using adaptive control,” in Control Applications (CCA), 2012 IEEE International Conference on. IEEE, 2012, pp. 1124–1130.

[9] J.-H. Jung, M.-H. Ryu, J.-H. Kim, and J.-W. Baek, “Power hardware-in- the-loop simulation of single crystalline photovoltaic panel using real-time simulation techniques,” in Power Electronics and Motion Control Conference (IPEMC), 2012 7th International, vol. 2. IEEE, 2012, pp. 1418–1422.

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BIBLIOGRAPHY

[10] M. G. Villalva, J. R. Gazoli et al., “Modeling and circuit-based simulation of photovoltaic arrays,” in Power Electronics Conference, 2009. COBEP’09.

Brazilian. IEEE, 2009, pp. 1244–1254.

[11] C. Chang and M. A. Knights, “Interleaving technique in distributed power conversion systems,” Circuits and Systems I: Fundamental Theory and Appli- cations, IEEE Transactions on, vol. 42, no. 5, pp. 245–251, 1995.

[12] N. Mohan, T. M. Undeland, and W. Robbins, “Power electronics: converters, applications and design, 1995,” pp. 333–336, 1997.

[13] Texas Instruments, “TPS40170, 4.5-V to 60-V wide-input synchronous PWM buck converter,” 2011. [Online]. Available: http://www.ti.com/lit/ds/

symlink/tps40170.pdf

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Appendix A

LTSpice Simulation

This appendix contains the LTSpice setup that is used for step response simulation.

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APPENDIX A. LTSPICE SIMULATION

L2 560µCf 10µ

V5 60

V6 5 PWL repeat forever (file=1000mA_pp.pwl) endrepeat

V2 0AC 1.

V3 L3 22µB3 V=max(0,min(50,15*V(u2))) Rf 3

V4

PU LS E(25 25.054 20m 0.

2m 0.

2m 0 0.4m )

R9 10m

L1 560µB2 V=max(0,min(50,15*V(u1))) R15 1m

C8 350p

R24 22k

C9 72p R25 1.725k

R26 100k R27 100k

R28 10k R29 10k B1 V=V(step)/10+0.1

U6 U7

R30 2.7k

R31 15k R32 15k

R33 2.7k1N4148

D6R34 2.2k

R35 2k R36 2k

U8 LT6221

R37 100k

R38 100k R39 5k

R40 5k10n C10C11 10n

R41 1k

R42 1k R43 1000k

R44 1000k

C12 100n C13 100n

R45 100

U9 LT6221

R46 1000k

R47 1000k

C14 100n C15 100n

R48 100

U10 LT6221

R49 1k

R50 1k U11 LT6221

U12 LT6221

U13 LT6221 R51 1m

C17 2.2p C18 2.2p

V7 3.3 PULSE(5 5.015 19.005m 0.2m 0.2m 0 0.4m)

V9

V8 0.1 V1

PU LS E(20 20.1 20m)

PULSE(5 5.1 22m)

V10

OUT +

+5v +60v

SW2 stai

r

step e sin

OUT -

SW1

ref

u1 u2

+3v3

SW2 SW1 +3v3 +3v3

+3v3 +3v3

f

bal1 bal1

bal2 bal2 I_sense+

I_sense+

I_sense- I_sense-

0v1ref

I_sense

0v1ref

ramp

;.ic V(out+) = 25

;.ic V(f) = 25

.tran 0 20.1m 20m 1u startup ;tf V(OUT) V3

;ac oct 10 0.01 1000meg .include opamp.sub

Active balancingPower supply Control reference Power stagePI controllerCurrent sense gainLoad --- C:\Users\Markus\Dropbox\Exjobb\Spice\buck_v9_OL.asc ---

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Appendix B

Schematics

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Appendix C

PCB

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TRITA XR-EE-E2C 2015:001

www.kth.se

Design of a Real-Time Model of a Photovoltaic Panel

Design of a Real-Time Model of a Photovoltaic Panel

Design of a Real-Time Model of a Photovoltaic Panel

Abstract

Referat

Acknowledgment

Contents

Chapter 1

Introduction

1.1 Project Background

1.2 Photovoltaic Panel

1.3 Maximum Power Point Tracking

1.4 PV Inverter Development

1.5 Previous Work

1.6 System Requirements

Chapter 2

System Overview

2.1 Current Controller

2.2 Balancing

2.3 Power Stage

2.4 A/D Conversion

2.5 D/A Conversion

2.6 MCU

Chapter 3

Theory

3.1 PV Model

3.2 Buck Converter

3.3 Interleaved Switching

3.4 LCL Filter

3.5 Current Controller

Chapter 4

Design and Simulations

4.1 Power Stage

4.2 Control

4.3 Capacitance to Ground

4.4 LUT

Chapter 5

Implementation

5.1 Hardware

5.2 Firmware

Chapter 6

Results and Discussion

6.1 Test Setup

6.2 Performance

6.3 Discussion

6.4 Future Work

6.5 Conclusion

Bibliography

Appendix A

LTSpice Simulation

Appendix B

Schematics

Appendix C

PCB