Figure 2.12 presents the decoding performance of the FTN receiver for different time spacings (T∆). It can be seen that at higher SNRs, the receiver perfor-mance is quite good and approaches the theoretical limit corresponding to the BER curve for the (7, 5) convolutional code (T∆ = 1.0) in an interference free Gaussian channel [Rus07, Lee01]. At lower SNRs the deviation is significant as the induced interference is hard to clean when the symbols are stacked close together. For SNR = 5dB, the FTN system using T∆ = 0.4 still has bad performance compared with lower SNR levels, while for T∆ ≥ 0.5 it improves significantly. It is evident from Figure 2.12 that one could employ the FTN
sys-2It is to be noted here that the indices k, ℓ refers to the sub-carrier and time instances on FTN/non-orthogonal grid
3Since F∆is fixed at 1, the FTN signaling parameter T∆F∆is sometimes simply referred to by T∆
0 2 4 6 8 10 10−6
10−5 10−4 10−3 10−2 10−1 100
SNR (E b/N
0) in dB
bit error rate
T∆=0.4 T∆=0.45
T∆=0.5 T∆=0.7
T∆=1.0
T∆=0.9 T∆=0.6
Figure 2.12: Receiver performance for varying time spacings T∆ with 3x3 projection coefficients.
tem to achieve higher bandwidth efficiency when channel conditions are good.
The FTN system provides 2x improvement in bandwidth efficiency when com-pared to an OFDM system using the same modulation at the cost of extra complexity in receiver processing. It was found that 8 iterations are sufficient to generate close to optimal results in terms of the decoding performance.
Our work presented in [DRAO09] has shown that the number of projection points is crucial for the overhead in transmitter complexity. The case is sim-ilar for the receiver since the same mapper is used in the SIC. The MF, the other component of SIC, also has the same order of computational complexity per FTN symbol as that of the FTN mapper. Hence the number of projec-tion coefficients play a major role in the receiver complexity as well. Ideally, all projection coefficients have to be considered to completely reconstruct the Gaussian pulse carrying FTN symbols, hereby simply referred to as an FTN pulse.
In Section 2.1.1 it was shown that in order to represent the FTN pulse fairly accurately, 3 × 3 projection coefficients are required when using the IOTA pulse. However, this does not say much about the degradation in receiver
34 2.6. Receiver performance
0 1 2 3 4 5 6 7 8 9
10−7 10−6 10−5 10−4 10−3 10−2 10−1 100
SNR in dB
bit error rate
T∆ = 0.5, 3x3 T∆ = 0.6, 3x3 T∆ = 0.7, 3x3 T∆ = 1.0, 3x3 T∆ = 0.5, 5x5 T∆ = 0.6, 5x5 T∆ = 0.7, 5x5 T∆ = 1.0, 5x5
Figure 2.13: Bit Error Rate comparison between 3x3 and 5x5 projec-tion coefficients with T∆= {0.5, 0.6, 0.7 and 1.0}.
performance. In order to evaluate the impact of using different number of projection coefficients, the receiver is evaluated for configurations 3 × 3 and 5 × 5.
The receiver is simulated using the system setup shown in Figure 2.11. The results are presented in Figure 2.13 showing the performance comparison when the FTN system is operated at different spacings (T∆) at varying SNRs and projection points being 3 × 3 and 5 × 5. The solid line is the performance for 3 × 3 projection points, while the dashed lines show the performance for 5 × 5 with all other parameters remaining the same. Using 5 × 5 projection coefficients requires 25 operations per FTN symbol, while the 3 × 3 requires only 9. The performance curves from Figure 2.13 show that the improvement from 5 × 5 coefficients is only marginal when compared to 3 × 3. This shows that the complexity is kept moderate by using 3 × 3 projection coefficients with only small degradation in performance.
Going beyond 5 × 5 is computationally intensive and prohibitive when con-sidering hardware implementations. Though 9 × 9 projection coefficients was evaluated for the FTN transmitter, it was for this reason that it was not
consid-ered for evaluation in the receiver. It can also be noted that 9 × 9 coefficients was the minimum requirement when using rectangular basis, indicating the inappropriateness of its choice for FTN.
2.6.1 Finite wordlength considerations.
A step closer towards implementation of the FTN receiver in hardware is to determine the finite wordlength requirements in the processing blocks. This is done by evaluating the receiver model under fixed point considerations. The iterative decoder passes the LLRs back and forth between the two component decoders. These LLRs are numbers represented in the log domain. Hence when performing calculations on the LLRs, it may be sufficient to represent them using fewer bits, or in other words, cover a small dynamic range with respect to the LLRs. Due to the log scale, a small dynamic range for the LLRs corresponds to a very wide dynamic range in the actual scale. Table 2.1 shows evaluated fixed point representation in this work and two other works from literature [MB00, MWW00].
Table 2.1: Comparison showing wordlengths evaluated in this work and two other works from literature.
Integer Fractional wordlength wordlength
[MB00] 3 2-3
[MWW00] 5 3-4
This work 4 2,4,6
The chosen wordlengths are primarily used for the representation of LLRs.
The same wordlength is also used within the inner decoder to represent the soft symbols and the values during SIC. Higher precision helps in better represen-tation of these soft symbols when SIC is carried out. The range of the LLRs is set to ±5 as the decoder rarely reverts from high LLR values. To cover this dy-namic range 4 bits is sufficient and hence the integer part is fixed at 4 bits. The fractional wordlength was determined by evaluating the receiver performance using 2, 4 and 6 precision bits. At all interfaces between the blocks depicted in Figures 2.5, 2.8 and 2.9 the inputs are quantized with the above mentioned wordlengths. Internal to the blocks, full precision is maintained and the final result is quantized to same the wordlength as the input and are passed on to the subsequent blocks.
36 2.6. Receiver performance
0 2 4 6 8 10
10−6 10−5 10−4 10−3 10−2 10−1 100
SNR (Eb/N0) in dB
bit error rate
T∆=0.9
T∆=0.5 T∆=0.4
T∆=0.45
Figure 2.14: Performance of fixed point receiver model (dash-dot lines:
8 bit, dotted lines: 6 bit wordlength) in comparison with floating point benchmark (solid line).
Figure 2.14 shows the performance from fixed point simulations with wordlengths of 6 bits and 8 bits in comparison with the floating point per-formance. The solid lines correspond to the BER curves of the model using floating point precision, while the dash-dotted and dotted curves represent the BER performance with fixed point representation using 8 bits and 6 bits respectively. It can be seen that the performance of the fixed point model using 8 bits closely follows the full precision counter part, while that using 6 bits is significantly farther away from the ideal curve. The performance with 8 bits deviated from the floating point performance only by a few fractions of a dB. Increasing the wordlength further to 10 bits will only increase the hardware complexity with negligible improvement in performance.
Figure 2.15: General grid of FTN and OFDM symbols.
2.6.2 Fixing the block size for interleaver/de-interleaver design.
In this work, the size of the information block is chosen to be 2016, a specifi-cation from the 3GPP standard [3GP07]. This choice of block size is to show compatibility of FTN system with standardized systems as well as to use the well defined specifications for hardware implementation.
The performance of a system with a block size of about 1000 has a margin of 1 − 2 dB worse than that employing a block size of 104 or 105 [BDMP98].
Comparing the performance degradation to the latency and memory require-ments for handling large block sizes of 104, a block size of ≈ 2000 is reasonable from an implementation point of view.