Figure 4.7: Layout of RAM based implementation of the FTN mapper in 130nm CMOS process.
As a result, the address decoder for the LUTs in RAM based architecture tend to have larger overhead than that in the register based counterpart which is shown in the comparison table. Overall, the RAM based approach saves more than 50% of the area when compared to the register based architecture.
4.4 Summary
This chapter has presented a look-up table based hardware architecture for realizing FTN signaling in the transmitter. The FTN system is operated with time and frequency spacings T∆ and F∆ at sub-optimal operating points so that the LUT that stores the projection coefficients have a repetition pattern resulting is small sizes of LUTs. Initially a register based implementation was proposed. Though such an implementation is fast, it has a high area overhead.
Hence, speed is traded for area by using RAMs instead. The RAM based architecture has been verified on a Xilinx FPGA for its functionality and its complexity is compared with an IFFT implementation. The mapper was also synthesized for a 130nm CMOS process and was found that memories were a dominant factor in the FTN mapper.
FTN Receiver: Hardware Architecture and
Implementation
The design and implementation of baseband processing blocks is one of the key challenges in wireless receivers. Earlier, the transmitter was evaluated to demonstrate that it need not be too complex but that an add-on processing block can realize transmission of data using FTN signaling. A similar approach is undertaken in the implementation of the decoder in the FTN receiver. This chapter discusses the hardware architecture and implementation of parts in the receiver responsible for decoding the received symbols into bits. The receiver proposed in Section 2.3 already did consider re-using the processing blocks to realize different functions hinting at less overhead in the receiver. The following sections detail the hardware architecture of each of the blocks and the motiva-tion to realize so. The proposed hardware architecture primarily focus on the inner decoder as it is specific to FTN signaling. While the outer decoder is a max-Log MAP approximation of the BCJR decoder for the (7, 5) convolutional code.
The architectural description of the processing blocks are organized in the same way as the received symbols are processed in the receiver. The IOTA pulse shaping filter used as a part of multi-carrier demodulation is separately discussed in Chapter 7. The FFT, being one of the most extensively researched topic for efficient and optimized hardware implementation is not considered for the very reason. The hardware architecture of the remaining processing blocks will be discussed before applying any optimizations. A simplified block diagram
69
70 5.1. Matched Filter architecture
Figure 5.1: Block diagram of the FTN receiver chain.
time
freq
FTN symbol Orthogonal symbol
0 1 N−1
0 1 2 3 M−1
M −1
FTN
f f f
t t t t t
0 1 2 3
t’ t’ t’ t’ t’
N −1
FTN
f ’
0 1
f ’
f ’ x
x
x x
x
x x
x
x C C
C C
C
C C
C C
01 02 03
11 12 13
21 22 23
01 02 03
11 12 13
21 22 23
FTN symbol at (t’,f ’)10
P
Figure 5.2: Time frequency grid showing the MF operation and com-putational diagram of Eqn. (2.23).
of the receiver is recollected from the previous chapters and is shown in Figure 5.1. The following sections consist of descriptions of the matched filter, inner decoder with soft output calculation, successive interference canceler, and the LLR calculation followed by a brief description of the outer decoder.
5.1 Matched Filter architecture
The hardware architecture of the matched filter algorithm described in Section 2.3.1 is explained using Figure 5.2. The time instances and sub-carriers for the FTN symbols are denoted as t′ℓ and fk′ while, tn and fm denotes indices for orthogonal symbols. In order to reconstruct the FTN symbol at (t′1, f0′), the orthogonal symbols at time instances t1, t2, t3and sub-carriers f0, f1, f2 are required when Nt× Nf = 3 × 3 is used. The symbols at these orthogonal time instances are denoted as x01, x02. . . , x23with the corresponding projection coefficients C01, C02. . . , C23. The matched filter operation requires Nt× Nf multiplications whose outputs are accumulated to obtain the reconstructed FTN symbol.
Figure 5.3: Architecture of the matched filter with triplicated LUTs and arithmetic units.
The maximum number of simultaneous FTN symbols that can be calcu-lated when 3 time instances of orthogonal symbols are available varies from 1 − 3, depending on T∆. Several FTN symbols can be calculated concurrently because each FTN symbol at the transmitter is projected onto the nearest Nf
sub-carriers and Nt time instances with respect to the FTN symbol. Hence, with a smaller time spacing there can be several FTN symbols that can be mapped onto the same set of orthogonal basis functions. Of all the time spac-ings considered in this work, T∆ = 0.4 has the smallest separation between adjacent FTN symbols, which gives the highest number of FTN time instances that may be calculated simultaneously (= 3). Accordingly, 3 arithmetic units and LUTs will be required to calculate the FTN symbols in parallel.
For illustration consider the time-frequency grid in Figure 5.2, when time instances t0, t1 and t2 are available, only 1 of the 3 arithmetic units will be used to compute the output corresponding to FTN time instance t′0. Similarly, 2 arithmetic units will be required to calculate FTN time instances t′1 and t′2 when t1, t2 and t3are available. In this way, depending on the orthogonal time instances currently being processed as well as time spacing T∆, the arithmetic units 1 − 3 are enabled accordingly.
The architecture of the matched filter with 3 arithmetic units is shown in Figure 5.3. It consists of 3 buffers indicated as ‘input buffer’ which stores the demodulated symbols and are read into the arithmetic units for FTN symbol reconstruction. If FTN symbols corresponding to 2 time instances are