Highly Linear Mixer for On-chip RF Test in 130 nm CMOS

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Highly Linear Mixer for On-Chip RF

Test in 130nm CMOS

Master thesis performed at division of Electronic Devices

by

Ghulam Mehdi

Thesis No: LiTH-ISY-EX--06/3913--SE

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Highly Linear Mixer for On-Chip RF Test

Master thesis in Electronic Devices

at

Linköping Institute of Technology

by

Ghulam Mehdi

LiTH-ISY-EX--06/3913--SE

Supervisor: Dr. Jerzy Dabrowski Examiner: Dr. Jerzy Dabrowski

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Presentation date: 2006-12-15 Publication date:

Division of Electronic Devices Department of Electrical Engg.

Language ●English Swedish Number of pages 82 Type of Publication Licentiate thesis ●_{Degree thesis} Thesis C-level Thesis D-level Report

Other (specify below)

ISBN (Licentiate thesis)

ISRN:

LiTH-ISY-EX--06/3913--SE Title of series (Master thesis)

Series number/ISSN ()

URL, Electronic Version http://www.ep.liu.se Publication Title

Highly Linear Mixer for On-Chip RF Test in 130 nm CMOS

Author

Ghulam Mehdi

Abstract

The complexity of wireless communication integrated circuits is increasing day by day due to the trend of multifunction and multistandard support. This has not only increased the production cost of these RFICs but the testing cost is also increased significantly, as much advanced test equipments and instruments are needed to carry out the sophisticated performance tests. To avoid this higher cost and to reduce the test time, the alternative is to perform on-chip test. .In RF transceivers, loopback is an on-chip test technique in which Tx signal, instead of radiating through antenna is fed to the Rx chain through a test attenuator (TA) during the test mode. A highly linear offset mixer is needed to implement this on-chip loopback test for these transceivers. The aim of this thesis work is to design a highly linear upconversion offset mixer for loopback test in CMOS technology. This mixer is designed for Bluetooth and GSM/EDGE standards. Few highly linear mixer architectures were simulated in 0.35um AMS process using Cadence SpectreRF software. When compared with active mixers, passive mixer consumes no dc power and there is significant reduction in silicon area overhead. The thesis presents a highly linear passive mixer with very low conversion loss and noise figure. The mixer is designed in 0.13um AMS CMOS process for higher cut off frequency and improved conversion loss. Pre and Post layout simulation results of the designed mixer are presented.

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vii Abbreviations

BalUn Balanced Unbalanced

1 db CP Input Referred one dB Compression Point dB Decibels

dBm Power level in dB (decibels) with respect to 1 mW DfT Design for Test

DRC Design Check Rules EDGE Enhanced Data Rate

EDGE Enhanced Data Rate for GSM Evolution

ETSI European Telecommunication Standards Institute FDD Frequency Division Duplex

FM Frequency Modulation FSK Frequency Shift Keying

GC Power / Voltage Conversion Gain GMSK Gaussian Minimum Shift Keying

GSM Global System for Mobile communications IF Intermediate Frequency

IIP3 Input Referred 3rd Order Intercept Point IM Intermodulation Products

IMD Inter Modulation Distortion IQ Inphase Quadrature

LFSR Linear Feedback Shift Register LO Local Oscillator

MOS Metal Oxide Semiconductor PA Power Amplifier

PAC Periodic PNoise Periodic Noise PSK Phase Shift Keying PSP Periodic

PSS Periodic Steady State QPAC Quasi Periodic

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viii RF Radio Frequency

RFIC Radio Frequency Integrated Circuit Rx Receiver

SDF Spectral Density Function SSB NF Single Side Band Noise Figure TA Test Attenuator

TDD Time Division Duplex TPG Test Pattern Generator Tx Transmitter

UMTS Universal Mobile Telecommunications System WCDMA Wideband Code Division Multiple Access

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Abstract

The complexity of wireless communication integrated circuits is increasing day by day due to the trend of multifunction and multistandard support. This has not only increased the production cost of these RFICs but the testing cost is also increased significantly, as much advanced test equipments and instruments are needed to carry out the sophisticated performance tests. To avoid this higher cost and to reduce the test time, the alternative is to perform on-chip test. .In RF transceivers, loopback is an on-chip test technique in which Tx signal, instead of radiating through antenna is fed to the Rx chain through a test attenuator (TA) during the test mode. A highly linear offset mixer is needed to implement this on-chip loopback test for these transceivers. The aim of this thesis work is to design a highly linear upconversion offset mixer for loopback test in CMOS technology. This mixer is designed for Bluetooth and GSM/EDGE standards. Few highly linear mixer architectures were simulated in 0.35um AMS process using Cadence SpectreRF software. When compared with active mixers, passive mixer consumes no dc power and there is significant reduction in silicon area overhead. The thesis presents a highly linear passive mixer with very low conversion loss and noise figure. The mixer is designed in 0.13um AMS CMOS process for higher cut off frequency and improved conversion loss. Pre and Post layout simulation results of the designed mixer are presented.

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Preface

This master thesis work describes the design of a highly linear CMOS upconversion mixer aimed for loopback test in RF transceivers. The aim is to design a highly linear mixer with good noise figure and conversion gain for the desired application. The scope of the thesis work is to understand basic loopback BiST concepts followed by a through study on mixers with emphasis on linearity. The work includes studying and implementing different linear mixer architectures and then selecting the most appropriate architecture which meets the required specifications for loopback test configuration. Transistor level and post layout simulations are done to verify the performance of the designed mixer. The simulation tool is Cadence RF Spectre and AMS 0.35 um and AMS 0.13 um processes are used for transistor and layout level simulations.

Chapter-1 starts with an introduction and motivation to this thesis work. Different wireless standards are described in this chapter. It also explains BiST, DfT and Loopback Test in RFICs meant for wireless standards like GSM, EDGE and GPRS etc.

Chapter-2 describes the basic mixer theory and working principle. Different types of mixers are discussed in this section along with their applications. This section also covers the specifications of a typical mixer like conversion gain, noise figure, linearity, port to port isolation, power consumption and area.

Chapter-3 includes the circuits and simulation results of four linear mixer architectures implemented in Cadence at transistor level. The specifications of these architectures are compared to select an appropriate architecture for the aimed mixer.

Chapter-4 In this chapter, a mixer with high linearity is proposed for loopback test. Mixer design from schematic to layout level is discussed. Pre and post layout results are presented in this section.

Chapter-5 concludes this thesis work and indicates some future work directions.

At the end, all the references of the literature reviewed during the entire thesis work are given.

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Acknowledgments

I am thankful to my supervisor Prof. Jerzy Dabrowski for providing me the opportunity to perform this thesis work and for his guidance. I am greatly thankful to Rashad Ramzan, PhD student at Electronic Devices division, ISY dept, for his guidance and encouragement during this thesis work.

I would like to acknowledge and thank to Dr.Jahangir K.Kayani, CESAT, Pakistan for his support, encouragement and technical guidance.

I am also thankful to the people at Electronic Devices department, Linköping University for helping me in technical and administrative issues.

At the end, I am thankful to my parents and my family for their support, patience and encouragement during my MS studies at Linköping.

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List of Figures

Figure 1: Recent trend in wireless standards ... 4

Figure 2: Typical BiST setup... 7

Figure 3: Loopback test setup... 8

Figure 4: Loopback setup for TDD with modulation at BB ... 8

Figure 5: Loopback setup for TDD with direct modulated VCO ... 9

Figure 6: Alternate loopback setup for TDD with direct modulated VCO ... 9

Figure 7: Carrier frequency offset in FDD transceivers ... 10

Figure 8: Loopback test setup in FDD transceivers... 10

Figure 9: Offset mixer before TA, LO connected to PA out ... 12

Figure 10: Offset mixer before TA, LO connected to SG ... 12

Figure 11: LO connected to PA out through TA (not suitable setup) ... 13

Figure 12: RF connected to PA out through TA... 13

Figure 13: Ideal Mixer ... 17

Figure 14: Mixer output frequency spectrum ... 17

Figure 15: Upconversion mixer ... 18

Figure 16: Upconversion mixer in RF Tx... 19

Figure 17: Single transistor unbalanced mixer ... 20

Figure 18: Dual gate unbalanced mixer... 20

Figure 19: Single balanced mixer ... 21

Figure 20: Double balanced Gilbert mixer ... 22

Figure 21: Single balanced passive mixer ... 23

Figure 22: Double balanced passive mixer... 24

Figure 23: Balanced transmission gate switch... 24

Figure 24: MOS noise model for RF ... 28

Figure 25: Input 1dB Compression Point of a mixer... 32

Figure 26: Intermodulation products ... 33

Figure 27: IIP3 of a mixer ... 34

Figure 28: Source degenerated Gilbert mixer... 41

Figure 29: Class AB transconductor mixer ... 44

Figure 30: S21, S22, and S33 & NF of class AB transconductor mixer ... 45

Figure 31: S11 response... 45

Figure 32: Conversion gain and NF with LO sweep ... 46

Figure 33: 1 dB compression point class AB Transconductor mixer ... 46

Figure 34: IIP3 class AB Transconductor mixer ... 47

Figure 35: Replacing (a) single transistor by (b) CMOS pair ... 48

Figure 36: MOS Transconductor (a) with tail current (b) without tail current... 49

Figure 37: CMOS transconductor mixer ... 50

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Figure 39: S21, S22, S33 & NF... 52

Figure 40: 1 dB compression point at 5 dBm LO... 52

Figure 41: IIP3 at 5 dBm LO ... 53

Figure 42: Equivalent circuit of MOS transistor ... 55

Figure 43: Approximate small signal model ... 55

Figure 44: Variation in g_ds₍₁_,₂_,₃₎with change in V_ds... 55

Figure 45: Resistive quad passive mixer ... 56

Figure 46: Conversion loss & NF with LO power sweep ... 56

Figure 47: S11 response of passive mixer ... 57

Figure 48: S parameters & NF response for 100 MHz output bandwidth... 57

Figure 49: 1dB compression point at 5 dBm LO... 58

Figure 50:IIP3 at 5 dBm LO ... 58

Figure 51: 1dB CP and IIP3 with LO sweep ... 59

Figure 52: Schematic diagram 0.13um CMOS passive mixer ... 67

Figure 53: Complete layout of mixer... 68

Figure 54: Pre & post layout result comparison ... 69

Figure 55: Post layout 1 dB CP at 5 dBm LO ... 70

Figure 56: Post layout IIP3 at 5 dBm LO ... 70

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1.1. Introduction

The complexity of wireless communication integrated circuits is increasing day by day due to the trend of multifunction and multistandard support. A hot research is in progress to develop low cost multistandard chip solutions. This has not only increased the production cost of these RFICs but the testing cost is also increased significantly, as much advanced test equipments and instruments are needed to carry out the sophisticated performance tests. To avoid this higher cost and to reduce the test time, the alternative is to perform on-chip performance testing also referred to BiST. In BiST, on-chip testing is carried out to measure the performance parameters of RF front end and to detect possible defects by enabling the test mode in the transceiver. Some extra circuitry has to be put on the chip to implement BiST. This may increase the power consumption and silicon area overhead of the chip but the testing cost is reduced drastically [1, 2].

The emergence of various wireless communication standards has also increased the complexity to incorporate on-chip BiST. Today’s complex RF transceiver architectures provide better sensitivity, selectivity, dynamic range and adjacent channel blocking. In RFICs, one of the most common implementation of BiST is “Loopback Test” in which Tx signal, instead of radiating through antenna is fed to the Rx chain through a test attenuator (TA) during the test mode. Different configurations of loopback test are described in section 1.2. An offset mixer is required to implement this on-chip loopback test.

The objective of this thesis work is to explore and design a highly linear upconversion mixer in CMOS technology. This mixer is designed primarily for GSM/EDGE standards but can be used for loopback test in other transceivers as well.

1.2. Wireless Standards

The field of wireless communication and networks has attained tremendous growth in recent years. The idea of having multi functions like phone, video, digital camera, web browser and email etc in a single terminal has led to different wireless standards. Wireless communication systems, such as cellular, cordless and satellite phones as well as wireless local area networks (WLANs)

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have become an essential tool to many people in every-day life. As the technology is advancing, these standards are becoming more and more stringent emphasising on enhanced data rates, circuit miniaturization, and multi function and multi standard support [3]. These standards are meant for both short and long range wireless communication. Zigbee, UWB, DECT and Bluetooth are standards for short-range communication. Fig.1 shows the recent trend in wireless standards.

Figure 1: Recent trend in wireless standards

Following is a brief description of these wireless standards.

1.2.1. GSM

GSM standard for mobile telephony was developed by ETSI and was operating in 900 MHz band. EDGE-GSM is enhanced data rate GSM standard.

Mobile Frequency Range (MHz)

Rx: 1805-1880, Tx: 1710-1785 Rx: 1930-1990, Tx: 1850-1910 Multiple Access Method TDMA/FDM

Duplex Method FDD

Number of Channels 124 Users Per Channel 8

Channel Spacing 200 KHz

Modulation GMSK,8-PSK (EDGE only)

Channel Bit Rate 270 833 kb/s

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In EDGE, the transmission rate is three times for the same bandwidth as used in original GMSK modulation (standard GSM). EDGE is based on a modified 8 PSK scheme. Polar modulation is implied at the Tx. The input signal to the PA is phase modulated with constant amplitude whereas amplitude modulation is added at the output by varying the gain of PA [4]. GSM standards are summarized in Table.1.

1.2.2. UMTS

Universal Mobile Telecommunications System is European 3G version of global wireless systems for voice and information services. This provides various data rates using WCDMA. UTMS is a FDD based system, so a highly linear receiver is required to reject the Tx leakage into the Rx section [3]. UTMS specifications are given in Table.2.

Mobile Frequency Range (MHz) Rx: 2110-2170, Tx: 1920-1980 Multiple Access Method WCDMA Duplex Method FDD Users Per Channel 8 Channel Spacing 5 MHz

Modulation QPSK/OQPSK Channel Bit Rate 384.833 kb/s outdoor

2 Mb/s indoor

Table 2: UTMS specifications

1.2.3. Bluetooth

Bluetooth is a wireless standard for short-range communication and commonly used for connectivity between electronic devices. This has enabled to replace the cables used for interconnections. Bluetooth can also be used to provide ad hoc networks or data/voice access points. Bluetooth operates in ISM band. Since Bluetooth is primarily intended for portable battery driven devices, minimum power consumption is essential. The constant envelope modulation scheme (BFSK) allows to use power efficient switching PA in Bluetooth TX [3]. Specifications of Bluetooth are given in Table.3.

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6 Mobile Frequency

Range (MHz)

2402-2480

(North America & Europe)

Multiple Access Method

Frequency hopping Duplex Method TDD

Number of Channels 79

Users Per Channel 7 active, 200 inactive Channel Spacing 1MHz

Modulation BFSK

(0.5 Gaussian Filter) Channel Bit Rate 721 kb/s raw data

56 kb/s return

Table 3: Bluetooth specifications

1.2.4. Zigbee

Zigbee is a wireless networking standard that is aimed at remote control and sensor applications which is suitable for operation in harsh radio environments and in isolated locations. It builds on IEEE standard 802.15.4.Zigbee a very attractive standard for wireless networking.

Frequency Range (MHz) 2402-2480,1000 mW/MHz (N. America) 2412-2472, 100 mW/MHz (Europe) Multiple Access Method TDMA Duplex Method FDD Users Per Channel 255 Channel Spacing 4 MHz Modulation GFSK

(0.5 Gaussian Filter) Channel Bit Rate 250/28 kb/s

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1.3. BiST Technique

Built-in self-test is a technique to perform on-chip performance test or to detect possible defects on-chip. BiST implementation usually requires extra hardware circuitry to be introduced on the chip. BiST can also be defined as a DFT technique in which testing is accomplished through built-in hardware circuitry. BiST is a cheap test solution since no expensive external ATE is required [5, 6]. As shown in Fig.2, TPG generates the test bits. This TPG can be implemented as a LFSR. Specifically, in digital RF transceiver the carrier signal is modulated with this BB signal. The BB processor then evaluates the received demodulated signal from Rx chain of DUT.

Test Pattern Generator

Device Under Test

Test Response Evaluation BiST

Controller

Figure 2: Typical BiST setup

1.4. Loopback Test

Loopback is straightforward test architecture for transceivers. In loopback test, the Tx test signal is fed to the Rx usually through a test attenuator (TA) to check the functionality of both the Tx and the Rx. The available baseband (BB) processor acts as both test pattern generator and spectrum analyzer respectively [6].

Fig.3 shows a typical loopback test setup. The primary advantage of on-chip loopback other then reduced testing cost and testing time, is that no sensitive block in the transceiver is accessed externally for test purpose and hence not affected. As described in Section.1.2, different wireless standards with different

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Tx and Rx architectures are in use so a generic loopback test setup not always is fully compatible with them [7].

Figure 3: Loopback test setup

Beneath, some possible loopback test configurations are described and requirement of a highly linear offset mixer is motivated, which is the core of this thesis work.

1.4.1. TDD with Modulation at Baseband

In RF transceivers where TTD duplexing technique is used and the Tx signal is modulated at the BB (LO is not directly modulated), a simple loopback configuration is applied as shown in Fig.4. The signal is fed to the RX chain through a TA. Usually this TA is programmable so that both the sensitivity and linearity of the RX can be tested [8].

Figure 4: Loopback setup for TDD with modulation at BB

Base Band Processor ADC LPF DAC LPF LNA LO Amp T r a n s m i t t e r R e c e i v e r TA Test xtest

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1.4.2. TDD with Directly Modulated VCO

Baseband signal directly modulates the VCO. There may be two loopback test setup configurations.

(a) In TDD, LO is shared by both Tx and Rx. In this scenario, LO is directly modulated by the BB signal. Both the LO of Rx and test signal are the same. This will generate DC at the Rx output. An offset mixer must be introduced in the test path as shown in the Fig.5 to strip off the modulation [7, 9]. Conversely, if LO remains unmodulated, modulation is achieved in the offset mixer so the test is feasible as well. One of the inputs of the offset mixer is the RF signal and the other input is the BB test signal. The transmission line delay in the RF signal path may degrade the loopback test performance.

Figure 5: Loopback setup for TDD with direct modulated VCO

Figure 6: Alternate loopback setup for TDD with direct modulated VCO R e c e i v e r Base Band Processor xtest ADC LPF DAC LPF LNA LO Amp T r a n s m i t t e r R e c e i v e r (zero-IF) TA Test _Control xtest Base Band Processor ADC LPF DAC LPF LNA LO Amp T r a n s m i t t e r TA Test Xtest xtest fRx fTx

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(b) The alternate approach may be to place the offset mixer between the LO and the receiver mixer, instead of placing it in the main loopback path. This is depicted in Fig.6. The directly modulated test signal is applied to the input of LNA through TA. The same signal is mixed with the BB signal using an offset mixer, to remove the modulation. Since offset mixer drives the Rx downconversion mixer, this mixer should be highly linear with minimum noise figure and large output swing.

1.4.3. FDD with/without Modulated VCO

In FDD, there is separate LO for Tx and Rx and transmitting and receiving frequencies are also different, therefore loopback test without offset mixer can not be performed in such transceivers [9].

For example, in GSM, the Tx band is from 1710 to1785 MHz and Rx band is from 1805 to1850 MHz, as shown in Fig.7. The ∆f may vary in range of few tens of MHz.

Figure 7: Carrier frequency offset in FDD transceivers

Figure 8: Loopback test setup in FDD transceivers Base Band Processor ADC LPF DAC LPF LNA LO Amp T r a n s m i t t e r R e c e i v e r TA Test ∆∆∆∆f xtest fRx fTx ∆f Tx band _{Rx band} fTx fRx

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The conversion gain of offset mixer is relaxed in this configuration as it can be compensated by the attenuation of programmable TA. The test setup for FDD transceivers is depicted in Fig.8.

1.5. Offset Mixer Placement in Loopback

A mixer can either be passive or active. Placement of an offset mixer is critical and determines the suitability of a mixer type and its specifications for loopback test. There are following two options for the placement of offset mixer in the main test loop.

1.5.1. Placement before Test Attenuator (TA)

Offset mixer can be placed between PA of Tx and TA. This mixer can be either passive, or active with some conversion gain. For passive mixers, conversion loss is approximately equal to NF. Since TA is also passive, placement of passive offset mixer before or after TA has not effect on total noise figure (NFtotal).

Consider an example where passive offset mixer with NF of 5 dB and conversion loss of –5 dB is the first stage and TA with attenuation of 30 dB is the second stage as depicted in Fig.9. Then NFtotal can be calculated using

following Friis formula:

1 2 1 1 G NF NF NF_total = + − NFtotal = 35 dB

Total noise figure remains the same even if the passive mixer follows TA.

On the contrary when this offset mixer is active (with some conversion gain), placement of mixer affects the overall noise figure. When TA follows the active offset mixer, the mixer gain helps to reduce the total noise figure.

Consider an active mixer with NF of 10 dB and conversion gain of 5 dB. TA follows the mixer with an attenuation of 30 dB. Then total noise figure is

NFtotal = 25.15 dB

By swapping their locations, the total noise figure of 40 dB is achieved. Hence, we infer that an active offset mixer with typical NF and GC values should be

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Since the mixer is a three-port device, there are two more options regarding the connectivity. Either LO or RF IN port can be connected to output of PA. Both the options for active and passive mixer are considered.

Consider the case when LO is connected to PA output as depicted in Fig.9. RF IN port is connected to on-chip test generator. The requirement for the signal swing of this generator is relaxed in this case but a possible overdrive must be avoided as well. Usually, PA output signal is large enough to drive the LO port i.e. switching stage, both in case of active and passive mixer. However, a too large LO swing used in active mixer leads to increased LO feedthrough and spikes in the output signal.

TA LNA PA Xtest (RF IN) LO Port

Figure 9: Offset mixer before TA, LO connected to PA out

Alternatively, PA output can be connected to RF IN port and then the on-chip test generator drives LO port as shown in Fig.10. A large enough on-chip swing is needed to drive the mixer LO port especially when a passive mixer is used. Since there is no attenuator between PA and the offset mixer, high power from PA output (typically 10 dBm) can saturate the transconductance stage of an active mixer introducing nonlinear distortions.

TA LNA PA Xtest (LO Port) RF IN

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A passive offset mixer is more appropriate in this case provided that LO power is typically 5 dB greater than the RF IN power. This ensures that MOS switch operates in linear region and the 1dB compression point is not affected.

1.5.2. Placement after Test Attenuator (TA)

Placement of the passive mixer after or before TA doesn’t affect NFtotal.

However, in case of an active offset mixer the overall noise figure may degrade if it is directly connected to the LNA input.

TA LNA PA Xtest (RF IN) LO Port

Figure 11: LO connected to PA out through TA (not suitable setup)

Consider the setup when the LO port of the mixer is driven by PA through TA and RF IN port is connected to on-chip test generator as depicted in Fig.11. Since a large amplitude is needed for switching the LO port, this configuration is neither suitable for active nor for passive mixers. A typical attenuation of TA would reduce the LO amplitude too much to make the mixer switch. The transceiver can’t be tested in this setup.

TA LNA PA RF IN Xtest (LO)

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The last configuration is the one in which RF port is connected to PA output through TA and LO port is connected to the test generator as depicted in Fig.12. An active mixer driven by a relatively low LO power is suitable in this case. A passive mixer can be used as well.

1.6. Required Mixer Specifications

The specifications of an offset mixer depend on the wireless standard, which it is meant for, RF transceiver type (FDD or TDD) and loopback test configuration. The aim of this work is to design an offset mixer to be used in the main loopback test path.

Since this offset mixer is a part of an extra test circuitry to implement on-chip loopback, the power and area constraints are very stringent. The portable devices have certain amount of stored energy. Therefore, a BiST circuitry with lowest power consumption is preferred. Area is another constraint as the cost rises with increase in area. Conversion gain of the required mixer is not that much critical as it can be compensated by the programmable TA. 10 dB, typical mixer NF is targeted.

However, the main focus is on linearity of the mixer. A mixer with poor linearity may obscure the test response and result in false rejects. The targeted linearity specifications are given in Table.5.

RF input frequency 60 MHz LOfrequency 2.4 GHz LOPower 5 dBm C G 0 dB NF < 10 dB 1 dB Compression Point 0 dBm 3rd Order Intercept Point 10 dBm Power consumption & area Minimum

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2.1. Introduction

An ideal mixer is a multiplier circuit and usually drawn with a multiplier symbol as shown in Fig.13. An ideal mixer translates the modulation around one carrier frequency to another carrier frequency. A linear time invariant (LTI) circuit cannot perform frequency translation. Mixers can be realized with either time-varying or non-linear circuits.

A mixer is a three-port device consisting of LO (local oscillator), RF IN (radio frequency input) and IF OUT (intermediate frequency output) ports. LO port is driven by a local oscillator, which is a fixed amplitude large signal.

Figure 13: Ideal Mixer

The mixer produces sum and difference frequencies along with other spurious tones due to the even and odd harmonics as depicted in the Fig.14.

Figure 14: Mixer output frequency spectrum

2.2. Ideal Multiplier

The multiplier circuit multiplies the two input signals A and B, and generates product terms. Multiplication in time domain is convolution in frequency domain. The following mathematical expression shows the generation of sum and difference frequency products.

t Cos A A= ₁

ω

₁ (2.1) t Cos A B= 2

ω

2 (2.2)

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18 Multiplying the two signals a and b

) )(

(

.B A₁Cos ₁t A₂Cos ₂t

A =

ω

(2.3)

Using the trigonometric identity, we have

t Cos A A t Cos A A B A ( ) 2 ) ( 2 . 1 2 2 1 2 1 2 1 ω −ω + ω +ω = (2.4)

2.3. Mixer Types

Classification of mixers is quite diverse. Mixers can be classified based on functionality, topology, power consumption and transconductance stage.

2.3.1. Up & Down Conversion Mixers

The mixer produces two useful frequency components at the output i.e. the sum and difference frequencies (

ω

RF ±

ω

LO)and other unwanted spurious signals. The main difference between down and up conversion mixer is the different output signal frequency. In downconversion mixer, the output signal frequency is low usually few MHz, whereas in upconversion mixers, the output signal frequency is high usually in GHz.

(a) Upconversion Mixer

In upconversion mixer, one of the input other than LO is usually called IF input as it is much lower than LO frequency. The output of the mixer is sum of IF and LO frequencies i.e.

ω

RF =(

ω

IF +

ω

LO)and called as RF out. Fig.15 shows symbol of an upconversion mixer.

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Upconversion mixers are used at the Tx side, either as modulator or frequency upconverter or both. This depends on the Tx architecture. Fig.16 shows a two stage Tx. The first stage works as upconverter generates (

ω

₁+

ω

₂). The mixers in the second stage act as IQ modulator [10].

Figure 16: Upconversion mixer in RF Tx

(b) Downconversion Mixer

Downconversion mixer in the Rx chain translates incoming high frequency into a lower frequency to be processed by the IF stage of the Rx. The input signal is called RF, and IF is the output frequency which is frequency difference of RF and LO frequencies i.e.

ω

_IF =(

ω

_RF +

ω

_LO).

2.3.2. Unbalanced & Balanced Mixers

(a) Unbalanced Mixer

Unbalanced mixers are the simplest kind of mixer with lowest noise figure. A single transistor unbalanced mixer is shown in Fig.17. This kind of mixer is also called as Square Law Mixer. Mixing is performed by using nonlinear square law characteristic of MOS transistor.

Conversion gain of such a mixer is independent of bias current and can be expressed by Eqn.2.5 [11, 12]. LO ox c V L W C G . 2 µ = (2.5)

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Figure 17: Single transistor unbalanced mixer

An alternative configuration of unbalanced mixer is depicted in Fig.18. Mixing is performed by modulating the transconductance of the driver stage with the large LO signal. The LO signal modulates the transconductance of the driver stage by varying the drain-source voltage vds of transistor M1. Drain of M1 is

biased just at the edge between triode and saturation region to maximize the transconductance variation due to large LO signal [12]

Vrf Vlo

M2 M1

Figure 18: Dual gate unbalanced mixer

The unbalanced mixers have very poor port to port isolation due to their structure. Port-to-Port isolation determines what fraction of the IF signal that appears at the RF. Feed through between different ports are undesirable in mixer design and can degrade the Tx or Rx performance.

In unbalanced designs, noise from the driver stage at the IF can mix with the dc component of the LO signal, and thus increase the noise power at the IF output port. This noise can be reduced by capacitive degeneration at the driver stage where M1 is the driver stage [12].

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This type of mixer consists of a single transconductance stage and a differential switching pair as shown in Fig.19. The incoming RF voltage is converted into current by the transconductance stage with some gain and then multiplication is performed in the current domain. The tail current is multiplied by the large LO signal. Thus the output is sum and difference frequency components. Since the output is differential and taken from both branches, RF feedthrough is cancelled out [11, 13].

The circuit has a lower noise figure than the double balanced mixer due to its fewer noise contributor devices. Source is degenerated for linearity improvement. The common source transconductance stage can be replaced with a common gate transconductance stage for better linearity but this makes the design noisier as the noise contribution from the switching pair is not attenuated [12]. VDD M3 M2 M1 Vss L LO-LO+ RF IF

Figure 19: Single balanced mixer

(c) Double Balanced Mixer

The most commonly used type of mixer is a double balanced mixer also known as Gilbert mixer and will be discussed in detail in chapter 3. This kind of mixer is suitable for both upconversion and downconversion applications. The mixer consists of a differential transconductance stage and a differential switching stage. Due to the fully differential structure, both the LO-IF and RF-IF feedthrough is cancelled and isolation is improved significantly. Off course, feedthrough exists due to the mismatches in the differential structure. However, RF-LO and LO-RF feedthrough exists in double balanced mixer. The

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22

transconductance stage provides gain to compensate the attenuation due to switching stage and also to reduce the noise contribution from the switching transistors [12, 13].

A doubled balanced Gilbert mixer is shown in Fig.20. The transconductance or driver stage consists of transistors M1 and M2 whereas M3, M4, M5 and M6 form

the differential switching quad. For perfect switching, the size of transistors M3

to M6 is much smaller than M1 and M2.

Resistive load is suitable for broadband operation but reduces the voltage headroom. For large output swing and save the voltage headroom, the resistive load can be replaced with a LC tank circuit tuned at the mixer output frequency. On the other side, this will limit the broadband operation of the mixer. The tuned LC load is suitable for upconversion mixers as the output frequency is high and an on-chip inductor can be realized at this frequency. For downconversion mixers with low IF, inductor of large value can not be realized on-chip.

IF+ IF-LO+ RF-RF+ LO+ LO-C L C L VDD M5 M4 M3 M2 M1 M6 Iss Vss

Figure 20: Double balanced Gilbert mixer

To improve the linearity of a double balanced mixer, there are different techniques and most common is the source degeneration. Degeneration can be implemented by using resistor, capacitor or inductor. The reactive source degeneration has lower NF than that with resistive degeneration [11, 12].

2.3.3. Passive & Active Mixers

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23 (a) Passive Mixers

Passive mixers, also known as switching mixers, are simple in construction. These mixers don’t consume any dc power. These mixers have conversion loss instead of conversion gain due to the absence of transconductance stage. The mixer performs a multiplication between the RF signal and the LO signal ideally represented by a square wave switching between +1 and -1 as expressed in Eqn.2.6. ) ( 2 1 ) ( 2 1 ) ( ).

( t COS t COS t t COS t t

COS ωRF ωLO = ωRF +ωLO + ωRF −ωLO (2.6)

The passive mixers require good switches with minimum on-resistance for reduced conversion loss. Similarly the switch must have a maximum high resistance when off, to provide good isolation.One of the disadvantage in such mixers is the need of large LO drive signal to turn the MOS switches on/off. MOS transistor are very good switches for such high frequency applications. When the MOS transistor is on, it operates in triode region and when off it is in cut off region. For precise switching, ideally, the transistor should be biased such that the gate-source voltage (VGS) is equal to the threshold voltage (VT) of

the transistor i.e. (VGS=VT). Lower the on resistance (Ron) of the switch, lesser

will be the conversion loss. The drain-source of passive mixers transistors are slightly bias with positive VDS to attain optimum conversion loss and optimized

IMD performance mixers are [11, 14].

Figure 21: Single balanced passive mixer

Fig.21 shows the working of a single balanced passive mixer. Both the transistors in the mixer switch on alternatively during the positive and negative LO cycles.

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24

Double balanced topology is preferred over the single balanced as it provides higher port-to-port isolation. Fig.22 shows a passive double balanced mixer. In mixers, the major source of non-linearity is the transconductance stage. Since there is no transconductance stage and MOS transistor is fairly linear in triode region when switched on, MOS passive mixers exhibit excellent linearity.

C C C C C C IF+ IF-LO+ RF-RF+ LO+ LO-VB VA

Figure 22: Double balanced passive mixer

For improved port-port isolation and rejection of even order nonlinearity, balanced transmission gate may be used instead of a single NMOS transistor [15, 16]. Transmission gate also called as balanced switch consists of a NMOS and PMOS transistor in parallel. A balanced transmission gate is depicted in Fig.23.

Figure 23: Balanced transmission gate switch

(b) Active Mixers

Active mixers consist of two stages, switching stage and the transconductance stage, hence consume static dc power. Active mixers can be either single ended or double ended. The most commonly used active mixer is the standard Gilbert

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25

cell mixer discussed in section 2.3.2(b). Since the circuit is active, the transconductance stage provides voltage gain, however, NF is increased. The non linear characteristics of transconductance stage degrades the over all linearity of active mixers. Different active mixer architectures for improved linearity have been proposed, and will be discussed in chapter 3.

2.4. Mixer Performance Parameters

The most important performance measure parameter of RF Rx is sensitivity and selectivity. Sensitivity depends on system noise figure and type of demodulation scheme. Selectivity includes adjacent channel selectivity, image rejection and out of band blocker rejection, and depends on the third-order intermodulation performance of the Rx front end. The total noise figure NFtotal and total

third-order intercept point IIP3total of a Rx can be calculated by using Eqn.2.7 and

Eqn.2.8. ... 1 1 2 1 3 1 2 1 + − + − + = G G F G F F NF_total (2.7) 1 3 2 2 2 1 2 2 1 1 .... 3 3 3 1 3 −       + + + = IIP G G IIP G IIP IIP total (2.8)

It is obvious from the above two formulas that NF of first stage and IIP3 of second stage is critical in determining the overall noise figure and third-order intermodulation performance. In heterodyne Rxs, first sage is LNA followed by downconversion mixer as second stage.

Following is a description of different performance parameters of a mixer.

2.4.1. Conversion Gain

Conversion gain can be defined as either power conversion gain or voltage conversion gain and represented by GC. Usually it is power conversion gain

unless otherwise specified. When the mixer’s input impedance and output impedance are both equal to the source impedance, the power conversion gain and voltage conversion gain, in dB, are the same.

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26 ) ( ) ( rms RF rms IF C V V G = (2.9)

The power conversion gain is the ratio of the output power at the load to the

available RF input power.

) ( ) ( RF in IF out C P P G = (2.10)

(a) Active Mixer GC

In active mixers like Gilbert mixer, transconductance stage provides the conversion gain. All transistors operate in saturation region. The conversion gain expression for a Gilbert mixer with source degeneration resistor RS and with a

load impedance RL is given by Eqn.2.11.

      = m L C dB G R G π 2 log 20 ) ( (2.11) where m S m g R G 1 1 + = (2.12)

and gm is the transconductance of V-I stage saturated transistor.

(

GS T

)

ox n m V V L W C g =µ − (2.13) T GS D m V V I g − = 2 (2.14)

Therefore, increasing the width (W) of the transistor while keeping length (L) at minimum increases the gain. Higher overdrive voltage also increases the gain.

(b) Passive Mixer GC

To derive the expression for conversion gain of an ideal mixer, consider the following input signals.

t a t v_LO( )= cosω_LO (2.15) t b t v_RF( )= cos

ω

_RF (2.16)

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27

The product of fundamental frequency of LO and RF signal is then

t b t a t v_IF ω_LO ω_RF π cos . cos 4 = (2.17)

[

t t

]

b a. cos( _LO _RF) cos( _LO _RF) 4 . 2 1 _ω _ω _ω _ω π + + − = t ab t vIF ωIF π cos 2 = (2.18)

Therefore, the ideal conversion gain of a passive mixer is

π

2 =

C

G , which is equal to 3.9 dB. With approximations, the above equation can be modified to include the on-resistance of the mixer switches, which appears in series with the source resistance.             + = on S S C R R R dB G 2 2 log 20 ) (

π

(2.19)

RS is the source resistance; Ron is the average on-resistance of a single switch

transistor and can be determined by

LO ox eff ds on WV C L g R

µ

= = 1 (2.20)

Where VLO is the LO drive voltage. Minimizing Ron by device sizing improves

the conversion loss but generates matching issues due to addition of larger parasitic capacitance. The other options to reduce Ron is to either increase the

LO drive or to use a transistor with minimum gate length [17]. 2.4.2. Noise Figure

Noise figure is defined as the signal to noise ratio at the input to signal to noise ratio at the output.

output input output output input input SNR SNR N S N S NF = = (2.21)

Mixer noise figure can be specified as either single sideband (SSB) or double sideband (DSB).SSB noise figure is used for the mixers in which the input signal is contained in one sideband and the other sideband is removed by an

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28

image rejection filter. DSB noise figure is applied for the mixers where the input signal is contained by both the sidebands. DSB NF is applicable to direct conversion mixers [12].

dB NF

NF_SSB ≅ _DSB +3

In this thesis work NF is SSB, unless otherwise specified. (a) MOS Transistor Noise at RF

The noise consideration at RF is different then at low frequencies. The basic noise behaviour is modelled by two correlated noise sources. The dominant noise sources for active MOSFET transistors are the flicker and thermal noise. The flick noise can be modelled as a voltage source in series with the gate as shown in Fig.24.

The SDF of voltage for this source has the following value

f WLC K f v ox f ng = ∆ 2 (2.22)

Where W and L are width and length of transistor respectively, Cox is the gate

capacitance per unit, f is the frequency and Kf is a constant and depends on the

process. It is important to note that for P channel device; this constant has much smaller value than the N channel device.

DC G S D g_mVgs r_g Cgs Vng 2 i_nd2

Figure 24: MOS noise model for RF

For thermal noise, the MOSFET noise model consists of following two noise sources. The drain current noise is

f g KT

i2nd =4

γ

_do∆ (2.23)

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29 f g KT i2ng =4 δ _g∆ (2.24) where do gs g g C g 5 2 2

ω

= (2.25)

The gate noise is correlated with the drain noise with the following correlation factor 2 2 nd ng nd ng

i

c

=

(2.26)

(b) Noise Analysis in CMOS Active Mixers

The CMOS mixers suffer from two types of noises, the flicker noise and the white noise. Flicker noise is more critical in zero and low IF Rx architectures. Active mixer consists of an input transconductance stage, switching stage and output load. All transistors in the circuit contribute noise. Detailed high frequency noise analysis of CMOS active mixers is presented in [18, 19] in which both flicker and white noise issues are discussed. A brief description of both types of noise is given below.

• Flicker (1/f) Noise:

To minimize the load noise, PMOS loads can be used instead of NMOS. The alternative is to use polysilicon resistors as load resistor is free from 1/f noise. For zero or low IF architectures, the transconductance stage transistors only contribute white noise after frequency translation. The flicker noise in these transistors is unconverted to ωLO and to its odd harmonics.

Switching stage in active mixers significantly contribute flicker noise. This noise can be minimized with sharp LO transitions. It has been observed that noise reduces with lower LO frequency or with higher device fT [19].

• White Noise:

In single balanced mixers, switches contribute white noise when both the switches are ON. The noise added by a switching transistor is given by

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30 A I KT i_n_o π γ 4 2 , = (2.27)

Where γ =Channel noise factor A= LO signal amplitude I= dc bias current

The white noise generated in the transconductance stage is indistinguishable from the RF input noise. So mixer commutation is assumed including conversion gain of 2/Π, yields following expression

2 2 , 2 4       × = m L m o n g R g KT n v

π

γ

(2.28)

The total white noise at the output of the mixer is 2 2 2 , 2 4 8 8       × + + = m L m L L o n g R g KT n A I R KT KTR v

π

γ

π

γ

(2.29)

Simplifying the above equation yields       + + = 2 1 8 2 , L m L L o n R g A I R KTR v γ π γ (2.30)

The total output noise for doubled balanced mixer is       + + = 2 1 8 2 , L m L L o n R g A I R KTR v γ π γ (2.31)

It is obvious from Eqn.2.31 that the output noise is proportional to transconductance of the transistor, load resistance and dc bias current.

(c) Noise Analysis in CMOS Passive Mixers For an ideal passive mixer

c

G

NF =

GC is the conversion loss of the mixer. This equation is modified to include the

on resistance of the mixer switches, which appears in series with the source resistance.       + = s on c dB R R G NF 1 2 (2.32)

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31

Ron is the average on-resistance of a single switch and the above equation show

that the noise added by the switching transistor can be minimized by reducing the Ron.

2.4.3. Port-Port Isolation

When port impedance is not matched to that of source impedance, some of the power delivered to the port is reflected back to the source. Impedance matching at RF and IF ports is necessary to avoid signal reflections.

Port-port isolation of a mixer depends on the architecture and topology. Higher the isolation between the mixer ports, the better it is. The isolation between LO and RF ports of the mixer is important as this feedthrough results in LO leaking through antenna [12].

2.4.4. Linearity

A weakly nonlinear system can be approximated by the following 3rd order polynomial.

( )

3 3

( )

.... 2 2 1 + + + = xt x t x t t y α α α (2.33)

Thus the output of such a nonlinear circuit for a sinusoidal input signal

( )

t A t

x = cos

ω

is

( )

t A t A t A t

y α cosω α cos ω α3 3cosω

2 2 2 1 + + = (2.34)

( )

t A A A t A t A t y

α

ω

α

ω

α

cos3

ω

4 2 cos 2 cos 4 3 2 3 3 2 2 3 3 1 2 2 + +       + + = (2.35)

In Eqn.2.35, cosωtis the fundamental frequency and rest is higher order harmonics. A differential structure suppresses the even order harmonics. Odd order harmonics make the system nonlinear [20].

An important specification of a mixer is its linearity. Mixers perform frequency translation and realized by either using non-linear or time varying circuit. Thus mixers are inherently non-linear. It is desirable for a mixer to act very linearly with respect to all nonlinearities except the one giving the desired frequency conversion. Two major sources of distortion in the mixer are the device nonlinearities and the nonlinearities coming from the switching devices.

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32 (a) 1dB Compression Point

1 dB compression point (P1dB) is a way to measure the extent of nonlinearities in

a mixer. A strong input signal saturates a mixer and reduces its power gain. Input P1dB is the input power level that causes the mixer to decrease from its

linear magnitude response by 1 dB, and is equal to

3 1 1 145 . 0 log 10

α

= dB P (2.36)

1dB

20log Ain

20log Aout

A 1-dB

Figure 25: Input 1dB Compression Point of a mixer

Fig.25 shows the output response of a mixer as a function of input signal power. The straight line shows the linear magnitude response of a mixer. Due to odd order nonlinearities and limiting (current limiting and/or voltage headroom limiting), the conversion gain of the mixer is reduced at high input power level as shown by the solid line. The point where the large-signal gain is 1 dB below the small-signal gain is P1dB.

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33

If the input signal is larger than the P1dB, this causes amplitude modulation (AM)

to phase modulation (PM) conversion. No information is lost if the desired signal is frequency modulated but for phase modulated signal, BER increases [12].

(b) 3rd Order Intercept Point (IIP3)

The other parameter to measure the extent of nonlinearity in mixers is the 3rd order intercept point known as IP3. IP3 is defined as,

“It is the extrapolated point where the fundamental and 3rd order intermodulation products (IM3) intersect each other. At this point IM3=0 dBc”

At this point, the input power level is called input referred IP3 (IIP3) and output power level is called output referred IP3 (OIP3) and is given by Eqn.2.37.

3 1 3 3 4

α

= IIP A (2.37)

Figure 26: Intermodulation products

When two signals close in frequency, are applied to a nonlinear circuit, intermodulation products are generated other than the harmonics of input frequencies. For input frequencies

ω

1and

ω

2, the intermodulation products are

ω

₁±

ω

₂, 2

ω

₁ ±

ω

₂and2

ω

₂ ±

ω

₁. If the frequency difference between

ω

₁and

2

ω

is small, then the components 2

ω

1±

ω

2and 2

ω

2 ±

ω

1 are the third order intermodulation products. These IM products will appear in the close vicinity of

1

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34

Thus, it is apparent that a stronger interferer with a frequency, which is close to the actual signal frequency, will corrupt the signal due to 3rd order intermodulation products because the fundamental increases in proportion to A, whereas IM3 increases in proportion to A3[20].

IP3 is measured by a two tone test. This two tone test is more relevant to evaluate mixer performance as in real life; both the wanted signal and interferer may exist. The magnitude of intermodulation products grows at three times the rate at which the fundamental component increases. The intersection point of these two lines is defined as the third order intercept point. The horizontal coordinate of this intersection point is called input IP3 (IIP3) and the vertical

coordinate is called the output IP3 (OIP3). Fig.27 shows IP3 of a mixer.

Pin (dBm)

P

o

u

t(

d

B

m

)

OIP3 IIP3 First-order output 3rd-order Intercept output 1dB Compression Point IP 1dB

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35

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36

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37

3.1. Introduction

To design a highly linear mixer, it is essential to understand the sources of nonlinearities in mixers. This is discussed in section 3.1. Different reported mixer architectures with high linearity were investigated and simulated with Cadence software using AMS 0.35um CMOS process. Only a few suitable architectures along with the simulation results are presented in this chapter, as describing the rest is beyond the scope of this work. The primary objective is to achieve highest possible linearity with good NF and GC. The mixer is aimed for

loopback test and is an extra component on the chip for BiST. Mixer design is a trade off among its specifications, power consumption and silicon area. The mixers presented in this chapter are designed and optimized for low dc power consumption and with controlled silicon area.

3. 2. Nonlinearities in CMOS Mixers

The two dominant nonlinear sources in CMOS is the transconductance and output conductance. The Taylor series is used due to its simplicity for weakly nonlinear circuits. The drain current of a MOS in the Taylor expansion can be expressed as follows:

(

)

3 3 2 2 2 2 3 3 2 2 2 2 ) , ( , ds d ds gs md ds gs md gs m ds d ds gs md gs m ds d gs m DS GS DS DS GS ds v g v v g v v g v g v g v v g v g v g v g V V I v v i + + + + + + + + + = (3.1)

In the above expression, gm3 is referred to as the third-order transconductance

and gd3 its third-order output conductance. Assuming that the drain current is

shorted at the signal frequency then all the output conductance terms and cross modulation terms are vanished and only the transconductance terms are left. IIP3 is given by 3 3 4 3 m m g g IP = (3.2)

However, the above model is not accurate, as it does not include output transconductance nonlinearity. Another model, which includes the nonlinearity added by output conductance, is presented in [21].

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38

According to this model, the third-order intermodulation current caused by the transconductance and output conductance nonlinearities is given by

load d load m trans IM G g G A g i + = 3 3 , 3 4 3 (3.3) load d load ds d cond IM G g G v g i + = 3 3 , 3 4 3 (3.4)

where A is the fundamental amplitude at the gate and vds is the fundamental

voltage at the drain and can be expressed by

d load m ds g G A g v + = (3.5)

At higher frequencies, the transconductance nonlinearity becomes a dominant source. The internal capacitances don’t add nonlinearity; however gain and output swing is reduced at higher frequencies. At lower frequencies, the output transconductance is the major source of nonlinearity. With technology scaling, the transconductance becomes more linear but the output conductance nonlinearity is increased [21].

The nonlinearities in active and passive CMOS mixers are as following.

3.2.1. Nonlinearities in CMOS Active Mixers

In active mixers, both the transconductance stage and switching stage add nonlinearities. The transconductance has poor linearity due to the nonlinear characteristics of the MOS transistors. The transistors operate in saturation region with quadratic V-I characteristics. The following model is not accurate for short channel devices. If the channel length modulation is neglected then the drain current is given by

(

)

2

2 GS T

D V V

I = β − (3.6)

Consider the input signal vgs is applied at the input. The total instantaneous gate

to source voltage will be

gs GS

GS V v

v = + (3.7)

and the total instantaneous drain current is 2 ' ) ( 2 1 T gs GS n D V v V L W k i = + − (3.8)

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39 2 ' ) ( 2 1 T GS n D V V L W k i = − + _n V_GS V_T v_gs L W k' ( − ) + ' 2 2 1 gs n v L W k (3.9)

The first term on the right hand side is the dc bias current. The second term is the current, which is proportional to the input signal vgs. The third term is the

unwanted nonlinear term and generates distortion. This nonlinear term must be kept small to reduce distortion, so that

2 ' 2 1 gs n v L W k << _n V_GS V_T v_gs L W k' ( − ) (3.10) This result in gs v <<2(V_GS −V_T) (3.11)

The above condition must be satisfied to neglect the last term and we have = d i _n V_GS V_T v_gs L W k' ( − ) (3.12) = = gs d m v i g _n' (V_GS V_T) L W k − (3.13)

3.2.2. Nonlinearities in CMOS Passive Mixers

Due to the absence of transconductance stage, only the switching transistors and other circuit components add nonlinearities. The discontinuity in switching action at zero crossing due to the voltage drop in gate voltage threshold of MOS switches generates intermodulation distortion. The finite rise and fall time of LO signals may create discontinuities and imbalance. Another phenomenon that adds nonlinearities in switching mixers is the modulation of Ron by higher input

signal levels [23].

3.3. Highly Linear Active Mixer

Active mixers consist of two stages. Transconductance stage performs voltage to current conversion and provides gain. Switching stage performs current commutation. Different techniques exist to improve the linearity of transconductance stage of active mixers. The architectures based on these techniques have their own merits and demerits in terms of power consumption, area consumption, and conversion gain and noise figure. While designing a

Highly Linear Mixer for On-chip RF Test in 130 nm CMOS

Highly Linear Mixer for On-Chip RF

Test in 130nm CMOS

Master thesis performed at division of Electronic Devices

by

Ghulam Mehdi

Highly Linear Mixer for On-Chip RF Test

Master thesis in Electronic Devices

at

Linköping Institute of Technology

by

Ghulam Mehdi

LiTH-ISY-EX--06/3913--SE

Abstract

Preface

Acknowledgments

Table of Contents

List of Figures

1.1. Introduction

1.2. Wireless Standards

1.2.1. GSM

1.2.2. UMTS

1.2.3. Bluetooth

1.2.4. Zigbee

1.3. BiST Technique

1.4. Loopback Test

1.4.1. TDD with Modulation at Baseband

1.4.2. TDD with Directly Modulated VCO

1.4.3. FDD with/without Modulated VCO

1.5. Offset Mixer Placement in Loopback

1.5.1. Placement before Test Attenuator (TA)

1.5.2. Placement after Test Attenuator (TA)

1.6. Required Mixer Specifications

2.1. Introduction

2.2. Ideal Multiplier

ω

ω

ω

ω

2.3. Mixer Types

2.3.1. Up & Down Conversion Mixers

ω

ω

ω

ω

ω

ω

ω

ω

ω

ω

2.3.2. Unbalanced & Balanced Mixers

2.3.3. Passive & Active Mixers

2.4. Mixer Performance Parameters

(

)

ω

[

]

π

µ

γ

ω

i

i

i

i

c

=

π

γ

π

γ

π

γ

2.4.3. Port-Port Isolation

( )

( )

( )

( )