Design of Multiplexed LO Single Mixer Receiver Front-End

(1)

Design of Multiplexed LO Single Mixer Receiver

Front-End

BABAK TAGHAVI

Master’s Thesis at ICT Department

Supervisors: Dr. Saul Rodriguez and Assoc. Prof. Ana Rusu Examiner: Assoc. Prof. Ana Rusu

(2)

(3)

iii

Abstract

A new quadrature receiver architecture is studied and designed in this thesis. In conventional quadrature receivers each of I and Q channels are down-converted separately using a mixer and a local oscillator (LO) in each path. On the other hand, the proposed architecture is based on multiplexed LO signals. As a result of multiplexing, just one LO buffer and one mixer are needed.

A top-down approach is used in the design of this receiver front-end. In the first design phase, a theoretical proof for the multiplexed LO down-conversion is provided. After that, the ideal and non-ideal system level design is per-formed using Agilent’s ADS. At system level, the bit error rate, sensitivity, and selectivity of the receiver are carried out using for example, a Gaussian MSK modulation/demodulation. The next phase is the circuit level design. The LNA, mixer, frequency divider, LO multiplexer-buffer, demultiplexer, and baseband amplifier circuits are designed in Cadence using a 65nm CMOS tech-nology. Different simulation setups and analyses, such as DC, AC, transient, HB, S-parameters, PSS, PAC, and NF are used in designing the sub-circuits of the receiver. The last phase of the design consists of floorplaning and layout of the chip.

(4)

(5)

v

Acknowledgment

During my master thesis, in the case of any problem I was confident that there is someone in the group who will really help me and encourage me to tackle it. He is Dr. Saul Rodriguez. Thanks Doctor! His extensive knowledge and outstanding patience has been the main driving force for me during this master thesis. He has been a very nice supervisor and a good friend for me.

My co-supervisor, whose high level management, punctuality, and kindness is well known, is Assoc. Prof. Ana Rusu. She has provided a unique atmosphere in her group so that everyone feels other colleagues as a family member. I admire her scientific, technical, and emotional support.

I would like to thank Assoc. Prof. Eduard Alarcon and Dr. Fadi Shahroury for hours of fertile discussions on my thesis. Also I should acknowledge the Swedish Research Council (VR) for the financial support of the project.

I am thankful to my colleagues, who shared the room and their knowledge with me. They are Rocco Luciano Grimaldi, Tingsu Chen, and my fellow, Milad Razzaghpour, whom we have spent memorable times together. Also it was a good opportunity for me to be with senior PHD students of our group. They are the kind girl, Tao Sha, prestigious Vasileios Manolopoulos, and hardworking Julian Garcia, and my awesome friend, Dr. Raul Onet. In addition to the support and guidance from my supervisors and colleagues, I should thank all my friends at the KTH who have always been helpful and kind to me. Among them my special thanks go to Hamed Rafi and Amin Vali, who were my great Linux teachers. I would like to thank two wonderful couples for sharing sweet times with me, my old friends Afsaneh and Hassan Foroughi , and my swimming partners Tove and Hans Brickner.

Although I am far away from Iran, my relatives and friends in Iran have always been supportive and passionate to me during my studies in Sweden. I appreciate their consistent friendship and it needs many pages to thank all of them. I would like to thank two of my best friends in Baku and Tabriz. First, Dr. Hamed Sabbagh, whose encouragements are never forgettable. Second, my hero and best friend, Azim Gheichisaz, who is a symbol of endurance and determination.

(6)

(7)

vii

Abbreviations and Acronyms

ADS Advanced Design System AM Amplitude Modulation

BB Base Band

BER Bit Error Rate

BW Bandwidth

CLK Clock

CMFB Common Mode Feedback CML Current Mode Logic DEMUX Demultiplexer

dft Discrete Fourier Transform GMSK Gaussian Minimum Shift Keying

GSM Global System for Mobile communications HB Harmonic Balance

IF Intermediate Frequency

L Length

LNA Low Noise Amplifier LO Local Oscillator LPF Low Pass Filter MIM Metal Insulator Metal MUX Multiplexer

NF Noise Figure PAC Periodic AC

PSS Periodic Steady-State QPAC Quasi Periodic AC

QPSS Quasi Periodic Steady-State RF Radio Frequency

SNR Signal to Noise Ratio

SP S-Parameter

VCO Voltage Controlled Oscillator

(8)

Introduction

Wireless communications has provided many uses for people all around the world. Two thousand cellphones are sold each minute in the world [1]. Nowadays almost all the cellphones and other wireless devices use CMOS technology. This huge market has urged designers to work on new systems or to improve the existing ones. Since 1992, wireless communication technologies have become mature [2]. Also by vast improvements in fabrication and design technologies it has become possible to integrate circuits with diverse functions on single chips. As RF designers, our focus is on the front-end of communication chips, which deal with high frequency analog signals. From the simple crystal detectors to current complex receiver front-end circuits, the primary goal of these circuits have been extracting the information that is received in the antenna of wireless devices.

The classical and widely used receiver architectures are reviewed in the first sec-tion. Afterwards, a brief description of the homodyne architecture and its pros and cons are presented. In the final sections of this chapter the scope and organization of this thesis are covered.

1.1 Classical Receiver Architectures

From the era of first wireless receivers until now, several receiver architectures have been proposed. The oldest and simplest type of receivers were crystal detectors.In crystal receivers the received signal is filtered by an RC network and rectified by a diode [3]. This receiver is called the AM receiver, which is depicted in figure 1.1. Although this architecture is simple, its poor sensitivity and weak selectivity urged designers to come up with new architectures. Later in 1902 Fessenden proposed the heterodyne receiver. The heterodyne architecture uses a local oscillator and has a better sensitivity and selectivity compared to the crystal detector.

In the heterodyne receivers a high frequency local oscillator (LO) is used to down-convert the received signal to an intermediate frequency (IF). Down-conversion exchanges the tough requirement of high-Q channel select filter, for an easier task of designing a tuneable LO [4]. A heterodyne receiver architecture is shown in figure

(12)

2 CHAPTER 1. INTRODUCTION Output Device Amplifier AM Detector Band Select Filter

Figure 1.1: Simple crystal detector

1.2. As shown in figure 1.2, the input signal which is centered at ωRF is multiplied

by the LO signal and the result is fed to a low pass filter (LPF). The output signal is centered at relatively lower frequency of ωIF, which facilitates the amplification

and filtering requirement of the next stages. The most important problem in a

het-LNA Image Reject Filter Next stage Filter cos ωLO t BSF

Figure 1.2: Heterodyne receiver architecture

erodyne receiver is to deal with the image problem [4]. This problem arises from the fact that there is no difference between cos(ω1− ω2)t and cos(ω2− ω1)t [5]. Conse-quently, if an unwanted signal, called the "image", exists in ωim, it will be translated

to the IF along with the desired input signal. The image problem is shown in figure 1.3. The image problem is alleviated by the use of an image rejection filter before the mixer. It should be noted that there is a trade-off between image rejection and channel rejection. Also availability and size of the image reject filter are critical factors in designing a heterodyne receiver [5].

(13)

1.1. CLASSICAL RECEIVER ARCHITECTURES 3 ωIF ω ω ωIF ωIF Desired Channel Interferer at Image Frequency ωLO After Down-Conversion

Figure 1.3: Image problem: Image signal is down-converted to the desired frequency

figure 1.4, more than one frequency conversion steps are involved in superheterodyne receivers. LNA Image Reject Filter LO1 LO2 Channel Select Filter 1 Channel Select Filter 2 BSF

Figure 1.4: Superheterodyne receiver architecture

(14)

4 CHAPTER 1. INTRODUCTION

1.2 Homodyne Receiver Architecture

Homodyne or zero-IF receiver was first invented by Colebrook in 1924 [3]. Unlike the heterodyne receiver, in zero-IF receivers LO frequency is chosen to be equal to the RF frequency. This architecture is depicted in figure 1.5. As shown in the fig-ure, two quadrature channels should be employed in the direct-conversion receiver. The reason for having I and Q channels is that the RF spectrum has different in-formation in its each sideband. Thus, in order to receive the inin-formation without any corruption, the two sidebands must be separated into two phases [6]. In other words, without quadrature channels, after down-conversion the negative sideband will be folded on the positive sideband [7]. Regarding to its simple architecture,

LNA 0o 90o LPF LPF LO I Channel Q Channel BSF

Figure 1.5: Homodyne receiver architecture

homodyne receivers have several advantages over heterodyne receivers. There is no image problem and therefor no need for image reject filter [5]. Another advantage of zero-IF receivers is that most of the filteration and amplification in the front-end is at baseband, which results in less power consumption [7]. Also it should be noted that there are some design issues and difficulties for the direct-conversion receivers which are presented in [6].

Although the direct-conversion method has its own difficulties in design, a sim-pler and smaller circuit size make zero-IF and low-IF receivers the most popular architectures found in modern mobile radio applications [8].

1.3 Scope of Thesis

(15)

1.4. THESIS ORGANIZATION 5

whole circuit working as good as possible, in order to demonstrate the feasability of the new architecture.

Unlike ordinary homodyne receivers which were briefly described in the last section, the proposed architecture has one mixer and one LO buffer. To try a new topology one should first prove the correctness of the principle behind this design. To do this, mathematical relations which model the proposed architecture are provided. Later a set of ideal simulations are carried out to ensure that the system functions properly. After completing the ideal simulations, a number of non-idealities such as noise and interference are added to the simulations. System level simulations are carried out in ADS. After ensuring the functionality of the proposed receiver the front-end circuit must be realized at circuit level. The whole receiver system is designed by connecting different building blocks. In circuit design all the blocks are designed at transistor level. Simulations for each block are done with considerations about preceding and succeeding blocks in the whole system. Different analyses and tools in the Cadence are used to simulate these sub-circuits. When all circuits are designed then all circuits are put together and the system is tested. After accomplishing the desired functionality, the receiver circuit is laid out in 65 nm CMOS technology. In the time of writing this report the layout work was ongoing and after finishing the layout the chip will be sent for fabrication.

1.4 Thesis Organization

This thesis covers a complete top-down design flow, starting from system level and ending with layout of circuits. The organization of this thesis is as follows.

In chapter 2, the proposed system is analyzed and system level simulations are carried out.

Chapter 3 presents the complete circuit level design. All the blocks that are used at system level are realized by their corresponding circuits and finally they are put together to simulate the entire receiver chip.

(16)

(17)

Chapter 2

Theory and System Level

Design

The Backbone of a novel architecture is the theoretical proof for the idea. After describing the system by mathematical expressions, the next step to develop an RF or mixed signal system is the system level design. The top level system design lets designers to examine the functionality of their idea without spending too much time on details of each block. Later on, going down in the design hierarchy, circuit design and layout limitations should be added to the models. In this chapter, we focus on the theory and system level design. The theory of the proposed multiplexed LO single mixer receiver is developed in the section 2.1. Going to the design stage in ADS, an ideal transmitter and receiver system are designed in ADS, which are fully described in section 2.2. After adding non-idealities such as noise and blockers, simulation results are presented in section 2.3.

2.1 Proposed System

As mentioned in the previous chapter, one of the reasons for using the direct-conversion receiver is its simplicity compared to the superheterodyne receiver. On the other hand, direct-conversion needs a quadrature architecture, which doubles the number of components in the receiver front-end. For instance it must have two mixers, two LO buffers, and two BB amplifiers and filters. If one can change the number of subsystems in this architecture, then there will be reduction of dissipated power and also active area on chip.

The LO buffer is one of the most power hungry circuits in the receiver front-end. It is used to drive the LO port of the mixer. Moreover, because of having zero-IF, the operating frequency of the LO and its buffer is equal to the RF signal. To work in high frequency and drive a capacitive load, like the mixer, the LO buffer will consume a considerable amount of power. Also in older CMOS technologies, using an inductor in the LO buffer is inevitable, which means an increase in the size of the circuit. Therefore, regarding these two points about power and size, we started

(18)

8 CHAPTER 2. THEORY AND SYSTEM LEVEL DESIGN

to work on a direct-conversion receiver with one mixer and one LO buffer.

The single mixer direct-conversion receiver architecture is shown in figure 2.1. LO signals are multiplexed by s1 and s2, which are simple switches. The result of this multiplexing is a signal which consists of the LO signal with 0 and 90 degrees phase shift. The multiplexed LO signal is fed to the LO port of the mixer. In the mixer the RF signal is multiplied by the LO signal. Afterwards, the IF output of the mixer is demultiplexed by s0

1 and s

0

2, which are synchronous with s1 and s2, respectively. After demultiplexing, the information is split in I and Q channels. Subsequently, the I and Q channels are passed through a low pass filter to cut their out of band frequency components. LNA 0o 90o LPF LO I Channel Q Channel BSF LPF S1 S´1 S´2 S2 Mixer

Figure 2.1: Proposed multiplexed LO single mixer receiver front-end

2.1.1 Mathematical Proof

Lets assume AsinωLOt and AcosωLOt as quadrature LO signals. These signals are

multiplexed by s1 and s2, which are complementary switches controled by mux(t).

mux(t) is a pulse train signal, which has a period equal to Tsw with a 50% duty

cycle, where Tsw is the switching frequency.

mux(t) =      1, for 0 < t < Tsw 2 0, for Tsw 2 < t < Tsw (2.1)

(19)

2.1. PROPOSED SYSTEM 9

scheme results in LO(t), which is connected to the LO port of the mixer:

LO(t) =      AsinωLOt, for 0 < t < Tsw 2 AcosωLOt, for Tsw 2 < t < Tsw (2.2) In equation (2.2), ωLO and A are the frequency and amplitude of the LO signal,

respectively. The multiplexing scenario and resulting LO(t) are illustrated in figure 2.2. As shown in the figure, LO(t) is a sine wave when mux(t) is high and cosine wave when mux(t) is low.

TSW mux(t) 2 TSW AsinωLOt AcosωLOt AsinωLOt AcosωLOt TSW 2 TSW TSW 2 TSW AcosωLOt AsinωLOt (a) (b) (c)

Figure 2.2: Switching the LO signal; (a) mux(t),sine and cosine waves, (b) signals after switches, (c) multiplexed sine and cosine waves

The RF signal which is applied to the RF port of the mixer can be shown as equation (2.3). This signal consists of the information of I and Q channels, modulated by quadrature sine waves at ωRF.

RF(t) = I(t).sinωRFt+ Q(t).cosωRFt (2.3)

Frequency translation in the mixer which is a multiplication of signals from RF and LO ports of the mixer, is depicted in the following equations:

IF(t) = RF (t).LO(t) =

(

[I(t).sinωRFt+ Q(t).cosωRFt].AsinωLOt

[I(t).sinωRFt+ Q(t).cosωRFt].AcosωLOt

(20)

IF(t) is the output of the IF port of the mixer. For direct-conversion or zero-IF,

we have ωLO = ωRF. Thus, after calculations, IF (t) can be written as

IF(t) =            1

2[A.I(t) − A.I(t).cos2ωRFt+ A.Q(t).sin2ωRFt]; 0 < t <

Tsw

2 1

2[A.I(t)sin2ωRFt+ A.Q(t) + A.Q(t).cos2ωRFt];

Tsw

2 < t < Tsw

(2.5) Note that the first line in equation (2.5) is for the time in which s1 is on, and the second line is valid when s2 is on.This decision making is done by demultiplexing switches, s0

1and s

0

2. As a result of demultiplexing, the I and Q channels are separated from each other. I and Q signals after s0

1 and s

0

2 are denoted by IIF(t) and QIF(t),

respectively. IIF(t) and QIF(t) are given by:

IIF(t) = 1₂[A.I(t) − A.I(t).cos2ωRFt+ A.Q(t).sin2ωRFt] (2.6)

QIF(t) = 1

2[A.I(t)sin2ωRFt+ A.Q(t) + A.Q(t).cos2ωRFt] (2.7)

In the later stage an LPF is applied to the resulting signals from equations (2.6) and (2.7), which will lead to extracting I and Q channels in base-band with an A₂ gain. Equations (2.8) and (2.9) show the final outputs of the receiver front-end:

IBB(t) = A 2I(t) (2.8) QBB(t) = A 2Q(t) (2.9)

2.2 System Level Design Using ADS

The proposed idea is first tested at system level. To do this, we used the Agilent’s Advanced Design System (ADS). The ADS has unique functionalities for RF design. An ideal single mixer receiver has been developed and then non-idealities have been added to it. A top level block diagram of the architecture is depicted in figure 2.3. At the input side, a random data sequence is generated by a data block. The bandwidth of input data is defined by BWin= 1

BitT ime. For instance, BWin for a

GSM transceiver is 200 KHz. After the data generator block, modulator, channel, receiver, and measurement blocks are placed.

(21)

2.2. SYSTEM LEVEL DESIGN USING ADS 11 Receiver Measurement Blocks Measurement Blocks Sync Sync Ideal Channel Transmitter Reference Q Output Q Output I Reference I

Figure 2.3: Top level block diagram for the ideal architecture

up-conversion block diagram is shown in figure 2.4. It should be mentioned that all the RF components which are used in the ADS design have matched inputs and outputs. Therefore, when it is needed to connect a measurement device, it is better to use a power splitter block in the desired path. The power splitter will provide two outputs which are exactly the same and can be used separately for signal path and measurement purposes. Digital data is generated by the Data block. Afterwards

Sin Sinusoid Frequency=fLO DelayRF Delay=1/fLO/4 MultiplierRF Gaussian GainRF I Q MultiplierRF Gaussian Port Port Port SplitterRF SplitterRF SymbolSplitter SummerRF Measurement Port Measurement Port Modulate Signal Data Data

(22)

a SymbolSpliter block is used to split the input data to I and Q channels. Data in each channel has half the bandwidth of input data. For instance, for a GSM transmitter, bandwidth of each of I and Q channels is 100 KHz. The splitting action is clearly demonstrated in time domain in figure 2.5. As can be seen in figure 2.5a the smallest pulse width is equal to the BitTime which is set to 50 µs. Data in I and Q channels have minimum pulse width equal to 100 µs. In frequency domain it is even more clear that after the splitter block the bandwidth of each channel shrinks to 100 KHz, which is half of the BWin.

-2.0 -1.5 -1.0 -0.50.0 0.5 1.0 1.5 2.0 -2.5 2.5 T _ D a ta , V -2.0 -1.5 -1.0 -0.50.0 0.5 1.0 1.5 2.0 -2.5 2.5 T _ D a ta _ I, V 20 40 60 80 100 120 140 160 180 0 200 -2.0 -1.5 -1.0 -0.50.0 0.5 1.0 1.5 2.0 -2.5 2.5 time, usec T _ D a ta _ Q , V Time (usec) In p u t D a ta D a ta _ I D a ta _ Q (a) 50 100 150 200 250 300 350 400 450 500 0 550 -60 -40 -20 0 -80 20 freq, KHz d B (S _ D a ta ) -55 -50 -45 -40 -35 -30 -25 -20 -15 -10-5 0 5 -60 10 d B (S _ D a ta _ I) 50 100 150 200 250 300 350 400 450 500 0 550 -55 -50 -45 -40 -35 -30 -25 -20 -15 -10-5 0 5 -60 10 freq, KHz d B (S _ D a ta _ Q ) Frequency(KHz) d B (D a ta _ I) d B (D a ta _ Q ) d B (D a ta ) (b)

Figure 2.5: Input data and resulting I and Q channels data; (a) time domain, (b) frequency domain.

Next block in 2.4 is a Gaussian filter. We can choose a typical modulation method like GMSK modulation scheme. In the GMSK, I/Q information are passed through a Gaussian filter. This filtering helps to make a narrower information bandwidth or speaking in time domain, it makes the edges of information signal smoother. The information signal after filtering is shown in figure 2.6. After filtering

-2.0 -1.5 -1.0 -0.50.0 0.5 1.0 1.5 2.0 -2.5 2.5 T _ s h a p e d _ I, V 20 40 60 80 100 120 140 160 180 0 200 -2.0 -1.5 -1.0 -0.5 0.0 0.5 1.0 1.5 2.0 -2.5 2.5 time, usec T _ s h a p e d _ Q , V Time(usec) S h a p e d I S h a p e d Q (a) -50 -40 -30 -20 -10 0 -60 10 d B (S _ sh a p e d _ I) 50 100 150 200 250 300 350 400 450 500 0 550 -40 -30 -20 -10 -50 0 freq, KHz d B (S _ sh a p e d _ Q ) d B (S h a p e d Q ) d B (S h a p e d I ) Frequency(KHz) (b)

(23)

2.2. SYSTEM LEVEL DESIGN USING ADS 13

stage, information signals are ready for being up-converted. For up-conversion, two ideal mixers are used. One LO signal is taken directly from a sinusoid signal generator and the other LO is a 90 degree shifted version of the same source. The phase shift is realized by the DelayRF block. The delay time is set to _4f1

LO, which

leads to 90 degree phase shift in LO path. Modulated signals are summed and then fed to the GainRF block. Transmitter gain can be set by the GainRF block. Final output of transmitter in time and frequency domain is shown in figure 2.7. As shown in figure 2.7, we have set fLO = fRF = 45MHz. Without losing generality,

this reduction of RF center frequency from the actual 900 MHz to 45 MHz is just for saving the simulation time.

20 40 60 80 100 120 140 160 180 0 200 -6 -4 -2 0 2 4 6 -8 8 time, usec T _ R F , u V 43.8 44.0 44.2 44.4 44.6 44.8 45.0 45.2 45.4 45.6 45.8 46.0 46.2 43.6 46.4 -170 -160 -150 -140 -130 -120 -180 -110 freq, MHz d B (S _ R F ) Frequency(MHz) Time(usec) R F S ig n a l d B (R F S ig n a l)

Figure 2.7: Modulated signal in time and frequency domains

The channel between the transmitter and the receiver is ideally modeled by a simple connection.

2.2.1 Design of the Proposed Receiver in ADS

(24)

14 CHAPTER 2. THEORY AND SYSTEM LEVEL DESIGN Sin Pulse PlateauTime=1/fs/2 RepetitionInterval=1/fs Sinusoid Frequency=fLO DelayRF Delay=1/fLO/4 SwitchSPST SwitchSPST SwitchSPST SwitchSPST MultiplierRF Gain Logic Inverter Gaussian Gaussian GainRF GainRF Limiter Limiter Port Port I Q Modulated Signal

Figure 2.8: ADS model for the proposed single mixer receiver

The pulse generator provides the switching signal or mux(t). The output of the pulse generator is a pulse train and its frequency is fs. Two switches are

directly driven by the pulse generator, while the other two switches are driven by an inverted version of the pulse. This inversion is done by a Logic Inverter and a Gain block. The Gain block is used to adjust the level of the inverted signal to the same level as the direct output of the pulse generator.All switches are identical and they are sensitive to the level of their control signal. When mux(t) is high,s1 and s0

1 switch ON, while s2 and s

0

2 are OFF and vise verse when mux(t) is high. At the input side, s1 and s2 are connected to sine and cosine signal generators, respectively. Output signals of the s1 and s2 are connected together and the signal formed from this combination is denoted by Multiplexed-LO, which is shown in time and frequency domains in figure 2.9. In figure 2.9a switching instances and the resulting waveforms are shown. Figure 2.9b gives more insight about the effects of multiplexing the LOs by a square wave. As expected, the original sine or cosine wave, which has a single tone at fLO is repeated at fLO ± fS, fLO ±2.fS, ....It is

obvious from figure 2.9 that the most dominant harmonic in the multiplexed LO is the one at fLO± fS, which is 3dB smaller than the main LO tone. The switching

frequency will determine how close are the harmonics to the main tone. Also, we should consider how the characteristics of other blocks of the receiver chain are affected by a choice of switching frequency.

Lower boundary for fS is defined by the Nyquist- Shannon sampling theorem.

Obviously, to maintain all the information, the switching frequency must be at least two times larger than the data bandwidth of each channel.

fs≥2.BWch (2.10)

where, BWch is the bandwidth of each channel. According to equation (2.10), for a

(25)

2.2. SYSTEM LEVEL DESIGN USING ADS 15 100.05 100.10 100.15 100.20 100.25 100.30 100.00 100.35 -1.0 -0.5 0.0 0.5 1.0 -1.5 1.5 time, usec T _ s a m p le d _ L O , V T _ Pu ls e , V M u lt ip le x e d _ L O M u x (t ) … . _ _ Time (usec) (a) 6 8 10 12 14 16 18 4 20 -40 -20 0 -60 20 freq, MHz d B(c lk ) 20 30 40 50 60 70 10 80 -60 -40 -20 0 -80 20 freq, MHz d B(S_ s a m p le d _ L O ) d B ( M u lt ip le x e d _ L O ) d B (M u x ) Frequency(MHz) Frequency(MHz) (b)

Figure 2.9: Multiplexed LO signals and the multiplexing signal; (a) time domain, (b) frequency domain.

thumb, a low switching frequency eases the requirements of the switching circuit.On the other hand, if fs is very low, then the harmonics due to switching action will

be too close to the desired LO frequency. As a result, the channel select filtering will become a tough job. Additionally, by switching the LO, noise in the LO path will be sampled and folded into the band of interest. Therefore, a low switching frequency will lead to a higher noise floor or lower dynamic range.

To select the switching frequency, we should compromise between requirements of the switches and channel select filter and noise floor. Also from circuit design point of view, availability of the switching frequency is a key factor. As it will be discussed more in the circuit design chapter, a frequency divider is needed to provide quadrature and differential LO signals for the mixer. A chain of frequency dividers can be used to generate the switching signal. Also a divide-by-two circuit seems to be the least challenging frequency divider circuit. Thus, a cascade of divide-by-two dividers proves to be a reasonable choice to generate the switching signal. We have chosen fS =

fLO

(26)

The next block is a MultiplierRF. This block is the single mixer in our archi-tecture. RF and LO signals are mixed and the result is the IF signal. IF is shown in figure 2.10. The low frequency IF is at fs = 11.25MHz. IF also has a high

frequency component at 78.75 MHz, which is easily removed by demultiplexing and filtering in later stages.

10 20 30 40 50 60 70 80 0 90 -134 -132 -130 -128 -126 -124 -122 -136 -120 freq, MHz d B m (S _ IF ) d B (I F S ig n a l) Frequency(MHz)

Figure 2.10: Down-converted signal after the mixer

In the next stage, I and Q channels should be separated. Demultiplexing the IF signal by s0

1 and s

0

2 results in separated I and Q channels. Frequency domain repre-sentation of I and Q signals after s0

1 and s

0

2 are shown in figure 2.11. Signals after

s0₁ and s0₂ contain the baseband information and other high frequency components

due to the harmonics of mux(t).

All high frequency components will be attenuated by low-pass filters in base-band. Gaussian filters are used as low-pass filters. These filters have the same characteristics as those used in the transmitter. I and Q signals after the Gaus-sian filter are shown in figure 2.12. As can be seen in figure 2.12b, high frequency component of output signals are greatly attenuated.

(27)

2.2. SYSTEM LEVEL DESIGN USING ADS 17 -90 -85 -80 -75 -70 -95 -65 .. .e3 *S_ I_a ft er_ s w it c h) 1 2 3 4 5 6 7 8 9 10 11 0 12 -90 -85 -80 -75 -70 -95 -65 f req, MHz .. .3* S_ Q_ af ter_ s w it c h) Frequency(MHz) dB(I_Before Filter) dB(Q_Before Filter)

Figure 2.11: I and Q signals after s0

1 and s 0 2 0 -1 1 T _ I_ b e fo re _ fil te r, u V 20 40 60 80 100 120 140 160 180 0 200 0 -1 1 time, usec T _ Q _ b e fo re _ fil te r, u V Time(usec) I_ A ft e r F ilt e r Q _ A ft e r F ilt e r (a) -130 -120 -110 -100 -90 -80 -70 -140 -60 .. .3 *S _ I_ b e fo re _ fi lt e r) 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 0.0 1.0 -130 -120 -110 -100 -90 -80 -70 -140 -60 freq, MHz .. .* S _ Q _ b e fo re _ fi lt e r) Frequency(MHz) dB(I_After Filter) dB(Q_After Filter) (b)

Figure 2.12: Received I and Q after the low-pass filter ; (a) time domain, (b) frequency domain.

a synchronization delay in the measurement path is to compensate the delays which are introduced by the filters in the transmitter and receiver.

Another common way to evaluate the performance of a digital receiver is to use constellation diagrams. In order to generate a constellation diagram for the system under test, we have used the TKConstellation block in ADS. One port of this block is connected to the input data as the reference signal, and the other port is con-nected to the output data. In figure 2.14, the constellation diagram for channel I is shown. The constellation diagram for channel Q is the same as channel I. From this constellation diagram it can be deduced that the sent data is received without any change in its amplitude or phase.

(28)

18 CHAPTER 2. THEORY AND SYSTEM LEVEL DESIGN -2.0 -1.5 -1.0 -0.5 0.0 0.5 1.0 1.5 2.0 -2.5 2.5 T _ D a ta _ I, V 20 40 60 80 100 120 140 160 180 0 200 -2.0 -1.5 -1.0 -0.5 0.0 0.5 1.0 1.5 2.0 -2.5 2.5 time, usec T _ I_ o u t, V Time(usec) I_ O u t D a ta _ I (a) -2.0 -1.5 -1.0 -0.5 0.0 0.5 1.0 1.5 2.0 -2.5 2.5 T _ D a ta _ Q , V 20 40 60 80 100 120 140 160 180 0 200 -2.0 -1.5 -1.0 -0.5 0.0 0.5 1.0 1.5 2.0 -2.5 2.5 time, usec T _ Q _ o u t, V Time(usec) Q _ O u t D a ta _ Q (b)

Figure 2.13: Received data after the limiter compared with synchronized input data; (a) channel I, (b) channel Q.

Figure 2.14: Constellation diagram for the ideal receiver conditions.

2.3 Simulations with Non-Idealities

In this section simulations after adding noise and interferer are presented. These analysis are carried out to ensure the tolerance of the system to non-idealities. A touchstone for acceptable performance of a digital communications receiver is the bit error rate or, BER [9] [10] . In all of our simulations the maximum acceptable BER is chosen to be 10−2_.

2.3.1 Sensitivity Analysis

(29)

2.3. SIMULATIONS WITH NON-IDEALITIES 19

factor of two. In other words, for a multiplexing system with two switches the signal power and consequently the SNR drops by 3dB [11] [12]. This phenomenon can be proved by a simple test setup in ADS. In this simulation the SNR for a sine wave with an added noise is compared to the SNR of the same signal after multiplexing. As shown in figure 2.15, the noise power is almost the same in both cases, while the signal power is roughly 3dB lower after multiplexing.

-30 -25 -20 -15 -10 -5 0 5 -35 10 d B (S 2 a ) 25 30 35 40 45 50 55 60 65 20 70 -30 -25 -20 -15 -10 -5 0 5 -35 10 freq, MHz d B (S 2 b ) SNR = 36.2 dB SNR = 32.5 dB Before Multiplexing After Multiplexing Frequency(MHz) dB

Figure 2.15: Effect of multiplexing on SNR

This can be considered as a drawback for multiplexed- LO receiver. On the other hand, the proposed system has advantages in terms of its DC rejection in baseband and easier requirements in channel select filter.

A simple way to add noise in a system level design is to add the noise block to the ideal channel, as shown in figure 2.16. The noise generator block in ADS is AddNDensity, in which the noise power is set by NDensity parameter.

It should be mentioned that in order to sweep the SNR values, noise power is set to a constant value and the signal power is tuned. By running parametric simulations for the SNR, different values for the BER are obtained. Considering

BERmax = 0.01, the SNR that leads to this value is the SNRmin. After running

a parametric simulation, the minimum SNR is SNRmin = 19dB. In another

simu-lation in order to illustrate the effect of added noise on the output bits, the signal power is set to -112dB. This SNR value is lower than the minimum allowable SNR, and therefore has obvious effects on the output bits. Output corruption in both channels due to the low SNR, is shown in figure 2.17. As it is denoted on the figure, the output has incorrect bits which are the erroneous bits.

(30)

20 CHAPTER 2. THEORY AND SYSTEM LEVEL DESIGN AddNDensity Receiver Measurement Blocks Measurement Blocks Sync Sync Transmitter Reference Q Output Q Output I Reference I

Figure 2.16: Adding noise to the channel to study the sensitivity

-2 -1 0 1 2 -3 3 T _ D a ta _ I, V 80 100 120 140 160 180 60 200 -2 -1 0 1 2 -3 3 time, usec T _ I_ o u t, V Time(usec) I _ O u t D a ta _ I Error (a) -2 -1 0 1 2 -3 3 T _ D a ta _ Q , V 80 100 120 140 160 180 60 200 -2 -1 0 1 2 -3 3 time, usec T _ Q _ o u t, V Error Time(usec) Q _ O u t D a ta _ Q (b)

Figure 2.17: Corrupted received data with signal power=-112dB ; (a) channel I, (b) channel Q.

values.

2.3.2 Selectivity Analysis

(31)

Figure 2.18: Constellation diagram for signal power=-112dB

AddNDensity

Receiver

Measurement Blocks Measurement Blocks Sync Sync

Transmitter

Reference Q Output Q Output I Reference I Summer RF Sin Sinusoid f=fLO + X

Figure 2.19: Adding the interferer to the channel to study the selectivity

selectivity simulations the SNR of the desired RF signal is set to SNRmin = 19dB.

Frequency of the blocker signal is set by fBK = fLO± x, in which fBK and x are

the blocker frequency and the distance of blocker from the desired RF frequency. The blocker mask for the proposed receiver is obtained by setting |x| to 0.6, 1.1, 1.6, 2.3, 3, and 4.5 MHz. Considering the performance limit of BERmax = 0.01, Power

(32)

22 CHAPTER 2. THEORY AND SYSTEM LEVEL DESIGN fRF fRF + 0 .6 M H z fRF + 1 .6 M H z fRF + 3 M H z fRF -0 .6 M H z fRF -1 .6 M H z fRF -3 M H z -100 -67 -57 -47 -67 -57 -47 Receiver Bandwidth f dBm fRF + 2 .3 M H z fRF -2 .3 M H z fRF + 1 .1 M H z fRF -1 .1 M H z fRF + 4 .5 M H z fRF -4 .5 M H z

Figure 2.20: Blocking mask for the receiver with BERmax = 0.01

As mentioned earlier, the choice of multiplexing frequency plays an important role in the selectivity performance. We can assume a blocker signal at fLO+ fSW.

Moreover, the multiplexed LO has a harmonic at the same frequency. As a result, the blocker signal will be mixed with an LO signal with the same frequency, which leads to blocking the receiver, as shown in figure 2.21. To overcome this problem we

0

f

f Desired

Channel

Resulting Baseband Signal

f fLO -fSW _f_LO fLO -2 fSW fLO -3 fSW fLO +3 fSW fLO +2 fSW fLO +fS W Interferer fSW

(33)

should set fSW large enough, that the input band select filter can fully attenuate

(34)

(35)

Chapter 3

Circuit Design

3.1 Introduction

After completing the system level design, all of the blocks of the system are im-plemented with appropriate circuits. As mentioned in the previous chapter, the transmitter is just modeled for providing modulated signals. Thus, in circuit design we focus on the receiver design and model the transmitter by ideal models. Cadence Virtuoso environment is chosen for circuit design and simulation. In order to simu-late both RF and baseband signals, various analysis have been used (e.g., harmonic balance, transient, ac, pss) [14]. In our design, each circuit is designed to fulfill the requirements that are extracted from system level design. This chapter covers the circuit design for a matched LNA, a frequency divider chain, an LO multiplexing circuit, a mixer, demultiplexing switches, and baseband amplifiers.

3.2 Low Noise Amplifier

After the antenna and band select filter, the LNA is usually the first circuit in the receiver front-end. The objective of using an LNA is to amplify the input RF signal while adding a minimum amount of noise to the signal [15]. Also in order to have a reliable and accurate measurement, the input of the LNA must be matched to 50 ohm impedance.

In this project a single-to-differential LNA similar to the one in [16] and a common gate differential-to-differential LNA are designed and simulated in a com-plete receiver chain. Considering the feed-through, mismatch and input impedance matching, the common gate amplifier has a better performance. Methods for de-signing a CMOS RF LNA circuit are presented in [17].

_B2

out

in

R

D

R

D

V

DD

Figure 3.1: Common gate LNA circuit, only the signal path

transistor models let the designer to merely focus on the signal path without worry-ing about DC bias circuitry design. In this circuit our primary concerns are havworry-ing a decent gain and low noise figure (NF), while consuming a low amount of power. By performing DC and AC analyses and also considering the DC characteristics of the transistors the required current and voltage values are determined. Table 3.1 contains dimensions and DC operating points for M1,3 and M2,4. Voltage gain of this LNA is roughly equal to

Av ≈ gm1(RD||Rout) (3.1)

Table 3.1: Size and DC operation points for transistors in signal path

(37)

3.2. LOW NOISE AMPLIFIER 27

By choosing RD = 500Ω, and considering Rout = 200Ω, which models the following

passive mixer, the resulting voltage gain is calculated to be 7 dB. This AC gain is also obtained from ac simulation. AC response of the LNA is shown in figure 3.2. The LNA has a bandwidth roughly equal to 1.2 GHz. This bandwidth is enough to pass the desired RF signal, while it attenuates the high frequency out of band signals. 100 102 104 106 108 1010 5.9 6 6.1 6.2 6.3 6.4 6.5 6.6 6.7 6.8 6.9 F(Hz) Voltage Gain (dB)

Figure 3.2: AC voltage gain of the LNA

To have the final topology of the LNA, the bias circuits must be added to the LNA circuit. M5 is used as a current mirror to bias M2,4. Vgs of M1,3 are set by a resistor and diode connected M6 and M7. Completed LNA circuit is shown in figure 3.3.

Noise performance of the LNA can be improved by reducing the noise current added by M2 and M4. A systematic way to find the minimum NF is to use a parametric simulation. The width of M2 and M4 are swept from 3 to 16 µm and corresponding NF curve is depicted in figure 3.4. NFmin is achieved when W2,4 = 7µm.

According to the layout consideration, it is recommended to have an even num-ber of fingers. As a result, M2,4 are decided to have NF=4 and Wf inger = 1.75µm.

Next step is to test the input matching for the LNA. The input reflection coeffi-cient or S11is extracted from the S parameter (SP) analysis in Cadence. S11versus frequency curve is illustrated in figure 3.5. The reflection coefficient is around -17 dB, at 1 GHz.

2 4 6 8 10 12 14 16 4.95 5 5.05 5.1 5.15 5.2 5.25 5.3 W(μ m) Noise Figure

(39)

3.2. LOW NOISE AMPLIFIER 29 0.8 0.85 0.9 0.95 1 1.05 1.1 1.15 1.2 1.25 −17.16 −17.155 −17.15 −17.145 −17.14 −17.135 −17.13 −17.125 −17.12 F(GHz) S11(dB)

Figure 3.5: Reflection coefficient at input of the LNA

10 11 12 13 14 15 −15 −10 −5 0 5 10 15 Time(ns) Input( μ V) (a) 10 11 12 13 14 15 −25 −20 −15 −10 −5 0 5 10 15 20 25 Time(ns) Output( μ V) (b)

Figure 3.6: Transient simulation; (a) Input signal, (b)Output of the LNA Table 3.2: Summary of LNA performance

Performance parameter Value

Gain 6.85 dB

NF 4.98 dB

S11 -17 dB

(40)

3.3 Frequency Divider

The frequency divider circuit is responsible for providing the LO signal to the mixer. In our design the clock signal or the input of divider comes from an off-chip signal source and there is no on-chip VCO.

There are different frequency divider architectures which have been subject to stud-ies for many years. A dynamic divider is studied in [18]. Another frequency divider architecture can be found in [19, 20]. Finally, the architecture that is used in our design is the same as architectures in [21,22], which use current mode logic (CML) circuits.

2

_

CLK

Figure 3.7: Flip-flop based frequency divider

3.3.2 CML Latch and Buffer Circuits

(41)

3.3. FREQUENCY DIVIDER 31

differential pair consisting of M1 and M2, and M5 can be called the track circuit. On the right side of the circuit, M6 and the cross-coupled M3 and M4 form the hold circuit. This circuit has four input and two output ports. Inputs D and ¯Dare

connected to ¯Qand Q of the second latch. CLK+and CLK− are connected to the

differential LO signal source.

M4 M1 M2 D M3 RD RD VDD M5 CLK M6 M7 M8

I

Bias _ D Q _ Q + _CLK_

Figure 3.8: Current mode logic latch circuit

To describe the operation of the circuit in figure 3.8, assume that CLK+ _{is high.} This causes M5 to be on and M6 switches off. In this state all the tail current flows through the track circuit. Assuming D to be high, then Q becomes high and ¯Q

becomes low the same as ¯D. In other words, it can be said that the circuit is in

track mode when CLK+ _{is high. Afterwards in the period when CLK}− _{is high,}

M6 turns on and M5 is switched off. In this state M3 and M4 are biased by the tail current. In the track mode Q was high, which means that the gate voltage of

M4 is high and M4 turns on. At the same time as ¯Q is low then M3 is off. While

M3 is off, Q will hold the high value that it had. Accordingly, circuit operates in hold mode when CLK−_{is high. It should be mentioned that the track circuit has a} dominant role in the speed performance of the latch circuit. Therefore we focus on the design of the differential pair in the track sub-circuit and we will use the same transistors for the hold sub-circuit.

The first thing to consider about the speed of this circuit is how fast the transistors operate. Characterization curves are used to find the proper operating points. Choosing W = 30µm the transistor has gm= 18m, fT = 125GHz, and ID = 2.7mA.

(42)

the circuit in figure 3.8, which can be quantified as follows,

ωout≈ 1

RD.Cout

≈ 1

RD.2[Cgd+ Cdb] (3.2)

equation (3.2) shows that RD must be kept as small as possible. On the other

hand, value of RD decides the output signal swing. According to these two points,

we have chosen RD = 200Ω. For the transistor with W = 30µm, sum of the parasitic

capacitors Cgd and Cdb is estimated to be around 60fF for this technology. Putting

these values in equation (3.2) shows that the output pole is placed around 42GHz. This bandwidth is adequate for the desired operating frequency of the divider circuit. To isolate the divider circuit from the next stages it is better to use a high speed buffer at the output of the frequency divider of figure 3.7. The buffer circuit is also designed using a CML circuit. Buffer circuit is shown in figure 3.9. Tail current is set to 1.6mA and RD = 600Ω. To minimize the parasitics, the length of transistor

is set to minimum value (i.e. 60nm), while W = 20µm.

M

1

M

2

in

R

D

R

D

V

DD

M

3

M

4

I

Bias

_

in+

out

Figure 3.9: Current mode logic buffer circuit

(43)

3.3. FREQUENCY DIVIDER 33 9 9.5 10 10.5 11 11.5 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 1.1 1.2 Time(n s) Output(V) ... Before Buffer ___ After Buffer

Figure 3.10: Frequency divider output, with and without buffer

3.3.3 Frequency Divider Chain

As mentioned earlier, the frequency divider is used for frequency division and also providing quadrature signals needed for quadrature down-conversion. Additionally, as discussed in system level design the multiplexing signals should be generated on-chip. An architecture that can provide both quadrature LO signals and the multiplexer signal is depicted in figure 3.11. In this configuration there are three dividers in series. The outputs of the first divider are the quadrature LO signals, which are at 1₂fin. The second and third dividers have outputs at 1

4fin and 1

8fin,

respectively.

CLK

Divider1 Divider2 Divider3

LO0

LO180

LO90

LO270

mux

(44)

For our receiver circuit which has fRF = 1GHz the CLK input must be set to

2GHz. Therefore the frequency of LO0−270 is 1GHz and fmux = 250MHz. All

the dividers in figure 3.11 have the same structure. However, since Divider2 and Divider3 operate at lower frequencies, they can be designed with lower tail currents. To maintain an enough voltage swing, RD of these two dividers are chosen to be

600Ω.

In order to show the functionality of the divider chain, transient simulations are set up and run. Input and output signals are shown in figure 3.12. The input signal is a square wave with f = 2GHz. It is illustrated in figure 3.12a that the output LO signals are quadrature or in other words each has 90 degree phase difference with other outputs. Also the multiplexing signal is shown in figure 3.12b.

4 6 8 10 12 14 16 0.4 0.6 0.8 1 1.2 O0 4 6 8 10 12 14 16 0.2 0.4 0.6 0.8 1 1.2 O90 6 8 10 12 14 16 0.2 0.4 0.6 0.8 1 1.2 O180 4 6 8 10 12 14 16 0.2 0.4 0.6 0.8 1 1.2 Time(ns) O270 (a) 4 6 8 10 12 14 16 0.4 0.6 0.8 1 1.2 mux + 4 6 8 10 12 14 16 0.4 0.6 0.8 1 1.2 mux − Time(ns) (b)

(45)

3.4. LO MULTIPLEXER AND BUFFER 35 1 2 3 4 5 6 7 8 −70 −60 −50 −40 −30 −20 −10 X: 1 Y: −5.725 F(GHz) Vout (dB) (a) 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 −120 −100 −80 −60 −40 −20 0 X: 0.25 Y: −4.891 F(GHz) Vout (dB) (b)

Figure 3.13: Frequency divider outputs; (a) Divide by two, (b)Divide by eight Output signals show that the frequency divider block works as expected. Power consumption of each divider and each buffer of figure 3.11 is shown in table 3.3. With PDivtotal = 18.72mW ,this block has the maximum power consumption in the

whole receiver front-end.

Table 3.3: Power consumption in frequency divider chain Circuit Power(mW) Divider1 6.48 Divider2 3.36 Divider3 3.36 LO buffers 3.84 mux buffer 1.68 Total 18.72

3.4 LO Multiplexer and Buffer

Figure 3.14: LO multiplexer and buffer circuit

the multiplexing signals, which have a lower frequency. The circuit in figure 3.14 is differential. In this circuit the CMOS transistors operate in either triode or off regions. As a result, the output is the same as I0 and I180, when S1 is high. On the other cycle when S2 is high, I90and I270are copied to the output. For a tail current equal to 2.3mA the proper size of the devices are as shown in table 3.4. These values are determined in a way to have the least delay with burning a reasonable amount of current. Transient simulation result for this circuit is shown if figure 3.15. As

Table 3.4: Transistors sizes for the LO multiplexer and buffer circuit

M1−4 M5,6 M7 M8 W L 25µ 60n 20µ 60n 60µ 200n 20µ 200n

expected, the output waveform contains both LOI and LOQ signals. The output

(47)

3.5. MIXER 37 50 51 52 53 54 55 56 57 58 0.5 1 1.5 LOp 50 51 52 53 54 55 56 57 58 0.5 1 1.5 Time(ns) LO N

Figure 3.15: Multiplexed LO waveforms

3.5 Mixer

The mixer circuit is responsible for frequency translation in the receiver chain. In CMOS technology, it is possible to design active [3,25,26] or passive mixers. Active mixers produce gain when doing the down-conversion. On the other hand, the active mixers are more complex and generate more noise than their passive counterparts. Also matching is very important in active mixers [27]. In [28] the authors give a comparison between active and passive mixers. In order to find the proper mixer circuit for this project, both types of mixers have been designed and tested. In the final version of our receiver circuit the passive mixer showed better performance and we will just focus on describing the design of passive mixer.

3.5.1 Passive Mixer Design

A passive mixer is basically formed by four CMOS switches. The signal path for a passive mixer is shown in figure 3.16. LO signals determine which RF signal should pass to the output.

Output is the down-converted signal which is denoted by IF. IF is a differential signal in which, IF+ _{and IF}− _{are given by following equations:}

IF+= RF+.LO++ RF−.LO− (3.3)

IF−= RF+.LO−+ RF−.LO+ (3.4)

Transistors in the passive mixer should be fast switches which pass the RF signal with minimum losses. The RF signal is provided by the LNA. In our design the received RF signal is converted to current in the LNA and hence the RF input of passive mixer in figure 3.16 is a current. Sizing of M1−4is done by considering sev-eral factors. One is to make the switches large to reduce their channel resistance or

rDS. Another consideration is to maintain the switching speed, which drops by the

+

LO

_

RF

+

RF

_

IF

+

IF

_

Figure 3.16: Signal path for the passive mixer between large size or low rDS and small size or higher speed.

Another issue in passive mixer design is noise. There are three different sources of noise in a passive mixer [29].These noises can be reduced by a careful design. Simulations show that the best performance is achieved using the minimum length

L = 60nm and W = 30µm. The output capacitor Cm is added to filter out high

frequency components at the mixer output [30]. To have a proper filtration, the value of Cm should be large. Low pass filtering property of the passive mixer is due

to the channel resistance and the output capacitor. In our circuit with Cm= 5pF ,

there is a pole at around 200 MHz, which helps to filter high frequency components of the output signal.

Drain and source terminals of a CMOS are identical, while for some layout con-siderations we have put the drain terminal at the RF input side. Also it should be mentioned that the mixer is decoupled from its input signal by a decoupling capacitor. Additionally, transistor operate in either off or deep triode region and in the ideal case VDS = 0 [31].

3.5.2 Biasing

DC biasing of the LO port is needed to use the full swing of the LO signal in switching. Bias components are added to the mixer core and the complete passive mixer circuit is shown in figure 3.17.

(49)

+

LO

_

RF

+

RF

_

IF

+

IF

_

Value(dB) -4.3 -1.2

For linearity analysis, several simulations like QPSS and QPAC are carried out. 1-dB compression point and input referred interception point of the designed passive mixer are reported in table 3.5.

3.5.3 Simulation Results

(50)

figure 3.18b. As it can be seen in the figure the maximum voltage is centered at 10 MHz. 1 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 −0.8 −0.6 −0.4 −0.2 0 0.2 0.4 0.6 0.8 Time(μ s) Output(mV) (a) 5 10 15 20 25 30 35 −115 −110 −105 −100 −95 −90 −85 −80 −75 −70 −65 f(MHz) Mixer Output(dB) (b)

Figure 3.18: Mixer output for fRF = 1.01GHz and fLO = 1GHz; (a) time domain,

(51)

3.6. BASEBAND AMPLIFIER AND OUTPUT BUFFER 41

3.6 Baseband Amplifier and Output Buffer

The final blocks in our receiver front-end are the baseband amplifiers. There are two baseband amplifiers. Each channel has its own amplifier. The reasons to put this amplifier are to amplify the baseband signal and to filter unwanted high frequency signals in the output data. The inverter based amplifier, can be used as the baseband amplifier.

3.6.1 Inverter Based Amplifier

+

I

_

Out+

_

Figure 3.19: Signal path of the differential inverter based amplifier

(52)

in-42 CHAPTER 3. CIRCUIT DESIGN

creased by increasing the width of transistors, while Rds is increased by increasing

the length of transistors. The transistor dimensions for circuit in figure 3.19 are

W1,2 = 165µ, W3,4 = 135µ, and L = 300n. Using these big transistors, the cor-responding ac gain is 32 dB. The ac simulation is carried out using the self-biased model for transistors.

The circuit in figure 3.19 is very sensitive to component mismatch. Any mismatch in components will lead to changes in DC operation points and consequently lead to imbalanced ac response. A CMFB circuit can be employed to solve this issue. The CMFB is responsible for sensing the DC levels at the output of inverters and set the voltage at source terminals of M3,4 in a way to balance the DC operating points.

The baseband amplifier is the final block in the receiver front-end. Thus, this cir-cuit provides the output for measurement. In order to have a correct measurement and an isolation between the measurement device and the amplifier, a buffer circuit with 50Ω output matching is required. A simple way to have an output matched buffer is to use a source follower stage at the output of the amplifier. To complete the circuit for baseband amplification and output buffer, the DC biasing, CMFB, and source follower circuits are added to the core inverter circuit. The completed baseband amplifier and output buffer circuit is shown in figure 3.20.

VDD VDD M12 M8 M1 M2 M3 M4 M5 M6 M7 M9 M10 _M 11

I

Bias VDD

I

+

I

_

Out

+

_

RF RF Rout Rout

(53)

3.7. COMPLETE RECEIVER CIRCUIT SIMULATIONS 43

After adding the source follower stage, ac gain drops around 5dB, while this stage provides maximum power transfer to the measurement device. Simulation result for the ac response is shown in figure 3.21. The baseband ac gain is 27.7 dB and the corner frequency is 30 MHz. 100 102 104 106 108 1010 −30 −20 −10 0 10 20 30 F(Hz) Voltage Gain (dB)

Figure 3.21: ac response of the baseband amplifier and buffer

The largest current in this circuit flows through the source follower stages. To have a large gm for M6,7, drain current of these transistors are set to 2.1mA. Power consumption of the baseband amplifier and buffer is summarized in table 3.6.

Table 3.6: Power consumption in baseband amplifier and buffer

Circuit Power(mW)

Inverter amplifier 1.96 Output buffers 5.04

total 7

3.7 Complete Receiver Circuit Simulations

(54)

input for the receiver front-end is the LO signal, which is provided by port blocks in the Cadence. The output of the baseband amplifiers are digitized by measurement tools. The reason is that the digital output can be readily compared with the digital input to test the correctness of receiving action. In our transient simulation, the bandwidth of input data for I and Q channels are set to 1MHz and 800KHz, respectively. Data signals are modulated by a 1GHz signal. The RF signal from the transmitter is fed to the receiver. In order to down-convert the RF signal to baseband and zero-IF, a 2GHz pulse generator is used. The 2GHz LO signal is connected to the frequency divider chain. The multiplexed LO signal is generated using the outputs of the divider circuit. As discussed earlier and shown on figure 3.11 frequency of outputs of the first and third divider are 1GHz and 250MHz. One of the main concerns in today’s IC design is the power consumption. However in this project the primary goal was to test the proposed architecture.As a result, the power performance of our circuit may not be comparable to other similar works. Amount of consumed power in all sub-circuits and the overall power consumption are reported in table 3.7.

Table 3.7: Power consumption in the single mixer multiplexed LO receiver

Circuit Power(mW) LNA 2.64 Frequency divider 18.72 LO MUX 2.76 BB amplifiers 14 Total 38.12

(55)

3.7. COMPLETE RECEIVER CIRCUIT SIMULATIONS 45 15 20 25 30 −1 0 1 2 3 Time(μ s) (mV) −−− in ___ out (a) 15 20 25 30 −1 0 1 2 3 4 Time(μ s) (mV) −−− in ___ out (b)

Figure 3.22: Input data and analog output signal; (a) I channel, (b)Q channel

15 20 25 30 0 0.5 1 1.5 Time(μ s) (V) −−− in ___ out (a) 15 20 25 30 0 0.5 1 1.5 Time(μ s) (V) −−− in ___ out (b)

(56)

(57)

Chapter 4

Floorplaning and Layout

Last step in the top-bottom receiver design is to layout the circuits. There are many important rules in doing the layout that affect the performance of the chip.

In the first section of this chapter, floorplan of the entire chip is presented. In the second section, layout considerations for a single MOSFET transistor are studied and also a brief insight to the physical properties of the used technology is provided. Finally, the layout of frequncy divider chain is presented.

4.1 Floorplaning

In floorplaning, position and orientation of each block is decided. By drawing a floorplan, an entire view of chip is obtained before doing the layout. In other words, floorplaning can be considered as a high level step in doing layout.

The receiver front-end chip has three inputs and two outputs. The inputs are RF signal, LO signal, and DC voltage. The outputs for a quadrature receiver are I and Q data signals. To handle these sets of inputs and output in the best possible way, each of them should be connected to different sides of the chip. The floorplan of our receiver is depicted in figure 4.1.

The RF signal which is fed from the left side of the chip should be connected to the LNA and then the output of the LNA is connected to the mixer. The LO signal which will be generated off-chip is applied to the chip from the bottom side. It should be noted that it is recommended to allocate the high frequency signal pins to the middle pins in each side of the chip [34]. Accordingly the RF and LO inputs in our chip are placed in the middle of left and bottom sides of the chip. The LO signal then goes through a chain of dividers and a multiplexer. Outputs of the MUX circuit are connected to the mixer. A DC voltage source is connected to the biasing circuitry, which is responsible for delivering DC currents to different blocks of the circuit. As mentioned in previous chapters, the function of DEMUX block is to separate I and Q outputs. Like the MUX block, the DEMUX block is driven by the output of the third divider. After separating the output signals, baseband amplifiers are placed to amplify and filter the outputs. The BB amplifiers

(58)

48 CHAPTER 4. FLOORPLANING AND LAYOUT

LNA

M

U

X

Div.3

Div.2

Div.1

D

E

M

U

X

Bias

BB

Amp.

BB

Amp.

RF

DC

I

Q

LO

Figure 4.1: Floorplan of the multiplexed LO single mixer receiver chip

are identical for both channels. To have the best performance, the BB amplifiers are placed symmetrically and the routing distance between outputs of DEMUX and BB amplifiers are tried to be equal. At the output side, the I and Q outputs are placed on the right side of the chip.

4.2 Layout

(59)

4.2. LAYOUT 49

4.2.1 Components Layout

In our circuit, the most complex component is the MOS transistor. The layout for a CMOS is generated automatically, while some of its features can be modified to have the best performance. In circuit level design, it is possible to choose the number of fingers (NF)=1. However, in the layout phase there are a few rules to have a reliable and layout for a transistor. One of them is to use transistors with multiple fingers. Multiple finger transistors have two advantages over single finger transistors. The first advantage is the reduction of gate resistance [35]. For example, consider a transistor with six fingers as shown in figure 4.2. This transistor has three drain

S

D

G

B

Figure 4.2: Layout of a triple well transistor with six fingers

and four source areas. One of the primary concerns in layout of transistors is the maximum current density that the metals of drain and source can tolerate. These metals are the lowest level metals or metal 1. Current density for different materials of a process can usually be found in the supporting documents of the design kit. For instance for metal 1 the current density is 1.9 mA

µm. Now assume that the transistor

shown in figure 4.2 is in a path that must carry 3 mA. Therefore each branch of the drain of this transistor must be able to handle at least I = 1mA. This means that with current density of 1.9 mA

µm, the width of each metal finger of the drain must be

520 nm. The maximum width of drain or source metals is defined for the process under use. There is another way of making the drain or source metals capable of driving high currents. Instead of widening the metals, a stack of multiple layers of metals can be used. This modification on the transistor layout is illustrated in figure 4.3. It is shown that three extra metal layers are added to the top of metal 1 to make a stronger drain or source metal finger, that can tolerate higher current values.

(60)

50 CHAPTER 4. FLOORPLANING AND LAYOUT

S

G

D

p-sub.

n

+

_n

+

Figure 4.3: Cross-sectional view of NMOS with extra metal layers in drain and source connections

device that is used in the circuit is the capacitor. In this chip capacitors are mostly used for decoupling some circuits and for power and ground decoupling. Also in the mixer the output capacitor is used to form a low-pass filter. These capacitors are metal insulator metal (MIM) capacitors and MOS capacitors. The MIM capacitors are accurate capacitors, but consume a large area. On the other hand, the MOS capacitors are not accurate but take less area. As a result the MIM capacitors are a good choice for the capacitors that their values are important like the mixer capacitor, and MOS capacitors can be used as decoupling capacitors [36,37].

4.2.2 Circuits Layout

All of the circuits that are shown in the floorplan in figure 4.1 should be laid out. There are some general rules and tips for RF and analog layout which can be found in [36, 38]. One of the most important points in the layout of the chip is the choice of metal layers for different signals. For instance it is recommended to select metal 1 and metal 2 for ground and VDD paths. Also in order to minimize

the parasitics it is better to use the top metals for input and output signals. In the layout and especially for RF applications the parasitics should be kept as small as possible. In addition to the general rules, each circuit block has some specific layout considerations which are discussed in [2]. In this report we will only present the layout of the frequency divider which operates with the highest frequency in the whole receiver and its layout can be the most challenging one.

The divider chain consists of six CML latch circuits and three buffers. First we will focus on the layout of the latch circuit, then forming the flip flop circuit with two latches, after that the layout for the buffer circuit is shown. At the end the layout of the completed frequency divider chain is shown.

Design of Multiplexed LO Single Mixer Receiver Front-End