Design of Building Blocks in Digital Baseband Transceivers for Body-Coupled Communication

(1)

Institutionen för systemteknik

Department of Electrical Engineering

(ISY)

Examensarbete

Design of Building Blocks in Digital Baseband Transceivers

for Body-Coupled Communication

Master Thesis Report

by

Rahman Ali

LiTH-ISY-EX--12/4648--SE

Linköping 2014

Department of Electrical

Engineering Linköping University

SE-581 83 Linköping, Sweden

Linköpings tekniska högskola

Institutionen för systemteknik

SE-581 83 Linköping

(2)

No Rev Date Repo Page

Title ID

Design of Building Blocks in Digital Baseband Transceivers

for Body-Coupled Communication

Master Thesis Report

by

Rahman Ali

LiTH-ISY-EX--12/4648--SE

Supervisor: Muhammad Irfan Kazim

Examiner: Dr. J Jacob Wikner

(3)

Abstract

Advances in communication technologies continue to increase information sharing among the people. Short-range wireless networking technologies such as Bluetooth or ZigBee, which are mainly used for data transfer over short range, will, however, suffer from network congestion, high power consump-tion and security issues in the future.

The body-coupled communication (BCC), a futuristic short-range wireless technology, uses the human body as a transmission medium. In BBC chan-nel, a small electric field is induced onto the human body which enables the propagation of a signal between communication devices that are in the proximity or direct contact with the human body. The direct baseband transmission and simple architecture make BCC an attractive candidate for a future short-range wireless communication technology in particular appli-cations such as body area network.

The main focus of this thesis is on the design and implementation of digi-tal baseband transmitter and receiver for the body-coupled communication. The physical layer (PHY) implementation of the digital baseband trans-mitter and receiver is inspired from the IEEE 802.3 Ethernet transmission protocol. The digital design is implemented at RTL level using hardware de-scription language (VHDL). The functionality of the digital baseband trans-mitter and receiver is demonstrated by developing data transfer application layers.

(4)

Acknowledgment

First of all I would like to thank Almighty Allah, who enabled me to carry out this work.

I would like to thank my examiner Jacob Wikner, for his kind guidance and support throughout the work. I would also like to thank my thesis su-pervisor Muhammad Irfan Kazim for his kind supervision. I would also like to thank, Ghafoor Shah for his help and guidance.

Last but not the least, I want to thank my family and friends for their support and prayers.

(5)

4 Digital Baseband Transmitter and Receiver Architectures 18 4.1 Introduction . . . 18 4.2 Transmitter architecture . . . 18 4.2.1 Interface . . . 19 4.2.2 Algorithm . . . 19 4.2.3 Design . . . 19 4.2.4 Simulation . . . 22 4.3 Receiver architecture . . . 23 4.3.1 Interface . . . 23 4.3.2 Algorithm . . . 23 4.3.3 Design . . . 25 4.3.4 Simulation . . . 27 4.4 CSMA/CA . . . 27 4.5 Summary . . . 28

5 BAN PHY–Simulation Results and Timing Diagrams 32 5.1 Introduction . . . 32

5.2 Test bench . . . 32

5.2.1 Test clock module . . . 32

5.2.2 APP transceiver 1 . . . 33 5.2.3 APP transceiver 2 . . . 33 5.2.4 APP transceiver 3 . . . 33 5.3 Simulation results . . . 33 5.4 Conclusion . . . 35 6 FPGA Demonstrations 41 6.1 Introduction . . . 41 6.2 Application Layers . . . 41

6.2.1 Data transfer application layer . . . 41

6.2.2 Data display application layer . . . 41

6.3 Quartus II Project . . . 42

6.4 DE2-115 Board Setup . . . 42

6.5 Channel evaluations . . . 43

6.6 Challenges . . . 43

6.7 Conclusion . . . 45

7 Project Conclusions 46 7.1 Conclusions . . . 46

7.2 Future research Works . . . 47

(7)

Contents

Bibliography 48

A Testbench module 52

A.1 Introduction . . . 52

A.2 VHDL code . . . 52

A.3 Instances of the transceiver . . . 54

A.3.1 Transceiver 1 . . . 54

A.4 Test clock module . . . 57

A.5 Test stimuli . . . 58

B Transceiver module 61 B.1 Introduction . . . 61 B.2 VHDL code . . . 61 C Transmitter module 66 C.1 Introduction . . . 66 C.2 VHDL code . . . 66

C.2.1 To receive data input through clk8 . . . 68

C.3 FSM of the transmitter . . . 68

C.3.1 Preamble generator and logical control . . . 69

C.3.2 Copying data into memory . . . 70

C.3.3 Parallel input serial output . . . 72

C.3.4 Multiplexer . . . 72 C.3.5 CRC calculation . . . 73 C.3.6 Manchester encoder . . . 74 D Receiver module 76 D.1 Introduction . . . 76 D.2 VHDL code . . . 76

D.3 Receiver clock recovery . . . 76

D.3.1 Edges detection . . . 77

D.3.2 Clock Recovery . . . 78

D.3.3 Resetting central transition counter . . . 79

D.3.4 Synchronization process . . . 80

D.3.5 Manchester Decoder . . . 80

D.4 FSM of the receiver module . . . 83

D.4.1 Preamble detection . . . 84

D.4.2 Start of frame(SOF) delimiter . . . 85

D.4.3 Calculate lenngth of the packet . . . 85

D.4.4 Store the data packet into memory . . . 86

(8)

List of Figures

1.1 Demonstration of human body communication technology

(Con-nected Me) at the International Consumer Electronics Show

(CES) 2012 [5]. . . 2

1.2 Coupler used for capacitive and galvanic coupling where (a)

shows the vertical structure and (b) illustrates the horizontal

structure. . . 4

1.3 Structures of horizontal couplers with (a) transversal

orien-tation and (b) longitudinal orienorien-tation. . . 5

1.4 BCC illustration with galvanic coupling interface. . . 5

3.1 Example of a capacitive coupling scenario with the human

body acting as a communication channel [36]. . . 12

3.2 A block diagram showing the architecture of BCC transceiver. 13

3.3 A block diagram showing different parts of the digital

base-band transceiver . . . 14

3.4 IEEE 802.3 Ethernet PHY frame format . . . 15

3.5 Graphical illustration of the Manchester encoder . . . 16

3.6 Adopted PHY frame format for the BAN discussed in this

thesis. . . 16

4.1 Transmitter PHY module: (a) shows block diagram and (b)

shows simulation waveforms of the transmitter PHY module. 20

4.2 State transition diagram of the transmitter FSM. . . 21

4.3 Illustration of the Manchester encoder. . . 22

4.4 Transmitter PHY frame format. . . 23

4.5 Illustration of clock recovery module: (a) shows block

dia-gram and (b) shows simulation waveforms. . . 25

4.6 State transition diagram of the receiver FSM. . . 26

4.7 Illustration of receiver PHY: (a) shows a block level diagram

of receiver PHY and (b) shows various simulation waveforms. 29

(9)

List of Figures

4.9 A block diagram showing the different modules of the

digi-tal baseband transceiver along with the application layer and

analog front end (AFE). . . 31

5.1 Elaboration of the testbench developed for design

verifica-tions. Three instances of the transceiver are used, which rep-resent three different transceivers, forming a small network. On the one side each transceiver is connected with a separate application layer, while, on the other side, all transceivers are

connected with each other, realizing a BAN network. . . 34

5.2 Different waveforms along the transmitted and received path. 35

5.3 The simulation diagram illustrates the behaviors of various

test clocks used for simulations. The signals clk1 and clk2 show slow clocks used for transmitter PHY. It is also shown in the graph that the clk1 and clk2 have different delays and different edges while their clock period is the same. Similarly, signals rx clk1 and rx clk2 show the faster clock used for

receiver clock recovery module. . . 36

5.4 A detailed simulation graph showing data transfer within the

network of three transceivers, where transceiver 1 sends data

to transceiver 2 and transceiver 2 sends data to transceiver 1. 36

5.5 This simulation graph shows various signals and buses of

the transmitter PHY. The final transmitter output is shown

through the signal tx out. . . 37

5.6 This simulation graph shows various signals and buses of the

receiver PHY. The receiver input is shown through signal rx in. The recovered clock is shown through signal clk recovered. The faster receiver internal clock is shown through signal clk.

The final decoded output is shown through signal rx out. . . 38

5.7 This simulation graph shows FSM of the receiver PHY. Upon

receiving the input on signal rx in, the different states of FSM of the receiver PHY is shown through various signal and buses. The signal rx busy shows the busy state of the receiver PHY. The other important signals recovered clock, and final receiver output are shown though signals clk recovered and

rx out. . . 39

5.8 The simulation graph shows the necessary signals of receiver

clock recovery module. For oversampling, an eight times

faster clock shown through signal clk is used. The various edge detectors signals are shown through pos edge, neg edge and pn edge. The final recovered clock is shown though signal

(10)

List of Figures

6.1 A block diagram illustrating the FPGA board setup for

demon-strating the functionality of the designed transceiver PHY layer. 42

6.2 Transmitter output on the oscilloscope for the FPGA based

implementation. . . 43

6.3 A zoomed graph of the transmitter output implemented in

FPGA. . . 44

6.4 Transmitter output of the FPGA based implementation shown

on the oscilloscope. . . 44

(11)

List of Tables

3.1 Important and relevant features of the IEEE 802.3 Ethernet

(12)

List of Abbreviations

1G First Generation 2G Second Generation ACK Acknowlegement AFE Analog Front End APP Application Layer BAN Body Area Network

CES Consumer Electronics Show CRC Cyclic Redundancy Check

CSMA/CA Carrier Sense Multiple Access/Collision Avoidance DBB Digital Baseband

DFF Data Flip Flop DR Data Register DUT Device Under Test EOP End Of Packet

FCS Frame Check Sequence

FPGA Field Programmable Gate array FSM Finite State Machine

GPIO General Purpose Input Output HBC Human Body Communication IC Integrated Circuit

IEEE Institute of Electrical and Electronics Engineering LAN Local Area Network

LFSR Linear Feedback Shift Register NFC Near Field Communication PDA Personal Digital Assistant PHY Physical Layer

PLL Phase Lock Loop RAM Random Access Memory RFID Radio Frequency Identification

RX Receiver

SOF Start Of Fram delimiter SOP Start Of Packet

SW Software

TCK Test Clock TRX Transceiver

TX Transmitter

(13)

Chapter 1 Introduction

1.1 Overview of the Project

Information sharing using different devices, e.g., mobile phones, personal digital assistants (PDAs), laptops, etc., has increased the demand for short-range wireless networking. Consequently, various short-short-range wireless net-working technologies such as wireless fidelity (WiFi), Bluetooth, ZigBee, radio frequency identification (RFID), etc., have been introduced recently. Any wireless technology can be characterized by the following important fac-tors: 1) network congestion; 2) security, and 3) power consumptions. Many solutions have been proposed in the research literature in order to improve the aforementioned factors of the existing wireless networking technologies [1]. However, all the mentioned wireless networking technologies suffer from the high power consumption mainly because they all use a high-frequency carrier for transmission over the air, which is a power-hungry operation. The use of a high-frequency carrier for transmission also makes these tech-nologies prone to possible eavesdropping, raising security issues. The third and most important challenge in the existing wireless technologies is the bandwidth issue, which can cause network congestion in certain scenarios. To compliment the existing short-range wireless communication technologies in certain applications such as body area network, a novel communication system was introduced in [2], which proposed the human body as a trans-mission medium. In [2], a small electric field was induced onto the human body which enabled the propagation of a signal between communication de-vices that were in the proximity of, or in direct contact with, the human body. The body-coupled communication (BCC) system uses direct base-band transmission which is more power efficient as compared to existing short range technologies which use the high-frequency carrier transmission over the air. Eavesdropping can also be avoided as the BCC system does not need a high-frequency carrier for transmission over the air. Therefore, the BCC is considered as an important futuristic short range wireless

(14)

com-Chapter 1. Introduction

munication technology in such applications such as body area network. This thesis is a part of the research project Transceivers for Body Area Network communication. Transceivers for body area network (BAN) com-munication use the human body as a transmission medium for data transfer between different devices. This thesis discusses the design and implemen-tation of the physical layer (PHY) of digital baseband transceivers of BAN

communication project. The transceiver for BAN communication is

be-ing developed by the Electronic Systems research group at the department

of Electrical Engineering, Link¨oping University, Sweden. Transceivers for

the BAN communication project is the continuation of the Connected ME Project previously developed by the same research group for Ericsson Swe-den. Connected ME was demonstrated by Ericsson Sweden at the Consumer Electronics Show (CES) held at Las Vegas Jan 2012 [5]. The human body

Figure 1.1: Demonstration of human body communication technology (Con-nected Me) at the International Consumer Electronics Show (CES) 2012 [5]. can act like a “conductor” to transmit digital data from a mobile phone to a TV screen as shown at CES 2012 in Figure 1.1. Transceivers for BCC communication exploit the capacitive coupling interface of the human body communication. Capacitive coupling is the transfer of energy within the cir-cuit nodes by means of capacitance in between [6]. The BCC is an attractive candidate for short-range wireless communication technology.

(15)

Chapter 1. Introduction

1.2 Near Field Communications

The Near Field Communication (NFC) is a short-range wireless communica-tion technology [7]. The NFC allows communicacommunica-tion to take place between devices that either touch each other or held together firmly. Traditionally the NFC technology operates on an unlicensed radio frequency band which works on the principles of magnetic field induction. The NFC is a part of the Radio Frequency Identification (RFID) standard. The NFC is like an open platform technology and is defined by the standard ISO/IEC 18092 [9]. The NFC technology is growing continuously in conjunction with mobile phones; it explores applications in many areas of life.

1.2.1 Importance of NFC

There are several reasons that have made the NFC an important technol-ogy. The NFC integration in mobile phones gives this technology a potential global reach. The NFC technology is compatible with the existing contact-less infrastructure. The inherent security in NFC, which require users to hold their mobile devices actively against other devices, makes NFC an at-tractive technology. The NFC provides countless value-added services and offers tremendous potential as it can be used in many different ways to make our daily life comfortable. Some of the important applications of NFC are given below.

The NFC employed in mobile phones can be used for identification pur-poses. For instance, student IDs stored on mobile phones equipped with NFC allows the students to open doors, borrow library books or receive discounts on purchases [8]. Also, fast and secure purchases can be made through mobile phones equipped with NFC [8]. Information transfer like downloading a movie trailer or a map from tagged objects [8] are some of the attractive applications of NFC. In short, a large number of interesting and essential daily life applications are becoming a reality with the use of NFC technology.

1.3 Body-Coupled Communication

In the BBC technology, the human body is used as a communication chan-nel. The basic concept of BCC is that a small electric field is induced onto the human body which enables the propagation of a signal between com-munication devices that are in the proximity of, or in direct contact with the human body. In order to induce the electrical signal onto the body, two conceptually different approaches have been previously proposed; 1) capacitive coupling and 2) galvanic coupling. These coupling approaches are further explained in Sections 1.3.1 and 1.3.2. For both approaches, the

(16)

BCC transceiver consists of a transmitter (TX) and receiver (RX), together connected to the coupler. Each coupler is composed of two electrodes. In galvanic coupling approach, both transmitter and receiver electrodes must be placed on the skin directly. While, in capacitive coupling method, direct human skin contact is not necessary, however, proximity of the coupler elec-trodes to the body is needed. These coupler elecelec-trodes can be structured vertically or horizontally. A dielectric material fills the spacing between the coupler electrodes. The horizontally and vertically structured coupler elec-trodes are shown in the Figure 1.2. The vertical structure is only used for the capacitive coupling approach, where as the horizontal structure can be used for both approaches. In the horizontal structure, the coupler electrodes can be oriented on the body in a longitudinal or transversal direction as can be seen in the Figure 1.3.

1.3.1 Galvanic coupling

The galvanic coupling approach is depicted in the Figure 1.4. At the TX node an electrical signal is applied differentially between two electrodes that are directly connected to the human body, which results in the flow of cur-rent between these two electrodes. The electric curcur-rent between the two electrodes (primary current) also induces a very small (secondary) electric current to propagate into the conductive body tissues. At the RX node, there are also two electrodes attached to the body. The induced current results in a differential signal between these two electrodes. The galvanic coupling approach makes use of the dielectric characteristics of human tissue, and the flow of ions within the human body acts as a carrier of information. In this approach, the human body serves as a kind of transmission line [11].

Figure 1.2: Coupler used for capacitive and galvanic coupling where (a) shows the vertical structure and (b) illustrates the horizontal structure.

1.3.2 Capacitive coupling

In capacitive coupling, a differential pair of coupler electrodes is used both at transmitting and receiving nodes. At the TX node, a signal is applied

(17)

between the electrodes and since the electrodes have a different capacitive coupling to the body, an electric field is induced to the human body and passes through the body over the skin. At the RX node, the two electrodes are at different distances from the body, so it is possible to detect a differ-ential signal between them as a function of the varying electric potdiffer-ential of a person. In the capacitive coupling approach, the human body acts as a conductor that forms a bridge between the TX and RX that are capacitively coupled to it. The environment is used as a reference to force or detect a variation of the electric potential of the human body. In this approach, the electric signal flows over the surface of the human body.

Figure 1.3: Structures of horizontal couplers with (a) transversal orientation and (b) longitudinal orientation.

Figure 1.4: BCC illustration with galvanic coupling interface.

1.3.3 Comparison of galvanic and capacitive coupling

Both approaches have their respective pros and cons from a technical as well as an application perspective. From the technical point of view, an essential difference between the two approaches is that the communication behavior in the galvanic coupling approach is profoundly influenced by the body physical parameters while, in the capacitive coupling approach, it is more influenced by the environment around the body. From the application

(18)

perspective, a significant difference between the two methods is that the galvanic coupling method requires a direct contact between the coupler and the human body, which is not needed in capacitive coupling approach. That is the reason that makes the capacitive approach more flexible hence we focus here on this approach.

1.4 BAN-Body Area Network

Advancements in the fields of low power integrated circuits technology, wire-less communications and physiological sensors have given birth to a new wireless sensor network called the body area network. A body area network (BAN) forms a communication network between various devices attached to the human body [12]. A BAN can be used for different applications. An important application of the BAN is in the health monitoring systems. The physiological sensors attached to different parts of the body used for health monitoring use BAN for internal communication [13]. A similar kind of BAN called Transceivers for BAN Communication project is being

de-veloped at the Electronics Systems research group at Link¨oping University

Sweden. This BAN uses human body communication with capacitive cou-pling interface. The following section defines the problem addressed in this thesis report.

1.5 Thesis problem

This thesis focuses on the design and implementation of the physical layer (PHY) of digital baseband transceiver for the BCC. A digital baseband transceiver consists of two parts; 1) a digital baseband transmitter and 2) a digital baseband receiver. The digital baseband transmitter takes data from an application layer, converts the data into a format suitable for transmis-sion over the human body, and gives it to analog front end (AFE) of the transmitter. The digital baseband receiver takes serial data from AFE of the receiver, recovers the data and passes the received data to the application layer. Further, to make the system full duplex, a suitable medium access control technique such as the classical carrier sense multiple access/collision avoidance (CSMA/CA) also needs to be implemented in the framework of this thesis.

1.6 Report outline

This report is structured as follows:

Chapter 2 gives a short review of the BCC literature. Chapter 3 outlines a general architecture of transceivers for the BCC and also describes the

(19)

fundamentals of the physical layer implementation protocols for the BCC transceivers. Chapter 4 explains the hardware design and implementa-tion of the PHY of the baseband BCC transceivers. The simulaimplementa-tion test bench and simulation graphs of the PHY of the baseband BCC transceivers are discussed in Chapter 5 . The demonstration of the baseband BCC transceivers on FPGA board is given in Chapter 6, while conclusions and future works are discussed in Chapter 7.

(20)

Chapter 2 BCC Literature Review

This chapter discusses a short literature review of the body-coupled com-munication (BCC) systems.

2.1 Introduction

Various studies have been carried out in the research literature to charac-terize BCC and to model its channel. The various existing studies have proposed different coupling schemes, data rates, signal strengths, frequency ranges, body channel modeling schemes and signal modulation techniques. Some of the important studies in the literature reviewed are the following:

2.1.1 Zimmerman

Zimmerman [3], in 1995 discovered the concept of human body communi-cation for the first time. In his study, the capacitive coupling approach was adopted, and the communication system consisted of a TX and an RX which were electrically isolated from each other. Data signal was transmitted by capacitively coupling a small current to the body. The human body con-ducts the small signal because of the body electrical field. A single-ended connection was used, where the environment provided the return path. It had been shown through experiments that placing a large area environment electrode close to the physical ground maximizes the magnitude of the

re-ceived signal. Moreover, two coding and modulations techniques, on-off

keying (OOK) and direct sequence spread spectrum (DSSS) had also been investigated. The OOK modulation was used because of its much simpler implementation. In the first ever HBC system, data rate of 2.4 Kbps was achieved using a carrier frequency of 333 kHz [3].

(21)

Chapter 2. BCC Literature Review

2.1.2 Fuji et al

The main focus in the study [14, 15, 16, 17], was on higher carrier frequencies, where the authors claimed that the body channel acts as a waveguide for frequencies between 10 MHz and 100 MHz. In this study, capacitive coupling interface was used. The authors have proposed calculation models of the HBC communication system using finite-difference time-domain (FDTD). In their experiments, the difference in the received signal strength as a function of the carrier frequency was investigated for different TX and RX electrode structures. In finding the optimal electrode orientation for the horizontal structure, longitudinal and transverse orientations for TX electrodes had been examined. The distance between the TX and RX was fixed during all the experiments. The good agreement between the computed and measured

signal strength had been shown through experiments. It had also been

shown that the received signal strength strongly depends on the size of the transmitter electrodes i.e. if the size of the TX electrode is halved; the signal strength is decreased by nearly 50%. A decrease in the strength of the received signal for higher carrier frequencies was also noted.

2.1.3 Yanagida

An HBC communication system with relatively high rate and low power consumption was claimed in [18]. The capacitive coupling approach was adopted in this study. A suitable transmission band with the proper con-figuration of the TX and RX electrodes was selected through different ex-periments. It had been shown that lowest transmission loss can be achieved with the vertical structure of the transmission electrodes. It had also been shown through experiments that the electric capacity of capacitive coupling was proportional to the area of the transmission electrodes. In other words, direct proportionality between the transmission range and the size of trans-mission electrodes was observed. An inverse proportionality of the electric capacity and the distance between the transmission electrodes had also been investigated. The frequency band of 500 kHz to 3 MHz was claimed to be the optimum for a good quality communication system.

2.1.4 Ruiz et al

In [19, 20, 21, 22], the propagation characteristics of the human body for higher frequency have been investigated. In these studies, the human body was considered as a waveguide with the RF signal propagating through the body. Interesting investigations have been done considering different configurations for TX and RX. In the measurement setup, 12 dBm TX signal was coupled onto the body via a coupler. The received signal at the RX node was measured by a spectrum analyzer. Various experiments were carried out using vertical electrodes in different sizes and locations on the

(22)

body. In these experiments, the signal electrode area was much smaller than the ground electrode area. The separation distance between these two electrodes was varied from 0.7 cm to 2.1 cm. Different scenarios, where the subject was sitting, standing and walking were considered for measurements. In this study it was concluded that the received signal power decreases when the frequency increases. The measurements carried out for sitting and standing tests were almost same. It has been observed that a higher quality HBC link was achieved when the subject was stationary. Moreover, in their experimental study, they have also compared the human body and air channel, where a lower propagation loss for the intra-body channel than for the air channel was observed. On the basis of the lowest path loss, the frequency range of 200 MHz to 600 MHz was claimed to be suitable for HBC. In these studies, a few digital modulation techniques have been evaluated, in order to determine the most suitable one for HBC. Their results showed that BPSK and MSK were the most suitable modulation schemes for HBC. However, a significant signal distortion was noted with an increase of symbol rate and distance between TX and RX for all modulation schemes.

2.1.5 Choi et al

Several aspects of HBC were studied in [23, 24, 25, 26, 27, 28, 29, 30]. To achieve low power consumption and high data rate, wide band transceiver with a direct-coupled interface (DCI) has been adopted for HBC. At the TX node, a single electrode was used to transmit the data to the body. At the RX side, a single electrode was connected to a digital oscilloscope, and its ground was floated to isolate it from the signal ground of the TX. This transceiver architecture without any modulation was not suitable for a shared body channel, which has been modified to a scalable PHY transceiver. The PHY transceiver used the DSSS for narrowband interference rejection. The 1 bit ADC used in this design could not provide sufficient dynamic range to cancel various interferences. Therefore, the authors came up with a solution; divide the operation frequency band to four sub-bands and make use of adaptive frequency hopping (AFH). With each sub-band, a 10 Mbps FSK signal was used. In their experiments, they showed that the AFH could improve the signal to interference ratio (SIR) of the HBC system by more than 10 dB. Moreover, an RC model of a T-shaped human subject has been developed to characterize the human body as a channel for HBC. The TX in their experimental measurement setup consisted of a battery-powered signal generator with a programmable frequency synthesizer and two vertically structured electrodes. The RX consisted of a single electrode in the same shape and dimension of the TX signal electrode. The received signal was measured by connecting a spectrum analyzer to the electrode at the RX node. In this setup, the receiver shared its ground with the earth-grounded instruments which potentially resulted in an increment in

(23)

the strength of the return path. However, they claim an increment of 6 dB, and this has been considered in their analysis. In their measurements, TX output power was fixed to three dBm and the body channel was measured up to 150 MHz. They claimed that below 4 MHz, the channel was deterministic and behaved like a high-pass filter. However, beyond 10 MHz the power loss was proportional to the distance between TX and RX.

2.2 Summary of literature review

In this Chapter, we discussed some of the important studies carried out for the development of BCC communication systems. Zimmerman [3], in 1995 discovered the concept of human body communication; in the first ever BCC system he developed, data rate of 2.4 Kbps was achieved using a carrier fre-quency of 333 kHz. Different aspects of BCC such as data rate, modulation schemes, operation frequency range, etc., have been investigated thus far. However, further investigation is needed to improve the various aspects of BCC communication system to an acceptable level. In the following Chapter 3, we discuss the architecture of BCC communication system.

(24)

Chapter 3 Digital Baseband Transceiver

for BCC

3.1 Introduction

In this Chapter, we discuss the architecture of the transceivers for the BCC. The transceivers for the BCC is a full duplex communication system which uses the human body as a communication channel and exploits the capaci-tive coupling interface of the BCC. The capacitor plates are used to couple the electrical signal from the transmitter to the human body and from the human body to the receiver. Figure 3.1 shows the BCC transceivers com-municating over the human body.

Figure 3.1: Example of a capacitive coupling scenario with the human body acting as a communication channel [36].

(25)

Chapter 3. Digital Baseband Transceiver for BCC

3.2 Transceiver Architecture

A Transceiver for the BCC consists of two main modules; 1) transmitter and 2) receiver. The architecture of the BCC transceivers is briefly discussed in the followings:

From the design point of view, the BCC transceiver can be divided into two parts; 1) a digital baseband (BB) part and 2) an analog front end (AFE) [36]. Figure 3.2 shows a block level diagram of the different parts of the BCC transceiver. The main focus of this thesis is the design and implementation of the digital baseband part of the BCC transceiver. The digital baseband transceiver can be further divided into the application layer (APP) and physical layer (PHY). The PHY of the transceiver has two main

Figure 3.2: A block diagram showing the architecture of BCC transceiver. modules, denoted as transmitter PHY and receiver PHY. The APP is re-sponsible for passing data byte-by-byte from keyboard to the transmitter PHY. The APP is also responsible for displaying the data received from re-ceiver PHY through an LCD display. The transmitter PHY takes data from APP and assembles the data into a frame suitable for transmission over the human body channel. The receiver PHY unstraps the received frame from AFE and passes the data to the APP for display. Figure 3.3 shows different parts of digital baseband transceiver. The design and implementation of the PHY layer of the transceiver is further discussed in Chapter 4.

(26)

Figure 3.3: A block diagram showing different parts of the digital baseband transceiver

3.3 BCC PHY

The transmission protocol used for the implementation of the PHY of the BCC presented in this thesis is inspired from the IEEE 802.3 Ethernet trans-mission protocol. The main reason is that IEEE 802.3 Ethernet uses Manch-ester encoder as a digital modulation scheme. The ManchManch-ester encoded data can be efficiently coupled capacitively to the human body as the BCC uses capacitive coupling interface with the human body. Section 3.3.1 briefly discusses IEEE 802.3 Ethernet transmission protocol. Other competitive communication protocols are also discussed in Section 3.3.2.

3.3.1 IEEE 802.3 Ethernet

The IEEE 802.3 Ethernet is local area network (LAN) transmission pro-tocol. The IEEE 802.3 specifies the PHY and lower software layers of the open system interconnection (OSI) reference model [31]. Table 3.1 summa-rizes the PHY characteristics of the IEEE 802.3 Ethernet standard. The important properties of the IEEE 802.3 Ethernet, which inspire PHY of BCC transceivers are discussed in the following subsections.

(27)

Table 3.1: Important and relevant features of the IEEE 802.3 Ethernet transmission protocol are summarized in this Table.

Data rate SM Media Topology MSL

10 Mbps Baseband 50-ohm coax Bus 500 m

SM: Signaling method MSL: Maximum segment length

Frame format

Figure 3.4 shows the IEEE 802.3 frame format [31]. The frame starts with a 7 bytes of alternating one’s and zero’s called preamble. The preamble in-forms the receiving station about the incoming frame. This preamble is also used for clock synchronization at the receiving station. A single byte field

Figure 3.4: IEEE 802.3 Ethernet PHY frame format

following the preamble is called Start of frame (SOF) delimiter. The SOF delimiter is a similar sequence of one’s and zero’s like the preamble but the last bit is one instead.

The third field in the 802.3 Ethernet frame is a two or six bytes of des-tination address, which contains the address of the desdes-tination station. Fol-lowing the destination address field is the source address field of two or six bytes which contains the address of the transmitting station. Two bytes length field follow the source address field, which contains the length of the

payload. The sixth field in the frame is payload or data. The payload or

data field is variable in the range of 46-1500 bytes. The last field is called frame check sequence (FCS). The two or four bytes FCS field is used for channel coding [31].

Baseband modulation

The baseband modulation technique proposed in the IEEE 802.3 Ethernet is the Manchester encoding modulation [31]. The Manchester encoding is implemented by taking the exclusive OR of the serial data frame and clock signal. The transition of “high” to “low” or “low” to “high” in the middle of every encoded bit helps in receiver clock synchronization. In Manchester

(28)

en-Chapter 3. Digital Baseband Transceiver for BCC

coding, a 0 is represented by transition from zero to one and 1 is represented by transition from one to zero. Figure 3.5 demonstrates the Manchester en-coding.

Figure 3.5: Graphical illustration of the Manchester encoder

The IEEE 802.3 features namely; 1) Manchester encoding; 2) frame format, and 3) medium access control inspire the BAN PHY implementation. Fig-ure 3.6 shows the actual frame format adopted for the BAN PHY according to the requirements.

Figure 3.6: Adopted PHY frame format for the BAN discussed in this thesis.

3.3.2 Related transmission protocols

The IEEE 802.15 working group specifies the wireless personal area network (WPAN) standards [32]. There are seven task groups in IEEE 802.15. The related transmission protocols are discussed in the following:

The IEEE 802.15.1 Task Group 1 (TG1) specifies the lower transport layers of the Bluetooth wireless technology, industry specification for short-range

(29)

radio frequency based connectivity for portable devices [33]. This

stan-dard defines a low data rate up to few Mbits/s. The IEEE 802.15.3 TG3 for WPAN, defines high data rate i.e., up to 55 Mbit/s, low power and low cost solutions [34]. Another candidate for BCC PHY is TransferJet, a newly developed technology for proximity wireless transfer application [35]. TransferJet technology aims at high speed up to 560 Mbits/s data exchange between devices in close proximity of up to 3 centimeter [35].

3.4 Summary

A top level architecture of the BCC transceiver is briefly introduced here. Transceivers for the BCC is a full duplex system which consists of two parts; 1) a baseband and 2) an analog front end. The fundamentals of the PHY of the BCC are also discussed in this Chapter. The Manchester encoding (baseband modulation scheme) and the suitable data rate of the IEEE 802.3 Ethernet transmission protocol inspires the PHY implementation of the dig-ital baseband transceiver for the HBC channel. This thesis further discusses the implementation of the digital baseband transceivers for the BCC in the following Chapter 4.

(30)

Chapter 4 Digital Baseband

Transmitter and Receiver

Architectures

This chapter provides a description of the hardware model of the PHY of digital baseband transceivers for the BCC.

4.1 Introduction

The PHY of the transceiver is implemented using transmission protocols discussed in Section 3.3. The PHY of the transceiver can be divided into three modules; 1) transmitter module; 2) receiver module and 3) a logical control module. The very high speed integrated circuits hardware descrip-tion language (VHDL) is used for implementadescrip-tion. The VHDL code of the implementation is given in appendixes. The implemented design is veri-fied through simulation, using ModelSim simulation tools. The following sections further explain the implemented design.

4.2 Transmitter architecture

This section discusses the PHY of the digital baseband transmitter. The PHY of the digital baseband transmitter takes data from the application layer, assembles data into a frame discussed in Figure 3.6, and passes the serial Manchester encoded data to the AFE of the transmitter. A transmit-ter PHY frame consists of seven different fields, and the frame size varies from 15 bytes to 1039 bytes. The various fields of the transmitter PHY frame are given in the Figure 4.4. The VHDL code of the transmitter PHY is given in Appendix C. The following subsections explain the digital base-band transmitter PHY interface, algorithm, design and simulation results.

(31)

Chapter 4. Digital Baseband Transmitter and Receiver Architectures

4.2.1 Interface

The interface between the PHY and APP layers of the transmitter is defined through a handshaking protocol. During the operation, the PHY of the transmitter takes data from the APP layer of the transmitter byte-by-byte along with two single-bit handshaking signals called Start of packet (sop) and End of packet (eop). It enables the user to choose the packet length according to the operational environments. It means different packet lengths can be set for different applications. The interface between the PHY and the AFE of the transmitter is a single bit Manchester encoded data.

4.2.2 Algorithm

The operation of the baseband transmitter can be viewed as a finite state machine (FSM). The FSM of the PHY of the transmitter consists of five different states. The algorithm developed for the PHY of the transmitter is described in Algorithm 1. The various states of the FSM of the transmitter

PHY are illustrated through state transition diagram in Figure 4.2. The

Algorithm 1 Transmitter FSM

1: State0: If start transmission then go to State1 else remain in State0

2: State1: If sop then store the incoming packet, byte-by-byte in memory

as Packet. Calculate length of the Packet. If eop, then go to State2

3: State2: Preamble-array = 0xAAAAAAAB (64 bits of 10101...11. Note

that the start bit should be 1 and the last 2 bits should be 11). Manch-ester encoder is on

f or (i = 0; i ≤ 64; i + +) { Send data=Preamble-array[63-i] (sending MSB first)}, then go to State3

4: State3: Start calculation of FCS (CCIT-CRC) of the data packet.

Manchester encoder is on

f or (i = 0; i ≤length-of-packet ; i + +) { Send data=Packet[i] (sending LSB first) }, then go to State4

5: State4: Manchester encoder is on

f or (i = 0; i ≤ 15; i + +) { Send data=CRC-array[i] (sending LSB first }. Acknowledge the APP, and then go to State0

Algorithm 1 is used in the actual design of the PHY of the transmitter. The different parts of the PHY of the transmitter are explained in Section 4.2.3.

4.2.3 Design

This section explains the design of the PHY of the transmitter based on Algorithm 1, discussed in Section 4.2.2. The design can be logically divided into the following main blocks: 1) controller, 2) interface, 3) clock generator,

(32)

(a) Various parts of the transmitter module are shown in this figure.

(b) This simulation diagram shows different waveforms of transmitter module. A clock signal denoted as clk, transmitter output signal denoted as tx out, data signal denoted as s data, CRC calculation denoted as calculate crc, send CRC denoted as send crc, etc., are shown in the diagram.

Figure 4.1: Transmitter PHY module: (a) shows block diagram and (b) shows simulation waveforms of the transmitter PHY module.

(33)

Figure 4.2: State transition diagram of the transmitter FSM.

4) a packet assembler, 5) a preamble generator, 6) a CRC calculator, and 7) a Manchester encoder, as shown in Figure 4.1a. Figure 4.1b shows various waveforms of the transmitter PHY module.

Controller

This logical block is the main control unit of the design. As explained

earlier, the transmitter module of the baseband transceiver is an FSM with five different states, shown in Figure 4.2. The control module is responsible for switching between different states and facilitates the intercommunication of different submodules.

Clock generator

The PHY layer of the transmitter takes data byte-by-byte from the APP layer. The clock generator module generates a clock that is 1/8 times the transmitter clock. This slow clock is needed for taking in data from the upper (APP) layer which runs at eight time’s lower clock then the receiver. Packet assembler

This block assembles the packet into the required frame format. The packet assembler block further contains many small blocks. The incoming data from

(34)

the application layer is received byte-by-byte and stored in the memory. The handshaking signals start of packet (sop) and end of packet (eop) are used for taking data from the application layer. The length of the data packet is kept variable which varies from one byte to 1024 bytes. The packet assembler module also calculates the length of the packet.

Preamble generator

The preamble generator is a lookup table storing an eight bytes of binary data. Among the eight bytes, seven bytes are alternating ones and zeros, starting from one. The last byte is called Start of frame delimiter which contains 10101011 sequences. It should be noted that the last consecutive ones, in the last byte, indicates the end of the preamble.

CRC calculator

A cyclic redundancy check (CRC) channel coding scheme is implemented which detects one error at a time. The CRC is implemented through linear feedback shift registers (LFSR). A 16 bit polynomial generator is used, which is enough for error detection of a given frame. The polynomial expression for CRC-CCITT in given as:

f (x) = x15+ x11+ x4+ 1 (4.1)

Manchester encoder

The baseband modulation is done through the Manchester encoder. The se-rial data is the Manchester encoded (i.e., by taking exclusive OR of the sese-rial data with the clock signal). It is worth mentioning that a transition from ’1’ to ’0’ and from ’0’ to ’1’ in every encoded data bit reduces receiver desensiti-zation in case of long consecutive one’s and zero’s. The Manchester encoder also helps in receiver clock recovery. Manchester encoder implementation is illustrated in Figure 4.3.

Figure 4.3: Illustration of the Manchester encoder.

4.2.4 Simulation

The ModelSim simulation tool is used for simulations. A testbench was created for the verification of the PHY of the transmitter’s functionality.

(35)

During the simulations, the testbench generates the desired stimuli to the PHY of the transmitter. The PHY of the transmitter then outputs the required frame shown in Figure 4.4. Various waveforms of the transmit-ter PHY are shown in Figure 4.1b and Figure 5.2. Figure 5.5 shows the simulation output of the PHY of the transmitter.

Figure 4.4: Transmitter PHY frame format.

4.3 Receiver architecture

The highly distorted human body channel puts strict limitations on receiver design. The baseband receiver is implemented as a fixed data rate system in order to avoid locking to false frequency. The synchronization of PHY of the receiver is the most important part of the receiver design. The AFE restores DC levels. The packet detection is performed by checking first 16 bits of alternating ones and zeros, and start of the payload is detected by delimiter detection that are consecutive ones. The incoming Manchester encoded data is oversampled to recover the clock, which is used as the main clock of the recovery module. The other functionalities of PHY of the receiver include undoing all the modifications done by the PHY of the transmitter and the channel. The VHDL code of the receiver PHY is given in Appendix D. The remaining section discusses the PHY of the receiver’s interface, algorithm, design and simulations.

4.3.1 Interface

The PHY of the receiver interfaces with the AFE of the receiver through single bit Manchester encoded data. On the other hand, the PHY of the receiver also interfaces with the APP layer of the receiver through different buses.

4.3.2 Algorithm

The PHY of the receiver can be divided into two parts; 1) this part deals with clock recovery and 2) implementation of the receiver’s FSM.

(36)

Transmitted recovery on the receiver side

The transmitted clock recovery is the most important part of the receiver design. The algorithm of the clock recovery is mainly based on an over-sampling architecture, where overover-sampling clock is used for edge detection. The incoming signal is over sampled with a higher clock in order to detect a transition edge. Theoretically, two times faster clock is enough, however, higher clocks are used in practice. We have used eight times higher clock than the highest clock of the incoming signal, which can detect clock edge of up to 75% duty cycle.

The Manchester encoded clock is recovered by using a simple edge detection algorithm. We know that the Manchester encoded data contains two clocks: 1) a clock equal to the Manchester clock is produced in the encoded data when the consecutive data bits are similar and 2) a clock corresponding to half of the Manchester clock is generated when the consecutive data bits are different. The received Manchester encoded data is oversampled to detect the clock transition. The positive edge detector detects a positive edge in the incoming data; a negative edge detector detects a negative edge while a simple edge detector detects both transitions (negative edge and positive edge). The combination of positive and negative edges recover the Manch-ester clock if the received data stream contain similar data bits (Here, the encoded data contains a full Manchester clock). While a central transition is generated if the received data stream contains different data bits (Here the encoded data contains a half Manchester clock). A central transition is generated upon the absence of a clock edge in the received data. A cen-tral transition can be a transition from low to high or from high to low, depending upon the previously detected edge. The algorithm developed for the transmitted recovery on the receiver side is demonstrated in Figure 4.5. Figure 4.5a shows a block level diagram whereas Figure 4.5b shows various waveforms of receiver clock recovery module.

Receiver’s FSM

Reciever FSM includes data recovery or packet detection and error detection. To ensure the arrival of the new frame, the preamble is first detected, by checking 16 bits of alternating ones and zeros. Then, the start of the packet is found through the start of frame (SOF) delimiter detection. The length of the packet is recovered by decoding the first two bytes of the packet. Once we know the length of the packet, the rest of the packet is decoded as the payload (or data), accordingly. The error detection is also done during the packet detection. The receiver’s FSM is outlined in Algorithm 2.

(37)

(a) Graphical illustration of clock recovery algorithm, where different modules and their interconnection is shown through block diagram.

(b) The simulation graph illustrates the behaviors of receiver clock syn-chronization block. Various signals such as receiver internal clock, re-ceiver input signal, recovered clock, positive edge detection, negative edge detection, simple edge detection and central transition are denoted as clk, rx in, clk recovered, pos edge, neg edge, pn edge, and central transition, respectively.

Figure 4.5: Illustration of clock recovery module: (a) shows block diagram and (b) shows simulation waveforms.

4.3.3 Design

The algorithms developed for the PHY of the receiver discussed in Section 4.3.2 are implemented in hardware using VHDL, which is given in Appendix C. The different submodules of the PHY of the receiver are discussed as follows:

Receiver clock synchronization

The algorithm explained in Section 4.3.2 is used in the actual design of the receiver clock synchronization. The data flip flops (DFF) and logical gates are used to implement edge detection circuits. The whole design is implemented using edge detection blocks, comparators and logical gates. Figure 4.5 shows the design of receiver clock synchronization block.

(38)

Algorithm 2 Receiver FSM

1: State Preamble detection: If the first 16 bits are alternating ones and

zeros, then go to State SOF delimiter detection, else remain in State Preamble detection

2: State SOF delimiter detection: If two consecutive ones are found, then

go to State Length detection

3: State Length detection: Start CRC calculation. Find the length of the

packet by decoding the first two bytes. Store the length of the packet in the buffer, then go to State Packet detection

4: State Packet detection: Start CRC calculation. Store the recovered data

in the buffer, and then go to State Error detection

5: State Error detection: If remainder is zero, CRC flag is reset (successful

transmission), else CRC flag is set (error in transmission). Acknowledge the APP, and then go to State Preamble detection

Figure 4.6: State transition diagram of the receiver FSM.

Receiver FSM

Algorithm of the receiver FSM explained in Section 4.3.2 is used in the hard-ware design of the receiver FSM. The receiver FSM is implemented using data flip flops (DFFs), logical gates and comparators. The design contains the following different states: a preamble detection block for preamble de-tection; an SOF delimiter detection block to detect start of the packet; a

(39)

length detection block used to detect length of the packet; a packet detection block which recovers the received data packet, and an error detection (CRC calculation) block. Figure 4.7a shows the interconnection of different blocks of receiver module. Simulation waveforms of receiver module are shown in Figure 4.7b. The various states of the receiver FSM are illustrated through a state transition diagram in Figure 4.6.

4.3.4 Simulation

The ModelSim simulation tool is used to simulate the PHY of the receiver. A test bench was designed for this purpose. The PHY of the receiver is con-nected to the PHY of the transmitter discussed in Section 4.2. To verify the functionality of the receiver, a test sink is also created. Various waveforms of the receiver PHY are shown in Figure 5.2. Figure 5.6 to Figure 5.8 show simulation results of the PHY of the receiver.

4.4 CSMA/CA

It is a logical control module, which controls different modules of the PHY of the transceiver. The control module also implements the classical carrier senses multiple accesses/collision avoidance (CSMA/CA). The CSMA/CA uses the strategy of listening before talk [37]. It means, in the CSMA/CA, a transmitting node always first sense the medium before starting any trans-mission. If the medium is free, the transmitting node starts transmitting its packet; otherwise it waits for a random number of cycles and checks the medium again for availability. A classical CSMA/CA multiple access technique is demonstrated through a flow diagram shown in the Figure 4.8, which starts with assembling data into a frame and transmitting the frame if the channel is available for transmission or waiting for a random number of clock cycles if the channel is busy.

The classical CSMA/CA medium access control protocol is implemented to achieve full duplex communication in the BAN using HBC. The various devices in a BAN using HBC are connected through the human body. Be-fore initiating any transmission, the receiver module checks if there is any activity on the medium. If the medium is free, the transmitter module of the transceiver starts transmitting data. Upon finding activity on the medium, the receiver modules of all transceivers in the network start receiving the incoming data frame. All receiver modules receive and decode the frame up to the destination field. The transceiver who finds a destination address match continues rest of the frame, while all other transceivers discard the data and go to idle mode for the duration of the length of the packet as every transceiver decodes the length of the packet field as well. Although the clas-sical CSMA/CA is implemented to avoid collision and control the medium

(40)

access, a collision is still possible, however, in a rare scenario when multiple transmitters start transmission simultaneously. In this particular scenario, incorrect data will be received by all the transceivers. Upon receiving in-correct data, all transceivers will discard transmissions and will reschedule the transmission with different random times. The control module is also responsible for controlling the flow of data between different modules of the transceiver.

4.5 Summary

In this chapter, we discussed the hardware implementation of the PHY of the transceiver. The implemented transmission protocol of the PHY of the digital baseband transceiver of the BCC is inspired by IEEE 802.3 Ethernet transmission protocol. For medium access control, the classical CSMA/CA was implemented, enabling the full duplex communication. The VHDL lan-guage was used for hardware implementation of the design. To verify the functionality of the PHY of the transceiver, various test benches were also developed. The ModelSim simulation tool was used for design verifications and simulations. The simulation results are further discussed in the follow-ing Chapter 5.

(41)

(a) A block diagram showing the submodules of receiver PHY.

(b) Simulation waveforms of receiver PHY. The various sig-nals such as receiver input, recovered clock, preamble detec-tion, find sof , length detection, packet detection are denoted as rx in, clk recovered, preamble detected, sof f ound, length detected, and packet detected.

Figure 4.7: Illustration of receiver PHY: (a) shows a block level diagram of receiver PHY and (b) shows various simulation waveforms.

(42)

Figure 4.8: Flow diagram of the classical CSMA/CA

(43)

Figure 4.9: A block diagram showing the different modules of the digital baseband transceiver along with the application layer and analog front end (AFE).

(44)

Chapter 5 BAN PHY–Simulation

Results and Timing

Diagrams

This chapter illustrates the functionality of the PHY of the BAN transceivers through simulations using ModelSim simulation tools.

5.1 Introduction

The PHY layer of the digital baseband transceiver discussed in Chapter 4, is implemented through hardware description language (VHDL). A testbench was developed (using VHDL given in Appendix A), for verifying the tionality of the PHY of the BCC transceivers. To ensure the correct func-tionality of the implemented classical CSMA/CA, three transceivers were connected with each other forming a small network. It realizes the scenario of the actual BAN transceivers in a human body area network using BCC. The developed test bench is discussed as follows:

5.2 Test bench

For design verification, a testbench is developed. The different modules of the test bench are discussed in the following subsections.

5.2.1 Test clock module

The test clock module generates different clocks used in the simulations. To realize the actual scenario, three transmitter clocks with the same clock frequency and different clock edges are used. Similarly, to verify the syn-chronous clock recovery and to realize the practical scenario, three different receiver clocks having the same clock frequency, but different clock edges are

(45)

Chapter 5. BAN PHY–Simulation Results and Timing Diagrams

used. Also note that the clock edges of the transmitter and receiver within the same transceiver are also different. The various clock edges are shown in simulation Figure 5.3.

5.2.2 APP transceiver 1

A simple application layer (APP) is designed, which passes data from the keyboard along with handshaking signal to the PHY of the transceiver com-ponent 1. This application layer also receives the recovered data from the PHY of the transceiver component 1.

Similarly, the APP transceiver 2, passes data from the keyboard along with handshaking signal to the PHY of the transceiver component 2. Also, it receives the recovered data from the PHY of the transceiver component 2. Figure 5.1 shows how the different components of the test bench are connected with each other.

This application layer passes data from the keyboard and handshaking signal to the PHY of the transceiver component 3. It also receives the recovered data from the PHY of the transceiver component 3.

The various waveforms along the transmitted and received path are shown in Figure 5.2. These are also shown in the simulation results in Section 5.3.

5.3 Simulation results

For design verification of the digital baseband transceivers for the BAN, various simulations were performed. A network of three transceivers, shown in Figure 5.1, is created in the simulation test bench. This network real-izes a simple BAN. For data handling, simple application layers, i.e., APP transceiver 1, APP transceiver 2 and APP transceiver 3, are used with transceiver components 1, 2 and 3, respectively.

As discussed in Section 5.2, to realize a practical scenario, transmitter and receiver clocks must have different edges. In our simulations, we clock differ-ent transceivers with test clocks having differdiffer-ent edges. The differdiffer-ent edges of the various test clocks used are shown in simulation Figure 5.3. The correct functionality of the transceivers in the network is verified through a scenario, where transceiver 1 sends data to transceiver 2 and transceiver

(46)

Figure 5.1: Elaboration of the testbench developed for design verifications. Three instances of the transceiver are used, which represent three different transceivers, forming a small network. On the one side each transceiver is connected with a separate application layer, while, on the other side, all transceivers are connected with each other, realizing a BAN network.

2 wants to send data to transceiver 1. Here, transceiver 1 first senses the carrier (channel) for availability, by checking activity (transition from ’1’ to ’0’ or ’0’ to ’1’) on the input of the receiver module. If transceiver 1 finds no activity on the input of receiver module, so this means that the medium is free. Upon finding the medium free, transceiver 1 starts the transmission of data. Now, sensing activity on the medium, transceiver 2 and transceiver 3 both start receiving the transmission from transceiver 1. Both transceiver 2 and transceiver 3 receive and decode the data frame till the destination ID field of the frame. We know that the intended data frame is for transceiver 2. Therefore, upon checking the destination ID, transceiver 3 discards the received data and stops receiving data for the rest of the frame transmission time. Transceiver 3 goes to idle mode for the duration of the frame trans-mission as it knows the length of the packet. Transceiver 2, upon matching the destination ID, receives and decodes the whole frame. Transceiver 2 recovers the data packet and stores it in its memory, which is further pro-cessed (i.e., displayed) by its application layer.

Also, during the frame transmission of transceiver 1, transceiver 2 also wants

(47)

Figure 5.2: Different waveforms along the transmitted and received path.

to send data. Upon sensing the medium, which was busy, transceiver 2 waits for a random time, longer than the ongoing frame transmission time. Once the waiting time is over, transceiver 2 again senses the medium. This time, upon finding the medium available for transmission, transmitter 2 starts transmission of the data. Now transmitter 1 and transmitter 3 start receiv-ing data. Transceiver 3 discards the packet and stops receivreceiv-ing data upon checking the destination ID which is for transceiver 1. As the destination ID matches for transceiver 1, it decodes and stores data in its memory. The PHY layer of the transceiver 1 also send the recovered data to its applica-tion layer for further processing (i.e., displaying in this case). The above transmission scenario is shown in Figure 5.4.

We also show some other important simulation graphs in Figures 5.5, Figure 5.6, Figure 5.7, Figure 5.8, and Figure 5.3. All these figures are described with their captions.

5.4 Conclusion

Various simulation results are discussed in this chapter. The functionality of the PHY of the digital baseband transceiver is verified through a test

(48)

Figure 5.3: The simulation diagram illustrates the behaviors of various test clocks used for simulations. The signals clk1 and clk2 show slow clocks used for transmitter PHY. It is also shown in the graph that the clk1 and clk2 have different delays and different edges while their clock period is the same. Similarly, signals rx clk1 and rx clk2 show the faster clock used for receiver clock recovery module.

Figure 5.4: A detailed simulation graph showing data transfer within the network of three transceivers, where transceiver 1 sends data to transceiver 2 and transceiver 2 sends data to transceiver 1.

(49)

Figure 5.5: This simulation graph shows various signals and buses of the transmitter PHY. The final transmitter output is shown through the signal tx out.

bench. The actual scenarios are realized by performing different simulations. We have used ModelSim as a simulation tool. The implemented classical CSMA/CA is also demonstrated and verified through a BAN network of three transceivers connected with each other.

(50)

Figure 5.6: This simulation graph shows various signals and buses of the receiver PHY. The receiver input is shown through signal rx in. The re-covered clock is shown through signal clk rere-covered. The faster receiver internal clock is shown through signal clk. The final decoded output is shown through signal rx out.

(51)

Figure 5.7: This simulation graph shows FSM of the receiver PHY. Upon receiving the input on signal rx in, the different states of FSM of the receiver PHY is shown through various signal and buses. The signal rx busy shows the busy state of the receiver PHY. The other important signals recovered clock, and final receiver output are shown though signals clk recovered and rx out.

(52)

Figure 5.8: The simulation graph shows the necessary signals of receiver clock recovery module. For oversampling, an eight times faster clock shown through signal clk is used. The various edge detectors signals are shown through pos edge, neg edge and pn edge. The final recovered clock is shown though signal clk recovered.

(53)

Chapter 6 FPGA Demonstrations

6.1 Introduction

This chapter discusses the demonstrations of the digital baseband transceivers for the BCC on the FPGA board. The ModelSim is used for the simula-tion of the synthesize-able VHDL design. The Quartus II software is used for synthesis, place and route and bitstream generation. Altera DE2-115 FPGA board is used for demonstration of the design that provides a 50 MHz clock signal [38]. The required 80 MHz clock signal is generated by using a phase-locked loop (PLL) provided on the FPGA board.

6.2 Application Layers

For the demonstration of the PHY layer of the digital baseband transceiver on FPGA board, a couple of application layers are developed using VHDL. These application layers are discussed as follows:

6.2.1 Data transfer application layer

A keyboard application layer is designed using VHDL to transfer data from the keyboard to the PHY layer of the digital baseband transceiver. Two different versions of the keyboard application are created; 1) a version work-ing with make code and 2) other version, workwork-ing with break code. The keyboard application layer transfers, the eight bit code to the PHY layer of digital baseband transmitter, along with the sop and eop handshaking signals when the key is pressed.

6.2.2 Data display application layer

The LCD component of FPGA board is used to display the recovered data at the receiving end of the PHY layer of the digital baseband transceiver. An LCD application layer designed in VHDL displays the received data on