A Cyclic Analog to Digital Converter for CMOS image sensors

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Department of Electrical Engineering

Examensarbete

A Cyclic Analog to Digital Converter for CMOS

image sensors

Examensarbete utfört i elektroniksystem vid Tekniska högskolan vid Linköpings universitet

av

Deyan Levski Dimitrov

LiTH-ISY-EX--13/4674--SE

Linköping 2013

Department of Electrical Engineering Linköpings tekniska högskola Linköpings universitet Linköpings universitet SE-581 83 Linköping, Sweden 581 83 Linköping

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image sensors

Examensarbete utfört i elektroniksystem

vid Tekniska högskolan i Linköping

av

Deyan Levski Dimitrov

LiTH-ISY-EX--13/4674--SE

Handledare: J Jacob Wikner

isy, Linköpings universitet

Trygve Willassen

OmniVision Technologies Inc.

Examinator: J Jacob Wikner

isy, Linköpings universitet

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Division of Electronic Systems Department of Electrical Engineering Linköpings universitet

SE-581 83 Linköping, Sweden

2013-06-12 Språk Language Svenska/Swedish Engelska/English Rapporttyp Report category Licentiatavhandling Examensarbete C-uppsats D-uppsats Övrig rapport

URL för elektronisk version http://www.es.isy.liu.se http://www.ep.liu.se ISBN — ISRN LiTH-ISY-EX--13/4674--SE

Serietitel och serienummer

Title of series, numbering

ISSN

—

Titel

Title

A Cyclic Analog to Digital Converter for CMOS image sensors A Cyclic Analog to Digital Converter for CMOS image sensors

Författare

Author

Deyan Levski Dimitrov

Sammanfattning

Abstract

The constant strive for improvement of digital video capturing speeds together with power efficiency increase, has lead to tremendous research activities in the image sensor readout field during the past decade. The improvement of lithogra-phy and solid-state technologies provide the possibility of manufacturing higher resolution image sensors. A double resolution size-up, leads to a quadruple read-out speed requirement, if the same capturing frame rate is to be maintained. The speed requirements of conventional serial readout techniques follow the same curve and are becoming more challenging to design, thus employing parallelism in the readout schemes appears to be inevitable for relaxing the analog readout circuits and keeping the same capturing speeds. This transfer however imposes additional demands to parallel ADC designs, mainly related to achievable accuracy, area and power.

In this work a 12-bit Cyclic ADC (CADC) aimed for column-parallel read-out implementation in CMOS image sensors is presented. The aim of the con-ducted study is to cover multiple CADC sub-component architectures and provide an analysis onto the latter to a mid-level of depth. A few various Multiplying DAC (MDAC) structures have been re-examined and a preliminary redundant-signed-digit CADC design based on a 1.5-bit modified flip-over MDAC has been conducted. Three comparator architectures have been explored and a dynamic interpolative Sub-ADC is presented. Finally, some weak spots degrading the per-formance of the carried-out design have been analyzed. As an architectural im-provement possibility two MDAC capacitor mismatch error reduction techniques have been presented.

Nyckelord

Keywords CMOS, Image Sensor, ADC, Cyclic ADC, Algorithmic ADC, MDAC, Switched Capacitor, Comparator, OTA, Logic, IC, VLSI, Circuit, System

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The constant strive for improvement of digital video capturing speeds together with power efficiency increase, has lead to tremendous research activities in the image sensor readout field during the past decade. The improvement of lithogra-phy and solid-state technologies provide the possibility of manufacturing higher resolution image sensors. A double resolution size-up, leads to a quadruple read-out speed requirement, if the same capturing frame rate is to be maintained. The speed requirements of conventional serial readout techniques follow the same curve and are becoming more challenging to design, thus employing parallelism in the readout schemes appears to be inevitable for relaxing the analog readout circuits and keeping the same capturing speeds. This transfer however imposes additional demands to parallel ADC designs, mainly related to achievable accuracy, area and power.

In this work a 12-bit Cyclic ADC (CADC) aimed for column-parallel read-out implementation in CMOS image sensors is presented. The aim of the con-ducted study is to cover multiple CADC sub-component architectures and provide an analysis onto the latter to a mid-level of depth. A few various Multiplying DAC (MDAC) structures have been re-examined and a preliminary redundant-signed-digit CADC design based on a 1.5-bit modified flip-over MDAC has been conducted. Three comparator architectures have been explored and a dynamic interpolative Sub-ADC is presented. Finally, some weak spots degrading the per-formance of the carried-out design have been analyzed. As an architectural im-provement possibility two MDAC capacitor mismatch error reduction techniques have been presented.

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First and foremost, I would like to express my deepest gratitude to Dr. J Jacob Wikner - the person, who first introduced me to this wonderful cosmos of inte-grated circuits and has made all this work possible. Jacob, teaching and guiding others is one of the most important things a person can ever do in their life. Thank you for taking the time to educate me and also for bringing me alert on topics even beyond the scope of science.

I am very thankful to Trygve Willassen who acquainted me with the world of image sensors and had guided me throughout this thesis work in an excellent way. Many of the ideas in this thesis I owe to him and without his guidelines none of this could have been possible. Thank you Trygve!

I would like to say big thanks to my friend Pavel Angelov. All electronics-related and not only, discussions were a real pleasure, and I thank him for always being aside for technical comments and suggestions.

I would also like to thank my colleagues and friends Jonas Tallhage, Johan Lindeberg, Andreas Öhlin and Georgios Mylonas for making the endless days and nights spent in the labs throughout my master’s education in Linköping University a real joy.

Finally, I am very grateful for being raised by parents who have always been paying attention to me and my upbringing. I thank my dad for opening for me, five times for one evening the back-lid of our tube radio receiver when I was at the age of four and for giving me that box of electromechanical relays igniting my interests to technics at a very early age. Without the unconditional care and love of my parents, all this would have never been possible.

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1 Introduction 5

1.1 A scope and goals of this thesis . . . 5

1.2 Introduction to CMOS image sensors . . . 6

1.3 Pixel structures . . . 6

1.3.1 Passive pixel . . . 7

1.3.2 Three-transistor active pixel . . . 8

1.3.3 Photogate and PIN photodiode active pixels . . . 9

1.3.4 Correlated double sampling . . . 9

1.4 Readout architectures . . . 10

1.4.1 Shutter modes . . . 10

1.4.2 Serial readout . . . 10

1.4.3 Parallel readout . . . 11

1.5 Noise sources in CIS . . . 12

1.5.1 Temporal noise sources . . . 13

1.5.2 Spatial noise sources . . . 16

1.6 Analog to digital converters in CMOS image sensors . . . 18

1.7 Algorithmic (Cyclic) ADC . . . 19

1.7.1 Redundant Signed Digit (RSD) error correction technique . 20 1.7.2 Switched-capacitor network MDAC structures . . . 21

1.8 Requirements over ADCs for CIS . . . 26

1.8.1 Integral non-linearity . . . 27

1.8.2 Differential non-linearity . . . 28

1.8.3 Full-scale step response . . . 29

1.8.4 Random noise . . . 29

1.9 ADC design requirements . . . 29

2 The Cyclic ADC implementation 31 2.1 Introduction and architectural choice . . . 31

2.1.1 A brief walkthrough on the proposed by [22] architecture . 32 2.2 The MDAC in details . . . 34

2.2.1 Functional analysis . . . 34

2.2.2 Capacitor choice and matching requirements . . . 37

2.2.3 Noise considerations . . . 38

2.3 OTA choice and design . . . 39 ix

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2.3.1 OTA DC gain requirement . . . 39

2.3.2 OTA bandwidth requirement . . . 41

2.3.3 OTA slew rate requiement . . . 41

2.3.4 OTA CMRR and PSRR requirement . . . 41

2.3.5 OTA offset requirement . . . 42

2.3.6 The elemental current mirror OTA . . . 42

2.3.7 A current mirror OTA with output cascodes . . . 44

2.3.8 Regulated cascodes . . . 45

2.3.9 Sizing methodology . . . 46

2.3.10 OTA results . . . 51

2.3.11 Comments on the current design state of the OTA . . . 54

2.4 Sub-AD Comparators . . . 55

2.4.1 Architecture exploration . . . 56

2.4.2 The Sub-AD comparator implementation . . . 60

2.4.3 Speed design considerations . . . 65

2.4.4 Design considerations with respect to offset . . . 66

2.4.5 Kickback noise design considerations . . . 67

2.4.6 Comparator resolution and noise . . . 69

2.4.7 Designed comparator’s characteristics . . . 71

2.4.8 Sub-AD control logic . . . 71

2.4.9 Sub-AD Phase Mux Memory . . . 73

2.5 MDAC switch network . . . 73

2.5.1 Basic switch background theory . . . 74

2.5.2 A clock boosted switch . . . 75

2.5.3 The bootstrapped switch technique . . . 76

2.5.4 The implemented transmission gate switch and its optimiza-tion . . . 78

2.5.5 Critical switch nodes . . . 81

2.6 RSD to binary converter . . . 82

2.7 CDS in-column subtracter . . . 83

2.8 A capacitor mismatch effect reduction technique . . . 84

2.9 A pseudo-calibration technique . . . 87

2.10 ADC timing and clock generation . . . 89

2.10.1 Basic ADC timing . . . 89

2.10.2 A possible linearly decreasing period clocking scheme . . . 90

2.10.3 Possible clock generation schemes . . . 91

3 Designed ADC characterization and results 93 3.1 Current ADC design state . . . 93

3.2 Linearity tests . . . 93

3.3 Random noise tests . . . 95

3.4 Sampling speed tests . . . 97

3.5 Summarised results . . . 97

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Bibliography 101 A Verilog-A implementation of a comparator offset-search

compo-nent using a binary search algorithm 105

B Comparator noise output variance calculation script in Matlab 108 C INL and ADC column mismatch image artifact simulation script

in Matlab 110

D ADC Random noise variance evaluation script following IEEE

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1.1 One-transistor passive pixel schematic. . . 7

1.2 Three-transistor active pixel schematic. . . 8

1.3 Four-transistor (Photogate) active pixel principal schematic. . . 9

1.4 A PIN diode active pixel principal schematic. . . 9

1.5 Serial (single ADC) readout architecture. . . 11

1.6 Parallel readout architecture. . . 11

1.7 Power supply / clock / control signal RC network model. . . 12

1.8 Energy diagram of a reverse biased p-n junction. . . 13

1.9 Thermal noise definition. . . 14

1.10 Capacitor and its internal parasitic conductance. . . 15

1.11 Band diagram with discrete sub-levels caused by impurities. . . 16

1.12 Column ADC mismatch (8-bit image) ±1 LSB. . . 17

1.13 Column ADC mismatch (8-bit image) ±2 LSB . . . 17

1.16 Column switching technique for CFPN reduction. . . 18

1.17 A functional block diagram of a RSD Cyclic ADC. . . 19

1.18 A comparative example between RSD and conventional ADC stages. 20 1.19 “Flip-around” multiplying digital to analog converter (MDAC). . . 22

1.20 “Modified flip-around” multiplying digital to analog converter (MDAC). 23 1.21 Simple capacitor stacking in series concept for voltage doubling. . . 24

1.22 A switched capacitor integrator - multiply by n structure. . . 24

1.23 Signal sampling phase. . . 25

1.24 Reset sampling phase. . . 25

1.25 Feedback and amplification phases. . . 25

1.26 Random uniform ADC INL (8-bit image) ±1 LSB. . . 28

2.1 Principal diagram of the proposed by Jong-Ho Park, Satoshi Aoyama and Takashi Watanabe [22] ADC architecture. . . 32

2.2 Local in-DAC mid-reference generation. . . 33

2.3 Principal schematic diagram of the MDAC. . . 34

2.4 Possible reference voltage configurations during amplification phase. 35 2.5 Detailed MDAC configurations for the four phases. . . 36

2.6 Ideal transfer function of the MDAC. . . 37

2.7 Noise accumulation sources during MDAC’s MSB sampling and am-plification phases. . . 39

2.8 An OTA configuration in a closed-loop configuration as a negative feedback amplifier for the purpose of gain requirement estimation. 40 2.9 A single-ended version of an elemental current mirror operational transconductance amplifier architecture. . . 42

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2.10 An equivalent small signal model of the current mirror OTA shown

on Figure 2.9. . . 43

2.11 Single output cascode section. . . 44

2.12 ESSS for Rout derivation of the single output cascode. . . 45

2.13 A regulated cascode built-up upon a common source feedback tran-sistor. . . 46

2.14 An excerpt of a current mirror OTA cascode stage built-up on RGCs. 47 2.15 The used current mirror OTA architecture. . . 47

2.16 Transit frequency versus gm/Id, W=10 µm L=1 µm. . . . 49

2.17 Transit frequency versus Vgs, W=10 µm L=1 µm. . . . 49

2.18 gm/Id versus Vgs, W=10 µm L=1 µm. . . . 50

2.19 gmr0 versus Vgs, W=10 µm L=1 µm. . . . 50

2.20 Family plot of gmId versus Id/W. . . 50

2.21 OTA step response overview of slew and settling time at Cl= 700fF and tclk= 500ns. . . . 53

2.22 An opamp in open-loop being used as a voltage comparator. . . 55

2.23 A regenerative latch. . . 56

2.24 A principle schematic diagram of the main kickback noise path back to the signal source. . . 56

2.25 A principle schematic diagram of a simple static latched comparator. 57 2.26 A semi-static often referred to as Class AB comparator. . . 58

2.27 A dynamic comparator implementation. . . 59

2.28 Comparator tradeoffs. . . 60

2.29 OTA residual voltage and comparator evalutaion time. . . 61

2.30 Sub Flash AD comparator interpolation technique as described by [23]. . . 62

2.31 Mid-reference interpolation output voltages of two differential am-plifier stages in a function of a linearly swept input voltage, hooked-up following the configuration on Figure 2.30. . . 63

2.32 A principal schematic diagram of the implemented Sub-AD com-parators. . . 64

2.33 A regenerative CMOS inverter based latch with its main parasitic capacitance contributors. . . 65

2.34 Lumped ESSS of the inverter latch shown on Figure 2.33. . . 65

2.35 Offset voltage search progress of the search component. . . 67

2.36 A kickback noise simulation comparison between (a) Static, (b) Class AB and (c) Dynamic comparator implementations. . . 68

2.37 A primitive comparator resolution test. . . 69

2.38 Input referred noise testbench scenario. . . 70

2.39 Simulated comparator noise variance. . . 70

2.40 A principal logic diagram of the implemented Sub-AD encoding control logic. . . 72

2.41 A principal logic diagram of the Sub-AD feedback memory multi-plexer. . . 73

2.42 On-resistance of MOSFET and transmission-gate based switches dependence on Vin. . . 74

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2.43 A physical illustration of the channel charge injection effect. . . 74

2.44 A clock-boosted switch implementation as presented by [14]. . . 76

2.45 A visual representation of the applied boosted gate voltage. . . 76

2.46 A bootstrapped switch implementation as proposed by [2]. . . 77

2.47 The bootstrapped concept - a simulated visual representation. . . . 78

2.48 A transmission gate. . . 78

2.49 Charge injection testbench. . . 79

2.50 Injected charge at the output sample node for different W L ratios versus applied gate overdrive voltage Vgov. . . 79

2.51 Injected charge ratio Ci Co versus applied gate overdrive voltage Vgov for a fixed switch size. . . 80

2.52 On-resistance plot of the implemented transmission gates vs Vin. . 80

2.53 Equivalent gate capacitance Cgg for different W/L ratios versus switch input voltage. . . 81

2.54 Equivalent on-resistance Ronfor different W/L ratios versus switch input voltage. . . 81

2.55 A clarification of the considered accuracy-critical switch nodes. . . 82

2.56 Principle schematic diagram of a serial RSD to parallel binary con-verter. . . 83

2.57 Principle schematic diagram of the in-column DCDS subtracter. . 84

2.58 A principle schematic implementation of a capacitor flipping tech-nique for the current MDAC. . . 85

2.59 Error reduction effect variation with respect to the used converter resolution. . . 86

2.60 A comparative error reduction progress between the even-odd ca-pacitor flipping technique and the proposed pseudo-calibration flip-ping method. C1=500 fF, C2=487 fF. . . 87

2.61 An ideological overview of a hardware implementation of the pseudo-calibration technique. . . 88

2.62 MDAC timing and control phases. . . 90

2.63 ADC Sub-AD comparators, memory mux and serial RSD to BIN converter timing control phases. . . 91

2.64 A basic graphical overview of the linearly decreasing period clocking scheme. . . 91

2.65 An ideological representation of oversampled digital control phase generation. . . 92

2.66 A basic graphical overview of a DLL-based linearly decreasing pe-riod clocking scheme. . . 92

3.1 Simulated worst case corner Integral Non-Linearity. . . 94

3.2 Simulated worst case corner Differential Non-Linearity. . . 94

3.3 Differential Non-Linearity deviation distribution. . . 95

3.4 Integral Non-Linearity deviation distribution. . . 95

3.5 Simulated random noise variance, estimated by 1500 samples, worst case corner. . . 96

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3.6 Residue voltage settling at conversion speeds of 100, 125, 150 and 166 kSps (from top to bottom) at worst case corner. . . 97

List of Tables

1.1 Main ADC specifications followed during the design study . . . 29 2.1 OTA Electrical characteristics measured at supply voltage of 3.3V

and 70 ℃ . . . 54 2.2 Summary of the main measured comparator performance parameters 71 2.3 A truth table of the implemented Sub-AD logic . . . 72 2.4 Serial RSD - parallel BIN conversion progress. . . 83 3.1 Summarised performance results of the designed converter . . . 98

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Introduction

The target of this thesis is to search for, investigate and elaborate on the design of an algorithmic, also commonly known as cyclic, ADC architecture for the purpose of its implementation in a column-parallel readout CMOS image sensor. With the increase of image sensors’ resolution and frame rate, traditional serial readout schemes become more laborious to design and in many cases simply unachievable for certain required readout speeds.

A possible solution to this problem is the usage of multiple parallelly working ADCs, in order to relax the speed requirements of the otherwise standalone data converter. This solution to the problem however, as in any technological problem has its advantages, challenges and disadvantages. One of the challenge points in column-parallel ADCs appear to be the tight silicon area and power consumption requirements. As various ADC architectures exist, among the compact ones strike to be the algorithmic (cyclic) ADC.

The most relevant reasoning about the conduction of this study on cyclic ADCs is the low area requirements as well as the reasonably high resolutions and con-version rates achievable with this type of converters. Additionally the reasoning about the cyclic architectural choice was that the topic was stated as of particular interest to the thesis co-supervision side at OmniVision Technologies.

1.1 A scope and goals of this thesis

Besides the learning experience, the scope of this thesis was to investigate on various cyclic data converter techniques to be implemented in an image sensor’s column-parallel readout architecture. Some of the main goals and milestones thoughout the thesis development are listed below:

• To conduct a study on image sensor readout architectures, identify the re-quirements imposed by the readout architecture on the cyclic converter to be implemented, and set preliminary ADC design requirements to follow throughout the rest of the study.

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• To explore various cyclic ADC architectures, pick an architecture capable of conforming with the set ADC performance requirements and motivate the contrived choice.

• To design and verify the chosen cyclic ADC core architecture, excluding the supporting power, reference and clock generation circuitry.

• To explore potential improvement techniques and/or possible architectual changes.

1.2 Introduction to CMOS image sensors

Historically the first trials of image sensor developments date back to 1969, when Willard Boyle and George Smith at Bell Labs invented the first charge-coupled device (CCD), which a few years later was implemented in the Hubble Space Telescope [4]. In the same decade range a non-charge-transfer imaging device, as we know it nowadays as CMOS image sensor, was introduced. Even though that both technologies are based on converting photon sheafs to electrical charges, CCD based image sensors gained higher velocity due to the fact that they provided much better imaging qualities with the existent semiconductor technology. In the later years, starting late 1980s, with the development of high precision lithography and silicon purification technologies, CMOS image sensors gained popularity, as they provide possibilities for reduced power consumption and integration of complete on-chip cameras.

This introductory chapter about CMOS image sensor readout and data conver-sion architectures is organized as follows. Section 1.3 gives a brief overview of the common CMOS pixel structures. Section 1.4 provides an overview of the common image readout techniques and some practical considerations with respect to the data converter’s point of view. In Section 1.5 a basic image sensor noise source classification has been synthesized. Sections 1.6 and 1.7 provide an overview of the most commonly used ADCs in column-parallel readout architectures, elabo-rate on the cyclic ADC fundamentals and present a few existent sub-component architectures. Finally Section 1.8 gives an analysis of the most important ADC performance parameters when considering column-parallel image readout and pro-vides preliminary ADC specifications used for the conducted design in Chapter ??.

1.3 Pixel structures

As the current thesis is related to image sensors, a short introduction to some of the common pixel structures would be given in the following section. A few pixel parameters have direct influence on the data conversion circuitry and an integration between the data converter and the pixel can not be successful if both components are not closely studied in conjunction. A bulletwise list with the most important pixel parameters, required as input data for the ADC design, is very briefly introduced below.

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• Output range - for full utilization of the converter’s resolution, its input range should match with the pixel’s output range.

• Integration (exposure) time - the minimum integration time goal for the CMOS image sensor is one of the parameters involved in the maximum required ADC conversion rate.

• Reset time - the pixel reset time would base to be the second parameter setting the maximum required ADC speed.

• Noise - the pixel’s output noise would practically set the random ADC noise boundary. As a rule of thumb the random ADC noise is always less than the induced pixel noise.

The above-mentioned parameters were very briefly discussed and the whole following section, aims to provide a closer look, yet at a very basic level of the "device under measurement" from the image sensor’s ADC perspective.

1.3.1 Passive pixel

A passive pixel, provides most simplicity with respect to in-pixel design and device count, however it has a few major disadvantages, which are also the cause of its lesser popularity. Figure 1.1 shows a basic principle schematic diagram of a passive pixel. 1T passive pixel to charge amplifier PD column readout Vword

Figure 1.1: One-transistor passive pixel schematic.

The main disadvantage regarding passive pixels is their slow readout speed. For reading-out a column charge amplifier, sample and hold as well as a multi-plexer for the case of a serial readout architecture is required. The time1_required

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for the pixel’s sensing may be significant, a potential readout speed-up could be preformed if the charge amplifiers have increased sensitivity, this however amplifies random noises as well. An additional disadvantage is that the performed reading is destructive, similar to dynamic random access memory, which does not allow an usage of correlated double sampling techniques, this effectively reduces the SNR of the pixel - to be discussed in further sections.

Possible advantages of the passive pixels, would be their small pixel size, thus the possibility for dense matrix incorporation. Having no additional in-pixel de-vices means that the pixel’s fill factor would be high and thus having an increased quantum efficiency. The latter statement however makes a difficult comparison, as with the usage of micro-lenses, lower fill-factor pixels may have higher efficiency, thus fill-factor should not be considered as a standalone parameter or a parameter providing information about the pixel’s performance.

1.3.2 Three-transistor active pixel

An active pixel, implies that charge transfer and photodiode integration is per-formed in-pixel, and only voltage levels are read-out of the pixel array. Figure 1.2 shows an example principle schematic diagram of a three-transistor active pixel.

VDD VDD active pixel Ibias PD column readout Vreset Vword

Figure 1.2: Three-transistor active pixel schematic.

We can observe that the readout voltage is now buffered with a voltage follower and much more controllability is now introduced with the usage of a reset transis-tor. A huge advantage in comparison with passive pixels is the increased readout speed, due to the direct voltage readout, instead of charge transfer. Such a buffer configuration implies that readouts now, in comparison with passive pixels are not destructive. By controlling the reset voltage level additional charge controllability could be introduced. The column readout circuit would have a reduced complexity as now the charge amplifier is transferred in-pixel.

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All forementioned additional devices however, increase the pixel’s complexity, respectively size, and reduce the allocated photodiode junction area. Despite these difficulties, with the usage of micro-lenses, the overall achievable SNR with such a three-transistor active pixel may be larger, in comparison with passive pixels, if the pixel’s size is not taken into consideration.

1.3.3 Photogate and PIN photodiode active pixels

The photogate (four-transistor) and PIN photodiode pixel implementations differ by device count with an addition of an extra transfer transistor, in comparison with the three-transistor implementation. All column readout circuitry is identical to the basic three-transistor pixel. Figure 1.3 and 1.4 show principle schematic diagrams of the two active pixel architectures.

VDD p+ TX PG Vreset Vword n n out

Figure 1.3: Four-transistor (Pho-togate) active pixel principal schematic. VDD p+ TX PPD Vreset Vword n n out

Figure 1.4: A PIN diode active pixel principal schematic.

The abovedescribed pixel architectures’ most relevant feature is that they are suitable for Correlated Double Sampling (CDS), which is also their main advantage over the three-transistor architectures. A basic drawback of this architecture could be the additional introduction of devices, which may degrade the pixel’s fill-factor, sensitivity and response.

1.3.4 Correlated double sampling

As the term Correlated Double Sampling (CDS) would be mentioned intensively during the next chapters, this subsection would aim to very briefly introduce the CDS principle and its advantages.

Practically CDS is a technique, allowing the measurement of absolute signal values, by removing undesired offset effects caused typically by noise disturbances. The technique is especially vital for the pixel’s readout, as throughout reset time, it is not possible to apply equal starting reset conditions to all pixels every time.

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Thus CDS practically is a technique measuring the absolute difference between two conditions, in this case - reset condition and end of exposure integration condition. In CMOS image sensors CDS can be performed in both the analog or digital domains. In the analog domain, the reset voltage is sampled and held, while after integration both the previous and current signals are subtracted, typically with the use of a differential amplifier. A digital correlated double sampling (DCDS), is a technique following the same scheme, however instead of storing the two variables in analog memory (as the sample and hold circuit is), an ADC is used to convert both readout voltages and a background subtraction in the digital domain is performed.

1.4 Readout architectures

The selection of readout architecture plays a significant role in the ADC design. We can distinguish three main types of architectures commonly used in practice. These are, serial, parallel and some hybrid readout architectures.

1.4.1 Shutter modes

This sub-section aims to give a very brief overview of the typical shutter modes used during a readout, since choice of shutter will also affect the readout and data converter requirements. Practically electronic shutters could be divided into two groups:

1. Rolling shutter - in CMOS sensors, this is probably the easiest shutter mode to implement, since it consists of consecutive row readouts in very fast speeds. This is probably the most spread shutter mode among low-cost imagers. However, the pixel, as well as the readout circuitry speed requirements should be very high in order to reduce effects of skewed, smeared and corrupted exposure fast moving objects in the reconstructed image.

2. Global shutter - a solution for eliminating the described negative effects of rolling shutter mode sensors, is to implement a readout, which captures all pixel information simultaneously. In CMOS one possible solution is to use an analog sub-memory block inside the pixel, typically a floating diffusion used as a storage element. With such a configuration the requirements on the pixel settling, as well as the speed of the readout circuitry could be relaxed, however the in-pixel analog memory block creates higher challenges in the pixel design and may cost image quality.

1.4.2 Serial readout

The architecture which appeared in the beginning of the CMOS image sensor evolution was a serial readout (single ADC) based Figure 1.5. While this structure provides excellent linearity and matching, due to the single ADC used for all pixel’s readout, it sets very high speed requirements on the data converter and additional circuit complexity, related to temporary charge storage and feed-out.

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R O W D E C O D E R ADC Column Amplifiers/Sample and Hold

Column Multiplexers

Figure 1.5: Serial (single ADC) read-out architecture. 0101 0101 0101 0101 0101 0101 0101 0101 0101 0101 R O W D E C O D E R

Local Memory and Drivers

to on-chip processing

Figure 1.6: Parallel readout architec-ture.

With the increase of array’s resolution, it becomes apparent, that doubling the resolution would increase the conversion speed requirements on the ADC by a factor of 4 at the same frame rate. With nowadays’ high frame rate and resolution requirements, this architectural choice becomes no longer trivial to design, by keep-ing the relative power consumption down. This is the main reason and motivation for the thesis’ aim - to investigate on column-parallel readout structures.

1.4.3 Parallel readout

As mentioned in the earlier sub-section serial readout architectures set very high requirements on the data converter and do not happen to be very practical for high speed - high resolution applications. Instead, a good solution happens to be the parallel readout technique, Figure 1.6 gives a principal overview of the column-parallel concept. While such a solution aims to relax the separate ADC speed requirements, it also applies restrictions and additional complexity, with respect the size, power consumption of the converters as well as additional data feed-out difficulties.

Some practical considerations:

Size: In order to physically fit a data converter under every column, it is

required that its width matches with the pixel pitch (for a single side AD placement) or at least x2 the pixel pitch (for top-bottom placement). As pixel sizes vary between 2 and 10 µm, the geometrical shape of such con-verters is very disproportional, in some extreme cases it could reach (2 µm x 800 µm). This dis-proportionality influences circuit design, requiring the use of device splitting and careful parasitic resistance and capacitance esti-mation.

Power consumption: In parallel readout the power consumption of the

data converters becomes dominant, in particularly peak power consumption should be taken care of. The parallel current draw during readout can reach up to hundreds of miliamperes and the power drop over the supply rails can

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lead to loss of performance. Figure 1.7 provides an overview of the occurring effect. A D C A D C A D C V_in 1 Vin2 Vinn R R R R R R C C C D₁[0 : N ] D₂[0 : N ] D_n[0 : N ] V_vdd/clk/sig

Figure 1.7: Power supply / clock / control signal RC network model. Assuming that the converters are supplied with power from both sides, the highest voltage drop would occur in the central converters. If the peak power consumption and the power rails sizing have not been cross-correlated with the power supply ripple rejection and ADC stability, offsets between separate column regions can occur. Typically due to clock skew not all converters would end-up triggered simultaneously, however the propagation delay τp

and peak power consumption are the major parameters of consideration when designing the power grid.

Speed: The column-parallel data converter speed of an image sensor, is

dependent on the requirements of the sensor itself. A generalized formula for a rough converter speed estimation is introduced below:

τconv<≈

1

Hfs Nmencds

− Nme

τpixresτpixsig

2 (1.1)

Where H is the vertical resolution in number of pixels, fs is the required

frame rate, Nme is correlated to the number of multiple exposures (if any),

ncds is 1 or 2, depending on whether digital CDS is performed, τpixres and τpixsig are the pixel settling times during reset and signal readout.

1.5 Noise sources in CIS

During operation, various noise source influence the capturing process and these must be studied and taken into account while designing any part of the analog signal readout blocks of an image sensor. These noise sources can roughly be split into two sub-groups. Temporal noise sources, which’s main ignitor is the natural random movement of fundamental particles and interactions between them and spatial noise sources, which are generated by electrical circuit offsets and non-linearity.

The following Subsections 1.5.1 and 1.5.2 aim to give a brief overview of the two main noise sub-classes.

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1.5.1 Temporal noise sources

As discussed earlier-on the temporal noise sources are mainly caused by the nat-ural movement of electrons and their interactions with the atomic environment surrounding them. A classification including a brief introduction to the noise contributors follows.

1.5.1.1 Photon shot noise

The photon shot noise originates from the nature of the particle characteristic of light, which could be described by a statistical distribution. Photon shot noise is not technology nor design dependent therefore the designer’s control over it is limited. However it is directly proportional to the exposed junction area, as well as light’s intensity. Equation 1.2 defines the fundamental photon shot noise dependencies.

nps=

r Φ

h.νt.A.η (1.2)

Where Φ is the light’s intensity, h.ν is the photon’s energy, A is the exposed photo-diode area, t is the integration (exposure) time and η is the quantum effi-ciency of the semiconductor.

1.5.1.2 Dark shot noise

The dark shot noise is defined as the random fluctuations in the current magnitude of a reversely biased p-n junction. Or in other words the reverse current of the pixel’s photo diode. It is caused by the random thermal generation of electron-hole pairs in the semiconductor within the depletion region of the p-n junction as well as occasional electron tunneling. Figure 1.8 shows a band-diagram of a reversely biased p-n junction.

E

c

E

v

q(V

0

+ V

rev

)

e

−

Figure 1.8: Energy diagram of a reverse biased p-n junction.

The current density of a reversly biased p-n junction has been defined by Shockley and is given by:

Jrev=

W.ni.e

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Where the depletion region width is defined by W, the thermal generation time

τg and the intrinsic carrier concentration nifor the semiconductor. The

optimiza-tion of this noise source is usually not in the scope of the analog readout design, however it could be handled by temperature, semiconductor material choice, purity and lattice orientation.

1.5.1.3 Thermal noise

Thermal noise, also known as Johnson-Nyquist noise is generated by the thermal movement of charge carriers (electrons, ions or holes) in a conducting material at equilibrium. G v2 n i2 n R

Figure 1.9: Thermal noise definition.

Idealistically the thermal noise’s power spectral density is constant in ampli-tude throughout most of the frequency spectrum, only at very high frequencies above ~80 GHz its power stops following the classic definition of it which is:

v2

n = 4kBT R (1.4)

i2

n= 4kBT GB (1.5)

Where k is Boltzmann’s constant in J

K, T is the ambient temperature in degrees

Kelvin, R is the active impedance of the conductive material. Thermal noise is an inevitable part of every electronic circuit, and is one of the fundamental limiters in high precision designs.

1.5.1.4 kT C noise

The kT

C noise fundamentally originates from the thermal noise, but it is reffered as

the thermal noise on capacitors. If we consider a capacitor model with a certain capacitance and ESR as Figure 1.10 suggests.

The impedance of the equivalent circuit will be:

Z = 1 Y =

1

G+ jωC (1.6)

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G C

Figure 1.10: Capacitor and its internal parasitic conductance.

v_n2= 4kT 2π ∞ Z 0 1 G+ jωCdω = kT C (1.7)

We can see that the noise does not depend on the resistance, due to the fact that the noise and the bandwidth are inversely proportional to the impedance, thus they cancel each other.

kT

C noise is one of the fundamental limits of switched capacitor circuits and

in case with data converters, SC network’s capacitor sizes must be chosen with respect to the noise induced by them and the minimum SNR specifications.

1.5.1.5 1

f noise

1

f noise, also commonly referred in literature as pink or flicker noise. In contrast

with thermal noise, which’s amplitude is constant in the frequency spectrum, 1

f

noise has constant energy over the frequency spectrum. It appears in many phys-ical and biologphys-ical systems and is fundamental source is vaguely defined and not yet fully understood.

With respect to electrical systems it is characterized as the slow fluctuations in the physical materials, some literature sources describe it as a function of the distribution of kinetic igniting energies in atomic compositions. The influence of 1

f

noise in this work is covered in the next chapters, where we shall we it’s importance and methods proposed for suppressing it.

1.5.1.6 Random Telegraph Signal (RTS) noise

RTS noise, or also called popcorn or burst noise is a type of electric noise occurring in materials (semiconductors and some insulators) which’s bandgap energy is 0.1<5 eV. It is caused by sudden discrete-like voltage or current transitions, which could be as high as a few milivolts. With respect to the occurring frequency of these transitions, RTS noise is characterized as very low frequency noise, where noise transitions can last up-to a few tens of miliseconds.

The physical phenomenon inducing this type of noise is the discrete step-levels inside the semiconductor’s bandgap caused typically by impurities in the grown crystal structure. Figure 1.11 shows a visual representation of the phenomenon.

Due to the discrete energy levels inside the bandgap, charges can accumulate and stay at these energy levels for a certain time, before passing-over to the

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con-Ev Ec

EL1

EL2

trapped electrons

Figure 1.11: Band diagram with discrete sub-levels caused by impurities. duction band. This accumulation and sudden release of charges is the source of RTS noise. It is highly dependent on the purity of the semiconductor materials, however it is existent in every electronic circuit. With respect to image sensor applications, such discrete sub-energy levels in the pixel photo diode can vastly affect image readout, thus should be taken of consideration.

1.5.2 Spatial noise sources

Spacial noise sources are typically induced by process variations and mismatch between different sub-system components as well as the in-pixel circuitry. These can be shortly sub-classified as:

1.5.2.1 Dark current fixed pattern noise (FPN)

Dark current fixed pattern noise is caused by the pixel’s photo diodes mismatches. Dark current fixed pattern noise becomes very apparent at slow integration times and low external photon stimulation. Some methods of post-processing compen-sation of this noise source exist (masking offset reduction techniques), however it is not of major concern for analog readout circuitry design.

1.5.2.2 Fixed pattern noise caused by source follower mismatches

Identically to sub-section 1.5.2.1 the FPN caused by source follower, reset and transfer transistor switch mismatches, has the same effect on images, however it may be more dominant than dark current FPN at higher intensity scenes. Sim-ilarly, offset and gain mismatches would cause random spatial noise on the final image. Some post-processing offset/gain compensation techniques exist, however such compensation in imagers for mass-production becomes hardly performable due to practical difficulties in fast calibration.

1.5.2.3 Column fixed pattern noise (CFPN)

Column fixed pattern noise (CFPN), is a type of spatial noise source, which is induced by offset and gain mismatches in the column readout circuitry, typically

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the PGA and ADC. The absolute offset/gain mismatch value between columns for CFPN, in comparison with DCFPN should be much smaller and be kept lower than 1% typically. This is caused by the fact that the human eye is much more sensitive to long (row/column) mismatch variations, rather than random mismatched pixels.

Figure 1.12: Column ADC mismatch

(8-bit image) ±1 LSB. Figure 1.13: Column ADC mismatch(8-bit image) ±2 LSB

Figure 1.14: Column ADC mismatch

(8-bit image) ±4 LSB Figure 1.15: Column ADC mismatch(8-bit image) ±16 LSB

A Matlab script listed in Appendix C was written in order to simulate and reproduce the column ADC offset mismatch effects on an image. Figures 1.12, 1.13, 1.14 and 1.15 represent the visual effects of column FPN.

Column FPN induced by ADC/PGA offset can be suppressed by means of calibration or more advanced column multiplexing techniques. A short example of a column switching technique proposed by [28] is shown on Figure 1.16.

The idea behind column swapping is to switch the readout circuitry on every row readout for the purpose of averaging-out column mismatches. I.e. ideally if the column offset deviations follow a pattern of ∆max, ∆min, ∆max, ∆min, etc...

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0101 0101 0101 0101 0101 0101 0101 0101 0101 0101 0 1 2 n-1 n 0 1 2 n-1 n n swap control R O W D E C O D E R

Figure 1.16: Column switching technique for CFPN reduction.

1.6 Analog to digital converters in CMOS image

sensors

This section aims to briefly describe the commonly used ADC configurations in image sensors employing the column-parallel readout architecture. In addition the last subsection aims to present a more detailed overview of the Algorithmic or commonly known as Cyclic ADC.

As briefly discussed in Section 1.4, the column-parallel readout, relaxes the speed requirements over the ADC of high-resolution imagers. However, employing massive parallelism, rises-up the power consumption and area requirements over the column-parallel ADC. Chapter 2 will give a more descriptive overview of the forementioned problem.

Some of the data converters having most popularity within column-parallel readout sensors are enumerate-listed below and some of their advantages and dis-advantages for the current application are briefly presented.

1. Integrating (Ramp) ADC - probably the simplest with respect to device count. It is a popular choice within the current application, due to its com-pactness. As a disadvantage is the requirement of a very linear DAC used for the reference ramp. In addition its conversion time is signal dependent, thus a somewhat more complex control circuitry is required if full speed of the converter is to be utilized.

2. Successive approximation register (SAR) ADC - offers much faster conversion time (typically n times clocks for n bits), however its complexity with respect to devices and sub-systems is larger compared to the integrating ADC. A charge-redistribution-based DAC is makes the most common choice among SAR ADCs. The popularity of the SAR ADC among column-parallel

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readout image sensors is lesser, due to its difficulty of integrating all SAR sub-components into the column.

3. Sigma-Delta ADC - even though that the Sigma-Delta converters incor-porate very little analog-based components, it still classifies under the larger area converters, due to the complexity of the digital low-pass filtering and decimation circuitry. One of the popularly mentioned disadvantages of the Sigma-Delta converters among image sensors is the high clock speeds re-quired due to the high oversampling nature of these converters.

4. Pipelined ADC - also known as Sub-ranging ADC, resolves the output word in a number of steps, by using a flash-type Sub-ADC and uses a DAC to convert the resolved digital word to an analog voltage for subtraction and multiplication. The pipelined ADC can very roughly be listed between the SAR and Sigma-Delta ADCs with respect to average number of devices. Potential disadvantages may be the lower achievable resolution and higher power consumption as compared to SAR and Sigma-Delta. Yet, depend-ing on the number of stages these converters are still of interest in sensor applications.

5. Algorithmic/Cyclic ADC - Based on the Pipelined ADC concept, the cyclic ADCs have larger in-column implementation benefits as compared to pipelined converters, due to their compactness. As this thesis focuses on the Algorithmic ADC a further analysis follows in the next sections.

1.7 Algorithmic (Cyclic) ADC

The algorithmic also well known as cyclic ADC could be referred as an evolution of the pipelined ADC. It basically re-uses a single stage for performing all sub-conversions. Figure 1.17 shows a principal diagram of the algorithmic ADC.

Sub-AD φin MDAC RSD [1 :0] WORDOUT [12 :0] vAnalogIn φcycle x2 analog input

digitized analog signal residual signal

Sub-DA

partial result iteration loop

RSD to BIN Logic

Figure 1.17: A functional block diagram of a RSD Cyclic ADC.

Following the signal flow, first the signal is sampled and held for evaluation of the MSB (at φin and φcycle on). The sampled initial voltage value is evaluated

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by the Sub-ADC which typically is a 1.5bit flash ADC comparing the signal with two threshold values. The reasons standing behind the popular choices of 1.5 bits as ADC resolution are briefly presented in Subsection 1.7.1. The Sub-ADC’s decision is strobed by the RSD to binary logic and the decision magnitude is further fed to a Sub-DAC, which together with an analog summer resolve the residue (unresolved) voltage left by subtracting the DAC’s output from the fed-in voltage. The residue is amplified and fed-back again for further LSB resolvings. The cycles are repeated until the required resolution is obtained.

1.7.1 Redundant Signed Digit (RSD) error correction

tech-nique

The fundamental redundant signed digit representations are defined as numeri-cal systems, which use more bits to represent digits which have a few different representations. RSD representations typically use more than one bit for for rep-resenting digits. Within the data converters the RSD technique is used typically for compensation of errors which have occurred due to non-idealities.

The 1.5 bit RSD technique, first introduced by [9], as it may be hinted by the name uses 1.5 bits or three 2 bit binary states to represent a single bit, “00” → 0, “01” → +1, “10” → -1. Thus by using such encoding scheme a digit representation of +1, 0 or -1 is achieved. The subtraction, addition by one or zero allows for performing digital error correction during subsequent bit-resolvings. To make the algorithm clearer let’s consider a simple example aiming to show the basic principle of RSD digital error correction in a Cyclic ADC. Figure 1.18 shows the transfer functions of a 1 and 1.5 bit stages with marked effects from comparator decision offsets. ”10” ”01” ”00” Vin Vin Vout Vout offset clipped output Vref 1 4Vref 3 4Vref offset ”1” ”0”

only offsets over7 8and below 1

8will not be corrected

Figure 1.18: A comparative example between RSD and conventional ADC stages. A property of the 1.5 bit RSD configuration is that the stage does not have a mid-switch point, as also seen from Figure 1.18. Resolving one of three states on every cycle, effectively for 12 clock cycles 18 non-error corrected bits would be resolved, re-computing these redundant signed digits to unsigned binary would bring back 12 error-corrected bits. The error correction technique simply resolves into a 1 bit overlapping addition of all intermediately computed bits resolved on

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every cycle. A simple example showing an error correction addition for 6 bits is shown below: 10 00 01 00 10 10 ---1100110

It is important to mention that this type of error correction would provide to compensate only comparator offset errors. Errors induced by DAC signal sub-traction or the amplification by two would not be corrected by this technique. For coping with the rest of the error sources various techniques exist, some of them are described in Chapter 2, however none of them is as versatile as the RSD comparator offset error correction.

1.7.2 Switched-capacitor network MDAC structures

Probably the most key-accuracy-responsible component of algorithmic converters is the multiplying and subtraction module. The conventional ways of performing these basic signal conditioning operations using differential and times-X voltage gain amplifier are rather bulky and require multiple operational amplifiers, thus are not power and area efficient. A very popular solution, performing these two mathematical operations are the so called Switched-capacitor Multiplying Digital-to-Analog-Converter circuit structures (MDAC). The following section provides a basic overview of a few SC MDAC structures, comments on their advantages, weak spots and formulates a base for our further discussions and motivations of structural choice in Chapter 2.

1.7.2.1 Filp-around MDAC

One of the most popular in literature and probably representative structure, form-ing a residue subtraction and amplification by two is the one presented on Figure 1.19, commonly known as the “Flip-around MDAC”. For simplicity in its functional explanation it is presented in single-ended mode, however its fully-differential mode sibling is also largely used.

Starting from phase φ1, the input voltage is sampled onto capacitors Cf and

Cs, during the same phase the amplifier is configured as a unity gain buffer and as

indicated on Figure 1.19 the amount of charge stored in Cf and Cs would depend

on the ideality of the virtual ground node, which is directly dependent on the amplifier’s gain. In addition any offset of the amplifier’s input would be sampled onto the capacitors, where as we shall see in phase φs making the MDAC stage

ref

)

V

in

V

out

φ

₂

virtual ground

Figure 1.19: “Flip-around” multiplying digital to analog converter (MDAC).

q1&2(t) = Cf &s(t)

Vin(t) − Vvgnd− Vos

(1.8) During phase φ2 the capacitor Cf is connected in the feedback loop of the

amplifier, thus since ideally both charges (capacitor sizes) are equal, this leads to a x2 amplification factor. In addition during phase φ2any external voltage applied

to the top plate of Cswould alter the charge over Cs which will result in addition

or subtraction. The charge redistribution dependencies at phase φ2 and the final

transfer function, in their ideal forms are shown in Equations 1.9, 1.10 and 1.11 below. q1 t+T 2 = Cf Vout(t + T 2) − 0 (1.9) q2 t+T 2 = Cs(−Vref) (1.10)

And for the final transfer function:

Vout= Vin(Cf+ Cs) Cf + Cs Cf Vref (1.11)

The structure above is widely used in applications where amplifier offset can-cellation is required. However, a major drawback of the above-described structure is that is limited by the amplifier’s settling time during the sampling phase. The amplifier’s input and output dynamic ranges (common-mode voltages) should be kept as equal as possible, thus adding additional complication to the amplifier’s design. In addition amplifier reuse techniques as proposed by [12] [22] and [15], during the sampling phases are not possible, therefore leading to an increased

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power consumption in the general case. It is worth mentioning that the structure is insensitive to parasitics and its accuracy, apart from the opamp-requirements is also very dependent on the good matching between Cs and Cf. For the general

case the matching between Cs and Cf for a 12 bit data converter should be

be-low 0.1 %. Using MIM capacitors and advanced layout techniques this should be reasonable to achieve.

1.7.2.2 Modified filp-around MDAC

To relax the opamp’s bandwidth and dynamic ranges requirements, a similar to the above-described structure is also found in literature sources, widely known as “Modified flip-around MDAC”. Its principal schematic diagram in single-ended mode is presented on Figure 1.20

Cf Cs φ1 φ2 φ₁ Vr(0, ±Vref) Vin φ2 Vout φ₁ φ₁

Figure 1.20: “Modified flip-around” multiplying digital to analog converter (MDAC).

During sampling phase φ1 the capacitor charge current path is directly fed

into the ground via a switch. This practically means that the bandwidth of the sampling network is only dependent on the RC time-constant of the switches and the capacitors. The opamp is in idle state during phase φ1. As we will see, this

feature can be exploited and can allow for implementing opamp reuse techniques, as we shall see in the later sections and as it was proposed by [12] [15] and others.

1.7.2.3 Capacitor matching insensitive MDACs

One major drawback of the structures in the sections above is the requirement for high capacitor matching accuracy, there have been proposed multiple techniques in the early 90’s [19] [17] for achieving the same mathematical MDAC function, by not relying on capacitor sizes, but instead on capacitor voltage stacking techniques. To give a simple example Figure 1.21 shows one of the basic ideas.

This technique however, turns out to be dependent from the top-plate parasitic capacitances to ground, in addition depend on the amplifier’s gain (in SC integra-tor configurations as we shall see further) and have turned-out to be impractical

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2V

in

q = CV

in

Figure 1.22: A switched capacitor integrator - multiply by n structure. This SC integrator structure however, suffers from multiple limitations mainly related to the opamp’s high gain requirement and offset accumulation for every of the n cycles. Depending on what switches have been used in the sampling network additional charge injection, finite-on resistance and capacitor non-linearity effects might show-up to be significant.

1.7.2.4 A fully-differential MDAC with integrated analog CDS

A short research on more practical structures, showed that opamp and capacitor reusing techniques are common means for area and power consumption reduction. This sub-section’s aim is to present and briefly discuss a fully-differential MDAC with integrated analog CDS structure. A proposed by [6] cyclic A/D converter with integrated pixel noise and column-wise offset cancellation was investigated, as

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a potential option for the thesis project’s task. However this structure, as we shall see further, was not considered as a suitable variant due to a row of complexities introduced with the analog CDS nature of the structure. As within this section the aim is to give a brief overview of the studied structures, the following will be briefly presented as a reference.

C₂ C₅ C₁ C₃ C₆ C₄ V_{ref +} V_sig

Figure 1.23: Signal sampling phase.

C2 C3 C6 V_{ref −} C5 C1 C4 V_reset

Figure 1.24: Reset sampling phase.

C1 C3 C6 C4 C2 C5 Vref + Vref − φ3 φ4 within range to comparators to comparators over-range under-range

Figure 1.25: Feedback and amplification phases.

During the initialization phases, shown on Figure 1.23 and Figure 1.24, the signal from the pixel output is sampled on capacitor C2, while in the same phase the

opamp’s output and input differential nodes are connected to C3 and C6 (marked

withredcircles), this allows for storing the opamp’s offset into the capacitors for subtraction in the further phases.

The next initialization sub-phase samples the pixel reset voltage level on C2

causing a charge redistribution and thus CDS. During the same phase C3and C6

are connected in the amplifier’s feedback paths, thus performing offset subtraction. By the end of the initialization phases the CDS absolute value is sampled on C1

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Vout= Vsignal− Vof f set− Vref− Vreset (1.12)

The SC configurations on Figure 1.25 represent the actual cyclic mode (residue subtraction and amplification). During phase φ3, indicated in sky blue the

sam-pled voltage on C1 and C4 and their bottom plates are fed into the input of the

differential amplifier, their top plates however are connected to either Vref +, Vref −

or shorted, depending on the comparator’s decisions from the previously sampled output. After all settling, the result is sampled on C2and C5, further in time the

capacitors interchange role are perform the same operation again.

C3 and C6 are sampling the opamp’s offset and due to the changing polarity

of the residue voltage at every phase, ideally the offset should be canceled after infinite number of clocks. In reality for 12 bit conversion, the offset error should result in Vof f set/2N −1, this practically eliminates the offset effects.

As a summary of the studied architecture, it could be concluded that its major disadvantages stand on the large design complexity and “bulkyness” of the design. The structure relies on the matching of three pairs of capacitors, where two of them are used for temporal charge storage, after the preceding phases. Such structure relies on high clock accuracy and complex switching network design. Due to the above-mentioned facts, the structure was removed from the further review list.

1.8 Requirements over ADCs for CIS

The basic requirements of ADCs for CMOS image sensors may differ depending on the imager’s readout architecture and size with respect to its conversion speed. Parallel readout requires much slower conversion speeds, however as the level of parallelism is increased, power considerations become a major requirement as men-tioned in Section 1.4.3. If we move aside the power and speed requirements, the parameters identifying the conversion’s quality parameters can basically be split into static and dynamic performance parameters. The latter two are tightly con-nected to each other and aim to grade the converter’s linearity and thus distortion that it adds to the converted signal basing on two different fundamental domains. According to the IEEE-1241 “Standard for Terminology and Test Methods for Analog-to-Digital Converters” [1] the critical ADC parameters for image process-ing applications, as image sensors fall in are:

1. DNL (Differential Non-Linearity) - for acquiring sharp pixel-pixel edge detection

2. INL (Integtal Non-Linearity) - for correct brightness and thus color magnitude representation

3. SINAD (Signal to Noise and Distortion Ratio) - a similar represen-tation of all included DNL, INL and random noise

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4. Out-of-range recovery - at high speed imagers for guaranteeing a quick converter recovery if a measured signal’s magnitude has been less or over the ADC’s input range

5. Full-scale step response - to guarantee that no neighboring pixels will be influenced from the previous conversion, thus ensure there will be no blooming/leakage effect on the reconstructed image

6. Random noise - the converter’s random noise would appear as random spatial noise in the image

Defining the above-mentioned requirements strictly depends on the imager ap-plication, as the information from the analyzed image would depend on the area of implementation. Example, the human eye has a certain dynamic range and sensitivity to sensing discrete color levels, if however the sensor is up-to be used for an automated machine vision, these requirements would differ. For the current study we assume that the image sensor would be applied for human vision and all up-following subsections are aiming to give a brief overview of the basic per-formance parameter requirements and their influence on the reconstructed images for human vision.

1.8.1 Integral non-linearity

Integral non-linearity (INL) describes the difference between the amplitude of the fed-in signal with the quantized by the ADC signal. Very often for simplicity the measurement unit of INL has been normalized to the voltage level of one LSB and thus is represented in deviation with LSBs. In order to visually see the influence on INL over an image a simulation with a taken reference image, assuming it being much more linear had been performed. A random uniform generation of INL patterns with different magnitudes for an 8 bit image had been generated and embedded onto the reference image. While in reality INL has a few discrete levels of constantly growing and steeply falling non-linearity, here for simplicity we have assumed that a random uniform INL would provide us with acceptable to compare results. The script used for the performed simulations is listed in Appendix C. Figures 1.26, 1.27, 1.28, 1.29 provide with four test images with embedded INL with magnitudes of ±1, ±2, ±4 and ±8 LSBs.

The simulated INL on the images above show that the dotty effect induced by INL becomes clearly visible at magnitudes around 8LSBs for an 8bit image, which is roughly round 7 % of the entire range. For higher resolution converters this would imply that integral non-linearity which would appear to degrade a visible image would be even larger in absolute number of LSBs. Typically the integral non-linearity for human eye image applications could be relaxed up-to roughly 5 % of the entire quantization range. This is also the case with the described design in Chapter 2.

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0 50 100 150 200 250 −15 −10 −5 0 5 10 15

Random uniform INL distribution.

Code

Dev in LSB

Figure 1.26: Random uniform ADC INL (8-bit image) ±1 LSB.

0 50 100 150 200 250 −15 −10 −5 0 5 10 15

Random uniform INL distribution.

Code

Dev in LSB

0 50 100 150 200 250 −15 −10 −5 0 5 10 15 Random uniform INL distribution.

Code

Dev in LSB

0 50 100 150 200 250 −15 −10 −5 0 5 10 15 Random uniform INL distribution.

Code

Dev in LSB

1.8.2 Differential non-linearity

The differential non-linearity (DNL) is defined as the deviation of the converter code width from the ideal step width of the converter. ADCs having a DNL of < 1 LSB are monotonic and therefore have no missing codes. In certain literature sources however DNL of < 0.5 LSB is considered to be safe. A larger DNL results in missing codes along the range, which effectively causes a loss of information and would practically result as reduction of the available discrete image sub-levels for representation or the converter’s effective number of bits. The random granulated image artifacts are more prone to appear detectable to the human eye at higher than 1 LSB DNL. In addition apart of granulated image artifacts, DNL will have an effect on the image’s contrast. It is also of key importance how often through-out the digital code range such errors appear, as this will mean a larger loss of quantized sub-levels. Typically DNL should be kept lower than 1 LSB to ensure monotonicity and all code coverage of the ADC.

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1.8.3 Full-scale step response

The full-scale step response of the converter is the logged response of the ADC when an ideal input step voltage close to the reference voltage limits is being applied. Ideally the converter’s current decision should not be influenced by the previous, however in certain cases the converter could still need time to settle to reset thus its conversions may vary with the decisions taken at previous times. This appears to be an even more important parameter when considering digital correlated double sampling as the consecutive analog signal levels is expected to vary within a high range. A typical visual artifact in converter with poor full-scale step response would be a leakage effect.

1.8.4 Random noise

Ideally when a constant DC voltage has been applied to the converter’s input, every time a conversion is performed, it should provide with the same converted result. In reality however, due to various random noise sources, a converter may not always provide the same quantized value as the fore-converted ones. The random noise is defined as the deviation of the converted results with a constantly applied DC voltage in the middle of a code range. In the case of a CIS, the random noise induced from the ADC is typically kept at a lower magnitude in comparison with the random noise induced from the pixel. Chapter 3 would provide further clarifications on the random noise influence and its measurement.

1.9 ADC design requirements

The last section of this introductory chapter aims to provide insight on the ADCs performance parameter aims and initial specifications followed. Table 1.1 lists the main imposed ADC requirements for this thesis’ task.

Parameter Value Unit

Resolution 12 bits Sampling rate >130 kSps Integral Non-Linearity < 10 LSB Differential Non-Linearity < 0.5 LSB Power consumption < 300 µW Supply voltage 3.3 ±10% V Process node 0.18 µm Area - µm

Table 1.1: Main ADC specifications followed during the design study The provided specifications have been kept in mind during the design study presented in Chapter 2 and all explored techniques have been guided by the current ADC specifications. The required sampling speed has been set to comply with a

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readout speed of 60 frames per second on a 1080p vertical resolution sensor utilizing digital correlated double sampling.