Evaluation of Xilinx System Generator

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Examensarbete

LITH-ITN-ED-EX--2001/02--SE

Evaluation of

Xilinx System Generator

Petter Fandén

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LITH-ITN-ED-EX--2001/02--SE

Evaluation of

Xilinx System Generator

Examensarbete utfört i digital elektronikkonstruktion

vid SAAB Avionics AB i Järfälla, Stockholm

Petter Fandén

Handledare: Magnus Persson

Examinator: Hans Hjelmgren

Norrköping den 2001-11-21

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Datum

Date 2001-11-21

Avdelning, Institution

Division, Department

Institutionen för teknik och naturvetenskap Department of Science and technology

Rapporttyp Report category Licentiatavhandling X Examensarbete C-uppsats D-uppsats Övrig rapport _ ________________ Språk Language Svenska/Swedish X Engelska/English _ ________________ ISBN _____________________________________________________ LITH-ITN-ED-EX--2001/02--SE _________________________________________________________________

Serietitel och serienummer ISSN

Title of series, numbering ___________________________________

URL för elektronisk version

Titel Utvärdering av Xilinx Systemgenerator

Title Evaluation of Xilinx System Generator

Författare Petter Fandén

Author

Sammanfattning

Detta examensarbete är en utvärdering av Xilinx Systemgenerator och tillhörande blockset. Systemgeneratorn är en modul till Simulink som utvecklats för att generera VHDL kod från modeller i Matlab. Arbetet genomfördes vid SAAB Avionics AB i Järfälla, Stockholm. För att kunna undersöka Systemgeneratorns prestanda byggdes en modell av en frekvensanalysator, ofta använd i radarvarnare, i Matlab med hjälp av Xilinx blockset. Kod för samma modell togs under arbetets gång fram av ingenjörer på SAAB Avionics utan att använda Matlab och Systemgeneratorn. Koderna syntetiserades, analyserades och jämfördes efter genereringen. Frekvensanalysatorn innehåller en FFT en fönsterfunktion och en sorteringsalgoritm för att möjliggöra analys av två samtidiga signaler. Problem under genereringsfasen gjorde dock att modellen bröts ner till enbart en 16-punkters FFT.

Abstract

This Master’s Thesis is an evaluation of the software Xilinx System Generator (XSG) and blockset for Matlab. XSG is a module to Simulink developed by Xilinx in order to generate VHDL code directly from functions implemented in Matlab. The evaluation was made at Saab Avionics AB in Järfälla, north of Stockholm.

In order to investigate the performance of this new module XSG to Simulink, a model of a frequency estimator often used in digital radar receivers were implemented in Matlab using XSG. Engineers working at SAAB Avionics implemented the same application directly in VHDL, without using Matlab and the XSG. After generating code the results were synthesised, analysed and compared. The frequency estimator basically contains an FFT, a windowing function and a sorting algorithm used to enable analyse of two real signals simultaneously. There were however problems during generation of the VHDL code and the model had to be broken into smaller parts containing only a 16-point FFT.

Nyckelord

URL för elektronisk version

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MASTER’S THESIS University of Linköping, LIU, LITH & Saab Avionics AB

ABSTRACT

This Master’s Thesis is an evaluation of the software Xilinx System Generator (XSG)

and blockset for Matlab. XSG is a module to simulink developed by Xilinx in order to

generate VHDL code directly from functions implemented in Matlab. The evaluation was made at Saab Avionics AB in Järfälla, north of Stockholm.

In order to investigate the performance of this new module XSG to simulink, a model of a frequency estimator often used in digital radar receivers were implemented in Matlab using XSG. Engineers working at SAAB Avionics implemented the same application directly in VHDL, without using Matlab and the XSG. After generating code the results were synthesised, analysed and compared.

The frequency estimator basically contains an FFT, a windowing function and a sorting algorithm used to enable analyse of two real signals simultaneously. There were however problems during generation of the VHDL code and the model had to be broken into smaller parts containing only a 16-point FFT. The results of comparison in this report are based on models containing only this 16-point FFT and they show a small advantage for the System Generator according to the resource usage report generated during synthesis.

Designing models for generation using Xilinx Blockset can create a lot of wiring between components. The reason for this is that the System Generator and Xilinx Blockset today is a new tool, not completely developed. There are many components found in simulink, Matlab that could not be found in Xilinx Blockset, this is however being improved. Another problem is long time for simulation and errors during generation.

My opinion is that when used for smaller systems and with further development the System Generator can be a useful facility in designing digital electronics.

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TABLE OF CONTENTS

LIST OF ABBREVIATIONS ...IV PREFACE/ACKNOWLEDGEMENTS...VI MASTER THESIS PROJECT ASSIGNMENT... VII

1 INTRODUCTION... 1

1.1 OVERVIEW OF THE REPORT... 1

1.2 ELECTRONIC WARFARE... 1

1.3 RADAR WARNING RECEIVERS... 2

1.3.1 Parameters to Detect ... 3

1.3.2 Analog Receivers ... 4

1.3.3 Digital Receivers... 4

1.3.4 Wideband / Narrowband Receivers ... 5

1.4 XILINX SYSTEM GENERATOR WITH MATLAB... 6

2 THEORY ... 8

2.1 FAST FOURIER TRANSFORM... 8

2.1.1 Discrete Fourier Transform... 8

2.1.2 Mathematical derivation of the radix-2 FFT algorithm... 8

2.1.3 Butterfly ... 11 2.1.4 Memories ... 13 2.1.5 Scaling ... 14 2.2 WINDOW FUNCTIONS... 15 2.3 DIGITAL FILTERS... 17 2.3.1 FIR Filter ... 17

2.4 USING TWO REAL INPUTS... 18

3 IMPLEMENTATION... 20 3.1 BUFFERING... 20 3.2 WINDOWING FUNCTION... 21 3.3 FFT ... 22 3.3.1 Butterfly ... 22 3.3.2 DIF Structure... 24 3.4 SORTING FUNCTION... 26 3.5 EXPERIENCES OF IMPLEMENTATION... 26 4 SIMULATION RESULTS... 28 4.1 SIGNAL A ... 28 4.2 SIGNAL B... 30 4.3 EXPERIENCES OF SIMULATION... 32

5 GENERATION OF VHDL SOURCE CODE... 33

5.1 GENERATED CODE... 33

5.2 EXPERIENCES OF THE GENERATION... 33

6 SYNTHESIS ... 35

6.1 SYNTHESIS RESULTS... 35

6.2 EXPERIENCE OF SYNTHESIS... 35

7 CONCLUSIONS... 36

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LIST OF FIGURES... 38

APPENDIX A... 40

RESOURCE USAGE REPORT FOR XILINX BLOCKSET MODEL... 40

APPENDIX B ... 42

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List of Abbreviations

ADC Analog to Digital Converter AOA Angle of Arrival

BRI Burst Repetition Interval CFT Continuous Fourier Transform DFT Discrete Fourier Transform DIF Decimation in Frequency DIT Decimation in Time

ECCM Electronic Counter-Countermeasures ECM Electronic Countermeasures

ESM Electronic Support Measure EW Electronic Warfare FFT Fast Fourier Transform FIR Finite Impulse Response

FPGA Field Programmable Gate Array GUI Graphical User Interface

IF Intermediate Frequency

IFM Instantaneous Frequency Measurement IIR Infinite Impulse Response

LO Local Oscillator LUT lock up table

PA Pulse Amplitude POI Probability of Intercept PRI Pulse Repetition Interval PW Pulse Width

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RF Radar Frequency

RWR Radar Warning Receiver

SGGUI System Generator Graphical User Interface SNR Signal to Noise Ratio

VHDL Very High Speed Integrated Circuit Hardware Description Language QFT Quick Fourier Transform

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Preface/Acknowledgements

The purpose of this report is to evaluate the XSG and accompanying blockset. This has been done at the Electronic Warfare Department (TUUD) of SAAB Avionics in Järfälla. In this project a model of a digital radar receiver is built and the

corresponding VHDL code is generated and evaluated.

At Saab Avionics I would like to thank the TUUD Department, and especially my instructor Magnus Persson, my technical supervisor Anders Qvarfordt and Magnus Kamél.

I am also grateful to my supervisors at the University of Linköping, Carl-Magnus Erzell and Stig Björklund, as well as my examiner Hans Hjelmgren.

Petter Fandén, 2001-11-02. SAAB Avionics, Järfälla.

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Master Thesis Project Assignment

Modern radio communication and radar equipment use more and more digital signal processing, which means a digitalization of the signals at the intermediate frequency (IF) and further digital processing of the signal.

The main assignment of this Masters Thesis is to evaluate a new way of designing digital electronics by using the XSG and blockset for Matlab. In order to get a feeling of the usefulness of this new method, we decided to test it on a common and

comparatively complicated application, a frequency estimator used in a digital receiver for radar.

Today Saab Avionics develops a second generation of a digital receiver for radar. The design of digital electronics today begins with the building of a model in Simulink Matlab. The model is later implemented in a Field Programmable Gate Array (FPGA) from Xilinx using Very High Speed Integrated Circuit Hardware Description

Language (VHDL) source code.

A description of the digital receiver is today made in Simulink, Matlab. Simulink is a software package for modeling, simulating, and analyzing dynamical systems. According to Xilinx the development time of a new system design can be shortened significantly by using their System Generator and Xilinx blockset, see figure 1.1. A postulate is however to translate the model from Simulink Blockset into a model containing Xilinx Blockset.

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1 Introduction

In this chapter, a brief introduction is made to give the reader some background information about this report, radar receivers and the XSG.

1.1 Overview of the Report

This report is a Master’s Thesis dealing with the application of the XSG and Blockset. The first chapter contains an introduction about electronic warfare, radar warning receivers and XSG. Different types of receivers used in radar warning systems are presented.

Chapter two is a theory chapter studying the Fast Fourier Transform (FFT), and related operations. The model built in this project is based on these theories. Chapter three presents the model to be simulated, and from which the VHDL code will be derived.

In chapter four a report from the simulation is given.

Chapter five gives the results and experiences from code generation. The sixth chapter is a chapter about synthesis of the generated code.

Chapter seven collects and presents the conclusions made from the project.

1.2 Electronic

Warfare

Electronic Warfare (EW) systems are used in military actions to protect resources from enemy threats. These systems can be divided into three parts:

• Electronic Support Measure (ESM), which collects information on the electronic environment.

• Electronic Countermeasures (ECM), trying to disturb enemy systems

• Electronic Counter-Countermeasures (ECCM), trying to disturb the enemies ECM.

The ESM and ECCM are referred to as passive systems because they do not radiate electromagnetic energy, while the ECM is referred to as an active system since it tries to disturb the enemy system by sending electromagnetic energy. A functional

description of a radar system is presented in figure 1.2. Enemy sonar and noise from ships can be detected by an acoustic detection system operating at frequencies below 30 kHz. Communication intercept receivers are used to detect enemy communication

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signals usually operating below 2 GHz. Radar intercept receivers are used to detect enemy radar signals between 2 GHz and 18 GHz. The infrared intercept receivers detect plume from an attacking missile operating at wavelengths between 2 and 15 µm. Laser signals are also used to guide weapon systems like missiles.

Figure 1.2 Functional structure of EW systems.

These first groups are used for identification of the threat. Stealth and chaff are methods to avoid enemy radar. [1]

1.3 Radar

Warning

Receivers

A radar-warning receiver (RWR) is a receiving system used to identify, locate and display threat radar signals. These receivers can be used to protect airplanes, ships and ground-mobile vehicles. A RWR has an instantaneous field of view of 360 deg and covers a large part of the radar threat spectrum. The RWR reports any threatening radar signal very fast, in order to give the pilot the best information about his present situation. An important factor is the probability of intercept (POI), that must be 100 % or as close as possible. Most RWRs operates from four or more antennas. Their sights are aimed symmetrically around the airplane or the ship and covers 360 deg around the platform, see figure 1.3. The angle of arrival (AOA) can be computed by

comparing amplitudes from different antennas. The received signal power is used to calculate the distance to the radar. Signals to receive and detect can be signals from airplanes, ground based search radars or signals from robots or missiles.

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Figure 1.3: Airplane RWR using four antennas.

A communication receiver has an analog input signal and also an analog output signal in shape of a picture or some kind of noise. Radar receivers input are also analog, but the difference from a communication receiver is that the output from the radar

receiver always is digital. Conventional receivers convert the input radar frequency (RF) signal to a video signal and further on into digital pulse description words, see figure 1.4. [1] [2]

Figure 1.4: Block scheme over a conventional receiver.

1.3.1 Parameters to Detect

Parameters used for detecting are among others amplitude, frequency, pulse width, and time of arrival. This is shown in figure 1.5. Depending on the detected radar signal the pilot of an airplane gets information of the threat he is exposed to. An electronic library in the aircraft recognizing different signal properties makes it possible to identify anti-aircraft artillery, the lock-on phase of surface-to-air missiles, the track-while-scan mode of airborne sensors or, most alarming, the continuous wave signal of an incoming missile.

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• Angle of Arrival (AOA) • Carrier frequency (RF) • Pulse Width (PW) • Pulse Amplitude (PA)

• Time of Arrival (TOA)

Figure 1.5: Parameters to measure.

Other parameters measured are Pulse repetition interval (PRI) and Burst repetition interval (BRI). PRI indicates how often pulses arrive and BRI indicates how often groups of pulses arrive. [1]

1.3.2 Analog

Receivers

Analog EW receivers can be classified in six categories depending on their structure, Crystal Video, Superheterodyne, Instantaneous Frequency Measurement (IFM), Canalized, Comprehensive and Bragg cell receivers. The three last receivers can handle simultaneous signals but not the fist three ones. The problem with these receivers is the parameter encoder design, which can result in reporting erroneous frequencies. [1]

Analog receivers are often based on a technique using crystal video receivers converting radio frequency signals to video signals. Some problems with the crystal receiver are that the receiver destroys the carrier frequency and the phase information of the signal. Using a fast analog to digital converter will solve these problems, and is one reason for digitalization of receivers.

1.3.3 Digital

Receivers

Many receiver systems today consists of both wideband and narrowband receivers, and the signals are often filtered to remove noise from the input. They are being more and more digitalized thanks to very fast analog to digital converters (ADC) and that commercially available components are coming down in price and doubling their processing speed. A digital receiver down converts the input RF signal into an

intermediate frequency (IF), which then is digitalized by a high-speed analog to digital converter, see figure 1.6. Then a Spectrum estimator, containing FFT and filters, is used to convert the digital signals into the frequency domain. In the end of this line a

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parametric encoder is used to convert the spectral lines or spectral density from the FFT to a carrier frequency of the input signal. The very high sampling rates and quantizing ratios of the ADC provides efficient analysis of signals for emitter identification. The advantage of digital processing is that it is more robust because there is no temperature drifting, gain variation or dc level shifting as in analog signal processing.

Figure 1.6: Functional block scheme of a digital EW receiver.

The main problem in a digital receiver is to process the ADC output in a necessarily high rate with considerations to the Nyquist sampling criterion. One possible

approach is to multiplex the ADC output. If an ADC operates in a speed of 1000 MHz and the FFT has the possibility to operate in a speed of 250 MHz, the output of the ADC can be divided into four parallel outputs feeding an FFT chip placed at each output. Conventional multi-rate digital filter design can also be used, with many parallel filters to sort the signals. [1] [3]

At Saab Avionics the development of a digital receiver has been done since 1998, and today a second generation is being developed. The first digital receiver required more than one FPGA, which made the internal signaling process in the receiver

cumbersome. This and the development of new larger FPGAs was one reason for Saab Avionics to improve the digital receiver, and to build a newer version.

1.3.4 Wideband / Narrowband Receivers

One difference between a wideband and a narrowband receiver is that the signal to noise ratio (SNR) is much larger for a narrowband receiver. The difference in designing a narrowband receiver comparing to design a wideband receiver is that a narrowband receiver has an extra block processing the input. This block consists of a Local Oscillator (LO), a mixer and a band pass filter. According to the frequency of the LO a certain frequency range is mixed down to suit the pass band of the filter in an intermediate frequency, lower than the original frequency. And then the filter passes the desired frequency to further processing.

The first search strategy is dedicating one or several narrow band receivers to the search function, sweeping at maximum rate and handling-off signals to set-on receivers for better analysis. The search receiver usually has a wider bandwidth then the set-on receivers. A processor collects information about found frequencies etc.

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from the search receiver and assigns the set-on receiver to examine interesting frequencies closer. Figure 1.7 represents a block scheme of this receiver.

Figure 1.7: Block scheme over search strategy using narrowband search receiver.

The second strategy is to change the narrowband search receiver into a wideband search receiver and to determine all frequencies of all signals with this and then perform more detailed research with narrowband set-on receivers. The wideband receiver can be an IFM receiver, a compressive receiver or a Bragg cell receiver measuring only frequencies. Then the procedure is identical to the first strategy, see figure 1.7. [1] [4]

1.4 Xilinx System Generator with MATLAB

The XSG is used to generate VHDL source code from Xilinx Blockset in the MATLAB environment. Blocks from the Xilinx blockset can be implemented in Simulink models and are simulated in the same way. After simulating the model in Matlab, VHDL code, cores that are design entities of functions, and test vectors for verification help can be generated by the XSG, accordingly to the user defined system parameters. Xilinx Blockset consists of five basic groups of blocks:

• Basic elements containing blocks like System Generator Graphical User Interface (SGGUI), Black Box, Converter, Multiplexer and Delay etc. • DSP containing FFT and FIR blocks.

• Math containing functions like adder, subtractions, inverter and shift etc. • MATLAB I/O used to create interfaces between blocks from Xilinx Blockset

and blocks from other blocksets used in Simulink. • Memories like ROM and RAM.

The block SGGUI is used to generate VHDL code. This block is placed on the

Simulink project sheet and when activated, code is generated according to the defined system parameters. The translation software of the XSG is invoked from Simulink and provides an interface to Xilinx FPGA software. This interface translates the model to VHDL code and consists of a netlister, a mapper and a testbench generator, see figure

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1.8. The netlister extracts a hierarchical representation of the model’s structure annotated with all the element parameters and signal data types and the mapper analyzes the elements in the hierarchy and creates VHDL code, describing the design. A testbench is used to control the function of the generated system and to report any discrepancies. These three steps are made when running the XSG.

The XSG also uses the Xilinx product Core Generator, which provides the user with a catalog of ready-made functions ranging in complexity from simple arithmetic

operators such as adders, accumulators and multipliers, to system-level building blocks including filters, transforms and memories. If the Core Generator is not used, the mapper initiates a reference to a parameterized, synthesizable entity in a synthesis library or user supplied model. Some additional inputs and outputs are also added for desired control signals not used in Simulink.

Alteration of a design might be necessary to achieve a properly working block since each block only is given default behaviour. This is called control design in figure 1.8. FPGAs suitable for generated code are Xilinx Virtex™/E, Virtex™-II, and Spartan®-II.

Figure1.8: System Generator flow diagram.

A component called Xilinx Black Box gives the ability to use extra functions in

designs. This can be used if a special block is not represented in the ordinary library of blocks. [5]

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2 Theory

Building a model of a frequency estimator in a digital receiver requires some necessary theory. This chapter will guide the reader through the most important theorems used building a model of an FFT. Some related operations are also presented.

2.1 Fast Fourier Transform

There are many instances where signal processing involves the measurement of frequency spectra in signals, either by calculating the Discrete Fourier Transform (DFT) or the more efficient Fast Fourier Transform (FFT). [6]

2.1.1 Discrete Fourier Transform

The basic concept of the Fourier Transform is that every periodical function in the time domain can be represented by an infinite number of sinusoidal functions. The Continuous Fourier Transform (CFT) is defined in equation 2.1.

) 1 . 2 ( ) ( ) ( 2

∫

∞ ∞ − − = _x _t _e j ft f X π

The DFT, defined in eq. 2.2 is used to implement the CFT when the input signal is in digitalized form, and it is one of the most powerful ways to analyze digital signals.

) 2 . 2 ( ) ( ) ( 1 0 / 2

∑

− = − =N n N nk j e n x k X π

The DFT procedure is often used to determine the harmonic, or the fundamental frequency, of a discrete signal sequence. The FFT algorithm uses only O((N/2)log2 N)

complex multiplications compared to the DFT that has to perform O(N2) complex multiplications.

2.1.2 Mathematical derivation of the radix-2 FFT algorithm

In 1965 Cooley and Tukey introduced an efficient way, later named the FFT, to implement the DFT. The most popular FFT algorithm is called the radix-2 FFT, and requires a size of the FFT that is a power of two. [6] A derivation of the radix-2 FFT starts with a separation of the input data sequence of eq. 2.2 into two parts based on

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even and odd index elements. This gives us:

) 3 . 2 ( ) 1 2 ( ) 2 ( ) ( ) 1 2 ( 2 1 2 0 1 2 0 ) 2 ( 2 N k n j N n N n N k n j e n x e n x k X + − − = − = − ⋅ + + ⋅ =

∑

π

∑

π

The constant phase angle is moved outside the second summation:

) 4 . 2 ( ) 1 2 ( ) 2 ( ) ( ) 2 ( 2 1 2 0 2 1 2 0 ) 2 ( 2 N k n j N n N k j N n N k n j e n x e e n x k X π π π − − = − − = − ⋅ + + ⋅ =

∑

To simplify this expression we use WN = e-j2π/N to represent the complex phase angel factor that is constant with N and observe that WN2 = WN/2 since e-j2π2/N = e-j2π /(N/2). This gives the expression:

) 5 . 2 ( ) 1 2 ( ) 2 ( ) ( ₂ 1 2 0 1 2 0 2 nk N N n k N N n nk N W x n W W n x k X =

∑

⋅ +

∑

+ ⋅ − = − =

The radix-2 algorithm has the benefit that the upper half of the DFT easily can be calculated once the lower part already has been calculated. To prove this consider the X(k+N/2) output according to equation 2.5. This gives us:

) 6 . 2 ( ) 1 2 ( ) 2 ( ) 2 / ( ( /2) 2 1 2 0 ) 2 / ( 1 2 0 ) 2 / ( 2 Nnk N N n N k N N n N k n N W x n W W n x N k X + − = + − = + ₊ ₊ _⋅ ⋅ = +

∑

The phase angle terms is now simplified, because W ( /2) can, for any n, be written:

2 / N k n N + ) 7 . 2 ( 1 ₂ 2 2 2 2 / 2 2 2 2 / 2 / 2 / ) 2 / ( 2 / nk N nk N n j nk N N N n j nk N nN N nk N N k n N W W W e W e W W W + = ⋅ = ⋅ − π = ⋅ − π = ⋅ =

And the so-called twiddle factor or the phase can be written:

) 8 . 2 ( ) 1 ( 2 / 2 2 / ) 2 / ( k N k N j k N N N j k N N N k N N k N W W W e W e W W W + = ⋅ = ⋅ − π = ⋅ −π = − =−

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The radix-2 algorithm makes use of the fact that the twiddle factor has an inherent symmetry as shown in eq. 2.8 and that it is periodic, i.e WNk = WNk+N. This is also shown in figure 2.1

Figure 2.1: Symmetry and periodicity of the twiddle factor for N=8.

Hence, the lower and upper parts can be calculated from two slightly different expressions: ) 9 . 2 ( ) 1 2 ( ) 2 ( ) ( ₂ 1 2 0 1 2 0 2 W x n W a W n x k X nk N N n k N N n nk N + + ⋅ ⋅ =

∑

− = − = ) 9 . 2 ( ) 1 2 ( ) 2 ( ) 2 / ( ₂ 1 2 0 1 2 0 2 W x n W b W n x N k X nk N N n k N N n nk N − + ⋅ ⋅ = +

∑

− = − =

The similarity between the equations can easily be seen, if written in a simpler way:

) 10 . 2 ( ) ( ) ( ) 2 / ( ) 10 . 2 ( ) ( ) ( ) ( b k Z W k Y N k X a k Z W k Y k X k N k N − = + + =

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These equations can then be implemented as shown in figure 2.2. During the calculation of the twiddle factor we make use of the relations from eq. 2.8. [6] [7]

Figure 2.2: FFT implementation of an N-point DFT using two N/2-point DFTs.

2.1.3 Butterfly

To implement an FFT in firmware like VHDL or in software the usage of butterflies is very efficient. There are basically two different types of butterflies used for

implementation of the radix-2 FFT, these are called decimation in time (DIT) and decimation in frequency (DIF).

2.1.3.1 Decimation in time

In the radix-2 DIT FFT algorithm the process passes through a total of M stages where N=2^M with N/2 butterflies per stage. N is the number of points in an FFT and gives the resolution. This means that an 8-point FFT passes through 3 different stages, and uses 12 butterflies. A butterfly is actually a 2-point DFT, shown in figure 2.3 and more simplified in figure 2.4.

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Figure 2.4: Simplified graph of a Radix-2 DIT FFT butterfly.

Decimation in time algorithm is based on subdividing the input data into its odd and even components. The case with an 8-point FFT makes a butterfly pattern shown in figure 2.5, where the twiddle factor ranges from W80 to W83 because the index k ranges from 0 to 3. Notice, this k aims to the variable in the twiddle factor and not to the index in the DFT equation. There are some special properties of the FFT that are important to mention. As seen in figure 2.5, the bits are reversed at the input. This is a direct result of the radix-2 FFT. Reversed bit order is shown in Table 2.1.

Normal order of index n Binary bits of index n Reversed bits of index n Bit-reversed order of index n 0 1 2 3 4 5 6 7 000 001 010 011 100 101 110 111 000 100 010 110 001 101 011 111 0 4 2 6 1 5 3 7

Table 2.1: Normal order and bit-reversed order.

Figure 2.5 has bit-reversal inputs and in in-order outputs, but this can be changed by swapping x(4) with x(1), and x(6) with x(3).

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The outputs of the DIT butterfly are given by:

) 11 . 2 ( * * x W y y x W y x k N k N = − + =

2.1.3.2 Decimation In frequency

The other derivation of FFT that leads to a butterfly structure is decimation in frequency (DIF). As stated in section 2.1.2.1 decimation in time is based on

subdividing input data into odd and even parts. Decimation in frequency is founded upon calculating the odd and even output frequency samples separately. Figure 2.6 presents differences between DIT and DIF.

Figure 2.6: Alternate FFT butterfly notation: (a) decimation in time, (b) decimation in frequency.

The outputs of the DIF butterfly are given by:

) 12 . 2 ( ) ( * * x y y W x y x k N − = + =

2.1.4 Memories

In the butterfly implementation, some registers are necessary as memories. Here there are two different categories, in-place FFT algorithms and double-memory FFT

algorithms. The in-place category of FFT algorithms uses the same set of input registers as output registers for holding results. No intermediate storage is necessary.

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An N-point FFT in this category needs 2^N memory locations. The double-memory category does not use the standard butterfly and requires 4^N memory locations. The advantage of this category is that data routing and memory access control is much easier. [6]

2.1.5 Scaling

In computation of an FFT scaling is necessary to prevent overflows. Starting from the general equation of an N-point DFT, application of Parseval’s theorem gives:

) 13 . 2 ( | ) ( | 1 ) ( 1 | ) ( | 1 ) ( 1 0 1 0 2 2 1 0 1 0 2 2

∑

− = − = − = − =     =      = N k N k N n N n k X N n x N N or k X N n x

This means that the mean-squared value of X(k) is N times that of input x(n). Working with fixed-point arithmetic without appropriate scaling may cause overflows. The maximum magnification of a DIT implementation is 1+sin(45)+cos(45), i.e. 2.414, because of the possibility of having complex input signals and twiddle factor. This worst scenario happens if the twiddle factor for a butterfly is represented by for example W81 = 0.707+0.707i. If we use x* part of eq. 2.11 for this specific case we get: Im Im Re Re Im Im Im Re Im Re Im Re 414 . 1 * 707 . 0 707 . 0 707 . 0 707 . 0 * ) )( 707 . 0 707 . 0 ( * ) 14 . 2 ( * iy ix x x y iy iy y ix x x i y y i ix x x y W x x RE k N + + = − + + + + = + + + + = + =

If the input imaginary signals of x and y both are 1 the output signal will become 2.414. The maximum magnification using a DIF implementation is 2.828, since the twiddle factor affects only the y output signal, see eq. 2.12, but involves both inputs x and y.

To avoid the possibility of overflow each stage of the DIT FFT is scaled down by a factor of 2. Apart from that, the input signal is also scaled down by a factor 1.207 in the case of a DIT implementation and the output signal is scaled up with the same factor. Scaling input and output signals are only necessary when working with both real and imaginary input signals. [7]

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2.2 Window

functions

The output from a DFT can be incorrect if the input signal not fulfills certain

requirements. One of these requirements is the Nyquist sample theorem. Another one discussed here is an unmatched time interval. In the time domain the input signal is windowed by a rectangular function, containing N data points from n=0 to N-1. If a periodic window matches the signal, the input to the FFT component will appear to come from a continuous signal, and the FFT will report two peaks see figure 2.7a. Two peaks since a frequency bin for every peak shows a mirroring peak also.

Figure 2.7a: Time and frequency scope of a matching window.

If on the other hand the signal does not match the window, it does not appear to come from a continuous signal and in the frequency domain there will be several peaks, this can be seen in figure 2.7b. The added spectrum lines are caused by the sharp

discontinuity in the input signal. This sort of truncation in the time domain is equivalent with convolving in the frequency domain, and is often referred to as the leakage effect. To minimize the disturbance, one way is to use a window that reduces the amplitudes at the end of the window, where the mismatch occurs.

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Using a rectangular window cannot do this, but with a window shaped like a cosine, the signal will result as in figure 2.8. Cosine windows can also be raised to a higher order of a, and the formula is:

) 15 . 2 ( ) 2 / ( cos ) ( = _ − _ N N n n w a π

If a = 2, the window is referred to as a Hanning window.

Figure 2.8: Signal filtered by a cosine filter.

The frequency domain response will have the shape of figure 2.9. In this signal no mirroring is shown.

Figure 2.9: Frequency bin of a Hanning window.

Another more frequently used method to handle the leakage effect is through

convolution. Convolving the signal with a sinc function, in the frequency domain, will bring many side lobs appearing in the frequency domain. For a rectangular window matching the period of the input sinusoidal signal, the spectrum lines in the frequency domain will match the zeros in the sinc function, and there will not be any side lobs.

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In other cases a window with low side lobs in the frequency domain is used to reduce the output side lobs. The cosine window is one example of a window with lower side lobs in the frequency domain. There is though one problem, decreasing the amplitudes of the side lobs brings that the width of the main lobe will increase. A wide main lobe width brings poor frequency resolution, while a narrow one will bring good frequency resolution. This is a trade off to be considered selecting a suitable window. [1]

2.3 Digital

filters

Filtering is a process in the time-domain that changes the signal original spectral content. Often the change is a reduction of unwanted input components, examples are when filters allow certain frequencies to pass and block other frequencies. There are two favors of digital filters, Finite Impulse Response (FIR) and Infinite Impulse Response (IIR) filters. [6] The difference between these is that IIR filters depend on both input and output signals while a FIR filter does not depend on the output signal.

2.3.1 FIR Filter

FIR filters are also called non-recursive filters, because they only use current and past input signals. Sending an impulse as input results in finite output signals, and

therefore the name is finite impulse response. There are two factors to consider calculating a signal frequency response, M, the number of taps or input signals to consider, and h(k), the specific values used for multiplication coefficients. The general equation for a M-tap FIR filter the n:th output is:

) 16 . 2 ( ) ( ) ( ) ( 1 0

∑

− = − =M k k n x k h n y

This convolution equation is applied to digital FIR filters. Another important term is the impulse response. This is the filters output sequence in the time-domain, when the input is an impulse. A filter’s impulse response is synonymous with the FIR filter coefficients h(k). This gives us the opportunity to improve the performance of the filter, i.e. how well the filter passes wanted signals and attenuates undesired signals. This performance can be evaluated by determining the shape of the frequency-domain response. The DFT of a convolution of a filters impulse response and an input

sequence is equal to the product of the spectrum of the input sequence and the DFT of the impulse response. The relation is stated in the expression:

) 17 . 2 ( ) ( ) ( ) ( * ) ( ) (n h k x n H m X m y IDFT DFT ⋅    ←   →  =

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Where IDFT is the inverse DFT, and H(m) and X(m) are DFTs of h(k) and x(n). The conclusion is that convolution in the time-domain is equivalent to multiplication in the frequency-domain. The product between H(m) and X(m) is the DFT of the filter output. H(m) is also called the filter frequency response.

2.4 Using two real inputs

An FFT is usually designed to process data from a signal consisting of a real and an imaginary part. This is however not easy cause it is difficult to collect complex data with well-balanced in-phase (I) and quadrature phase (Q). One way of using the FFT is to use the real data as an input to the FFT, but instead of using the imaginary part of the data, putting zeros to the imaginary input of the FFT. Another more efficient way is to collect real data from two different signals to the inputs of the FFT, which will be done building the frequency estimator model in this assignment. This gives the

possibility to analyze two signals simultaneously. If the real data is expressed as x(n), the k:th component can be expressed as:

) 18 . 2 ( ) ( ) ( 1 0 / 2

∑

− = − =N n N nk j e n x k X π

And the (N-k):th component as:

) 19 . 2 ( ) ( ) ( ) ( 1 0 / 2 1 0 / ) ( 2

∑

− = − = − − ₌ = − N n N nk j N n N k N n j _x _n _e e n x k N X π π

The only difference between these expressions is the minus in the exponent. From this follows that X(k)=X(N-k)* where * symbols the complex conjugate. This can also be expressed as:

[

]

[

]

[

( )

]

Im

[

( )

]

(2.20) Im ) ( Re ) ( Re k N X k X k N X k X − − = − =

If another signal, beside from x(n), is added called y(n) with the same number of data points a complex function z(n) can be expressed such that:

) ( ) ( ) ( ) 21 . 2 ( ) ( ) ( ) ( k jY k X k Z n jy n x n z + = + =

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Written in another way this is:

[

]

[

]

[

]

[

]

[

]

[

]

[

]

[

]

[

]

[

]

[

]

[

( )

]

Im

[

( )

]

Re

[

( )

]

Im ) 23 . 2 ( ) ( Im ) ( Re ) ( Re ) ) ( Re ) ( (Im ) ( Im ) ( Re ) ( ) 22 . 2 ( ) ) ( Im ) ( (Re ) ( Im ) ( Re ) ( k Y k X k Z k Y k X k Z or k Y j k X j k Y k X k Z k Y j k Y j k X j k X k Z + = − = + + − = + + + =

The real parts of X(k) and Y(k) are symmetric with respect to (N-1)/2, since x(n) and y(n) are real functions, while the imaginary parts are asymmetric. By using the expressions 2.22 and 2.23 we can write the second half of the k components in terms of the first half. [1]

[

]

[

]

[

]

[

]

[

]

[

]

[

]

[

]

[

( )

]

Re

[

( )

]

Im ) ( Re ) ( Im ) ( Im ) ( Im ) ( Re ) 24 . 2 ( ) ( Im ) ( Re ) ( Re k Y k X k N Y k N X k N Z k Y k X k N Y k N X k N Z + − = − + − = − + = − − − = −

The desired result can now be calculated using these expressions:

[

]

[

]

[

]

[

]

[

]

[

]

[

]

[

]

[

]

[

]

[

]

[

]

2 ) ( Re ) ( Re ) ( Im 2 ) ( Im ) ( Im ) ( Re 2 ) ( Im ) ( Im ) ( Im ) 25 . 2 ( 2 ) ( Re ) ( Re ) ( Re k Z k N Z k Y k N Z k Z k Y k N Z k Z k X k N Z k Z k X − − = − + = − − = − + =

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3 Implementation

The digital receiver Saab Avionics is developing has an FFT operation as one of its central parts. To find out more about Xilinx Blockset and the System Generator, an existing model of the FFT operation was translated to a model containing blocks from Xilinx Blockset. This model is presented in figure 3.1 and it function is to calculate the frequency spectra of two real signals.

Figure 3.1: Model in Matlab over a FFT operation.

Two signals are first converted from analog to digital signaling. After this, a buffering is made for each signal to convert them to parallel signals. The buffers have an

overlap so the same values are used more than one time. After paralleling the signals, they are filtered in a windowing function. This function is based on a FIR filter, with coefficients calculated using Matlab Filter Design. The filters mix four of the parallel input signals into one output signal. The part used to detect the signals is an FFT, this component investigates the spectrum of the signals. The FFT component is based on a Radix-2 algorithm, and built up with butterflies, see chap 2. The components FIR filter and FFT, available in the Xilinx Blockset, are not used in this model, because of the required speed of the system by using parallel signals. The following block sorts out the real and imaginary parts of the signals and is necessary if two signals are analyzed simultaneously. The Simulink model also contains blocks necessary to verify the model. Such blocks are scopes that give a picture of the output and sources giving input signals etc. These blocks are only used to get a verifying picture and will not be analyzed here. They will though be used in the Xilinx Blockset model also since the Xilinx blockset block gateway makes it possible to mix blocks from these blocksets.

3.1 Buffering

For a pilot in a plane it is very important to know which signals are sent against the airplane. This information sometimes has to reach the pilot very fast to give a good

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possibility to avoid missiles or other threats. Therefore the signals received by the antennas are paralleled. The ADC samples the signal with a frequency fs, the

digitalized signal then passes delay elements with a latency of one. Sample and hold elements holds signals between the delay elements with a desired frequency and parallels the signal.

Figure 3.2: Paralleling the signal

3.2 Windowing

function

After paralleling the signal inputs they are filtered in a windowing function. This is done to avoid the leakage effect, se more in chapter 2.2. The window used in this model is a FIR filter with coefficients calculated by Matlab Filter Design. The coefficients are stored in a text file and loaded to the model using a Matlab m-file. Four input signals are multiplied with their respective coefficient and after this they all are added together into one output. This is one way to increase the speed of the FFT.

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As seen the windowing function adds four inputs into one, this gives an approximation, making it possible to use a smaller DIF FFT.

3.3 FFT

The FFT is the central element in the model. It has the function of investigating the spectrum of the input signals. The FFT is based on a Radix-2 algorithm. This choice was made since it is easy to find documents describing Radix-2 and since it has been used earlier at Saab Avionics. To build this FFT butterflies are used as described in chapter 2. A manually written FFT at Saab Avionics uses a DIF structure, and in order to make a correct comparison this method will be used here also.

3.3.1 Butterfly

The representation of a DIF Radix-2 butterfly is described in figure 3.4, where WNk is the twiddle factor. The twiddle factor makes it easy to build a butterfly component using adders, subtractors and multipliers. This is one advantage of using an FFT to represent a DFT. X and Y consists of both real and imaginary parts, se eq 3.2. However in this FFT only real parts are used as inputs, see chapter 2.3, for details.

Figure 3.4: DIF butterfly

The expressions describing x* and y* are:

) 1 . 3 ( ) ( * * x y y W x y x k N − = + =

The twiddle factor, WNk however consists of both a real and an imaginary part, depending on the value of N and k as shown in figure 2.1. Furthermore, the inputs to the butterfly has to be described with real and imaginary parts. This gives:

Im Re Im Re (3.2) jy y y jx x x jW W W + = + = + =

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The outputs from a butterfly will also consist of real and imaginary part and x* can now be expressed as:

Im Im Im Re Re Re * ) 3 . 3 ( * y x x y x x + = + =

And the output y* is a bit harder to express but is evaluated here:

) ( ) )( ( )) ( ) )(( ( ) 4 . 3 ( ) )( ( * Re Im Re Im Im Re Im Re Im Im Im Im Re Re Re Re Im Im Re Im Im Im Re Im Im Re Re Re Im Re Re Re Im Im 2 Re Im Im Im 2 Re Im Im Re Re Re Im Re Re Re Im Re Im Re Im Re Im Re Im Re Im Re Re Re Im Re y W x W y W x W i y W x W y W x W y W y iW x W x iW y iW y W x iW x W y W i y iW x W i x iW y iW y W x iW x W iy y ix x iW W iy y ix x iW W y x iW W y − + − + + − − = + − − + − − + = − − + + − − + = − − + + = + − + + = − + =

The real part of the outsignal y* is presented as:

) 5 . 3 ( ) ( ) ( ) 5 . 3 ( ) ( ) ( * Im Im Im Re Re Re Im Im Im Re Re Re Im Im Im Im Re Re Re Re Re b y x W y x W or a x y W y x W y W x W y W x W y − − − = − + − = + − − =

And the imaginary part:

) 6 . 3 ( ) ( ) ( * Re Re Im Im Im Re Re Im Re Im Im Re Im Re Im y x W y x W y W x W y W x W y − + − = − + − =

Taking these expressions for x* and y* and building a butterfly component in Matlab using blocks from Xilinx blockset will look like in figure 3.5. It is very important to have good control over the ports in and out from the butterfly because they are going to be connected with other butterflies. If the expression in eq. 3.5b is used the

subtractions xRe-yRe and xIm-yIm can be found in both real and imaginary equations for

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Figure 3.5: Butterfly built of adders, subtractors and multipliers.

To make the model easier to handle and to work with, this butterfly is converted to a subsystem with four inputs representing real and imaginary parts of x and y. In the system there are also four outputs representing real and imaginary parts of x* and y*.

Figure 3.6: Butterfly block.

3.3.2 DIF Structure

The chosen structure is a DIF structure. This choise sets the structure to connect the butterflies into an FFT. Another thing to consider is the bit input order and output order. In this case bit reversed input order are chosen and normal output order. This to simplify the handling of the output data and to be able to have control over the

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Figure 3.7: Schematic scheme over a DIF structure with reversed input order and normal output order.

The twiddle factor is important and in the schematic picture it is also described how it should be implemented. The FFT consists of stages of butterflies connected to

eachother. Butterflies with the same twiddlefactor are gathered in a new block. This to make it easier to write the twiddlefactors, which is done by a Matlab program written in an m-file. The portnumbers to the blocks controls the connections between the butterflies. Setting these numbers can also be facilitated by using an m-file program. Between every stage d-flip-flops are placed to control the signal rate and to pipeline the system for a faster throughput. This places the FFT in the cathegory with in-place memories, where the same registers are use at the input to one butterfly as at the output of another one. With this requirements an 8-point FFT will look like in figure 3.8. An important thing to remember is that the output from a butterfly consists of a longer bit-width than the input. Therefore the numbers of bits used in the butterflies increases for every stage, to avoid overflow. This can be studied further in chapter 2.1.5 about scaling.

Figure 3.8: Implementaion of a 8-bit FFT using butterflies. Between every butterfly stage there are registers used as memories for pipelining of the system.

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3.4 Sorting

function

To be able to analyze two different independent signals using the FFT a sorting function has to be implemented, this is based on the theory in chapter 2.4. In this model four different blocks is used to achieve this. These blocks are implemented according to the equations 2.26, representing real and imaginary parts of two different signals. The blocks used are adders and shifting, connected as in figure 3.9

Figure 3.9: Sorting function blocks.

In the implementation there are four different sub blocks, used to sort out real and imaginary parts of the two input signals.

3.5 Experiences of implementation

Modeling systems in Matlab is a common and popular method to simulate and verify systems. Building models using Xilinx Blockset is just like building models using other blocksets in Matlab. Learning how the program works is not a problem if the user has any kind of experience of using Matlab earlier.

There are however some restrictions and some things to be considered. Not all blocks from Simulink are available in Xilinx Blockset. This problem can often be solved by building blocks from simpler components like adders and logical components. But building a component this way will take longer time than it would if the component was available in the Blockset. The gateway cannot translate an array of signals into signals suitable for Xilinx Blockset, which also can force the designer to build models of existing blocks. The XSG is however updated continually, giving better

performance and more blocks in Xilinx blockset.

Modeling in Xilinx Blockset also demands a calculation of the necessary bit width. Unlike in Simulink, the bit widths in Xilinx Blockset are not floating. This requires settings of bit width and binary point for every block output, and also for constants used in blocks.

A large model consisting of a large number of components like an FFT built of butterflies can be hard to control for the reason of its size. One way to simplify this is to make subsystems containing suitable parts of the design. In the example in this

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project every butterfly is a subsystem. Every stage of the implementation of the FFT also contains subsystems to make it easier to control the twiddle factor and to simplify the connecting between butterflies. Settings can be done, by writing a Matlab program in m-files. These programs can set correct port numbers, between the FFT stages, or give the right twiddle factor to the butterflies. They also facilitate changing settings to many blocks, like setting bit widths or type of quantization.

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4 Simulation

results

The model can easily be simulated in Matlab, which is one of the strongest arguments of using Xilinx Blockset and the XSG. Two signals are used as inputs to the model from mat-files using the Simulink block “Signals from workspace”.

4.1 Signal

A

The first signal, here called signal A, gives a plot of the output frequency bin like in figure 4.1. This plot is from the Simulink model using floating-point integers. As seen in the figure there is an evident peak showing the frequency center, but the signal also brings some results to the other frequency channels which is noise that also has to be considered.

Amplitude (dB)

Samples

Channels

Figure 4.1: Frequency contents of signal A using Simulink model.

The Xilinx Blockset model uses fixed-point integers. This requires some necessary truncations and shifting operations to use the correct bits. Because of the truncations the result will not be perfectly like the results from the original Simulink model, see also figure 4.2. The system uses an overlap when buffering the signal. This means that the buffer is not completely loaded with values from the signal before it sends data to the FFT. In the beginning and in the end of the signal this will in the figure look like frequency content spread on more than one channel.

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Amplitude (dB)

Samples

Channels

Figure 4.2: Frequency contents of signal A simulated using Xilinx Blockset.

A simulation of the model written in VHDL can be seen in figure 4.3. This signal has fewer disturbances in the beginning and in the end of the signal.

Amplitude (dB)

Samples

Channels

Figure 4.3: Frequency content of signal A simulated in Matlab using written VHDL-model.

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Figure 4.4a: Peak of signal A from Xilinx Blockset model.

Figure 4.4b: Peak of signal A from VHDL code model.

A well working FFT should have a signal to noise ratio (SNR) of approximately 50 dB, this requirement is being fulfilled by both models as seen in figure 4.4 a-b.

4.2 Signal

B

Using another signal at the other input did result in a frequency content described in figure 4.4-4.6.

Amplitude (dB)

Samples

Channels

Figure 4.4: Frequency contents of signal B using Simulink model.

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however easily be discovered in all models. In this signal the frequency lies between the frequencies represented by channels 9 and 10 resulting in a peak with a flat top.

Amplitude (dB)

Samples

Channels

Figure 4.5: Frequency contents of signal B simulated using Xilinx Blockset model.

The first channel is set to zero because the truncations in the model cause a not wanted peak on this channel.

Amplitude (dB)

Samples

Channels

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4.3 Experiences of simulation

Simulating models is one way of verifying the system. The time to simulate models with components from Xilinx Blockset is longer than the time it takes to simulate in Simulink. There are a number of reasons for this. Xilinx blocks are “bit-true” models of the hardware implementation. This means that the models are represented as fixed-point data. In hardware, this corresponds to standard logic vectors and brings more complex models and therefore longer computation time. Another thing is that simulation using Simulink blocks is frame-based, which enables them to process hundred of pieces of data on one simulation step. Blocks in Xilinx Blockset can only process one piece of data in one simulation step. This is however something Xilinx is looking in to support in the next generations. The general explanation for longer simulation time, using Xilinx blockset, from Xilinx is that the system generator is in its infancy and will be further developed to improve its performance. [8]

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5 Generation of VHDL source code

When the model is made and simulated with desired result, the next thing is to

generate the VHDL source code. This is done using a special block in Xilinx blockset in this report called the SGGUI. In the graphical user interface (GUI) for this block different settings can be made, this is shown in figure 5.1.

Figure 5.1: System Generator block and its GUI.

As seen in the figure the user can choose which Xilinx component to use. There are also selections about where to save the generated code. Other options is whether generating a testbench or not, and if the Core Generator should be used.

5.1 Generated

code

The generation process is one large argument of using the System Generator, and it works perfectly on smaller models. Larger model however can be a problem. Code could not be generated from the full digital receiver model, so it had to be breaken into smaller parts. This finally resulted in the generation of code to a 16-point FFT, more about this can be read about in chapter 5.2. The code after generation can be found in a chosen folder. The model of a 16-point FFT generated 406 files, mostly VHDL files, and in this generation there were no testbench generated which would generate some additional files. Exept from VHDL files, there are some log files describing the generation process and how the System Generator has been working.

5.2 Experiences of the generation

Generation of VHDL code caused some problems. The first thing to mention is that this process also requires a lot from the computer just like the simulation step. There

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were also problems generating code for larger models, the full digital resceiver was not successfully generated. This forced the breakdown of the model into smaller parts and finally to just generate code to a 16-point FFT. Trying to synthesis this code was not successful however so an update from System Generator 1.1 into System

Generator 2.1 was made to deal with this. System Generator 2.1 was unfortunately not released before first of november 2001, which was a bit late for further evaluation. But synthesizeble code could finally be generated. This code was later used for an

evaluation of the System Generator.

As written before there are a lot of code generated from the System Generator. File names are based on how different blocks in the model are named, which makes it possible to find out what different files describes. The possibility of reading and understanding the generated code can be a requirement for designers. Every block in Xilinx Blockset is represented by a generic code used in the generation process. These blocks are mapped together according to the model built in Matlab. Blocks inherit their block names during generation so the designer can recognize parts of the code, but to change something in the code is not easy.

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6 Synthesis

This chapter collects the results from simulating and synthesis. This to verify the model and to be able to compare the different ways of designing an FPGA.

6.1 Synthesis

results

A resource usage report from the resulting log file after synthesis of the code

generated from the Xilinx Blockset model can be seen in appendix A. And from code generated from a generically written VHDL model can be see in appendix B. The target Xilinx FPGA was an XCV1000. As seen in this log files the Xilinx model uses 1152 register bits not including I/Os. The code generated from the generic VHDL model uses 1362 register not including I/Os. The mapping summary can also be compared, total number of look-up tables (LUTs) used in Xilinx Blockset model is 3840 compared to 4261 in the generic model. This can be said to be a measurement of how large the construction will be, placed in an FPGA.

6.2 Experience

of

synthesis

Synthesis using code generated from the Xilinx model with System Generator 2.1 is very easy to make, there are also a project made to use in the synthesis tool, so dealing with files is very easy.

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7 Conclusions

Working with the System Generator can have its benefits, especially when it comes to smaller models. Implementation requires a lot of line connecting between a lot of blocks, which may do the models quite hard to follow. The Matlab possibility of making sub blocks with desired settings is also a good function, just remember checking ports and ports numbers. In this model generating caused some problems, but I think the XSG can be useful many times, because of the easiness of synthesizing the generated code. Generation of test bench and test vectors is excellent for verifying. The problems of the System Generator can be explained by the fact that it is a new product not fully developed yet. It requires as said a lot from the computer and the generation step can be a problem for larger models. The number of blocks and

functions of the blocks are also limited today, but further developing from Xilinx can however make this to a good alternative to present design techniques.

Help for each block can be found just like other Simulink blocks in the Matlab help function. Help on generation problems can be found on Xilinx web site, but is not as accessible as one could desire.

An important thing to know is that versions of the XSG are bound to certain versions of Matlab and Xilinx software package. The version used in this project was mostly v1.1 but the generation phase required v2.1. To the version 1.1 of the XSG, Matlab 6.0 has to be used, and updating Matlab will cause problems.