Techniques for High-Speed Digital Delta-Sigma Modulators

Institutionen för systemteknik

Department of Electrical Engineering

Examensarbete

Techniques for High-Speed Digital Delta-Sigma

Modulators

Examensarbete utfört i Datorteknik vid Tekniska högskolan vid Linköpings universitet

av

Hsu Ching

LiTH-ISY-EX–16/4922–SE

Linköping 2016

Department of Electrical Engineering Linköpings tekniska högskola

Linköpings universitet Linköpings universitet

Techniques for High-Speed Digital Delta-Sigma

Modulators

Examensarbete utfört i Datorteknik

vid Tekniska högskolan vid Linköpings universitet

av

Hsu Ching

LiTH-ISY-EX–16/4922–SE

Handledare: Syed Asad Alam

isy_{, Linköpings universitet}

Examinator: Oscar Gustafsson

isy, Linköpings universitet

Avdelning, Institution Division, Department

Electronic and Engineering Department of Electrical Engineering SE-581 83 Linköping Datum Date 2016-01-25 Språk Language Svenska/Swedish Engelska/English   Rapporttyp Report category Licentiatavhandling Examensarbete C-uppsats D-uppsats Övrig rapport  

URL för elektronisk version

http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-125778

ISBN — ISRN

LiTH-ISY-EX–16/4922–SE Serietitel och serienummer Title of series, numbering

ISSN —

Titel Title

Techniques for High-Speed Digital Delta-Sigma Modulators Techniques for High-Speed Digital Delta-Sigma Modulators

Författare Author

Hsu Ching

Sammanfattning Abstract

In this theses techniques for high-speed digital delta-sigma modulator (DDSM) structures are considered. Four techniques are applied and evaluated: unfolding, increasing the num-ber of delay elements in the inner loop, pipelining/retiming, and optimizations provided by the synthesis tool. Of interest is to see the speed-area-power trade-offs.

For implementation, three different modulators meeting the same requirements are im-plemented. Each modulator has a 16-bit input and results in a 3-bit output. The baseline case is a second-order modulator, which has one delay element in its inner loop. Through optimization, two new structures are found: to provide two delay elements in the inner loop, a fourth-order modulator is required, while to provide three delay elements, a thirteenth-order modulator is obtained.

The results show that in general it is better to unfold the modulator than to obtain the speed-up through optimizing the arithmetic operators with the synthesis tool. Using cor-rect pipelining/retiming is also crucial. Finally, for very high-speed implementation, using the structures with more delay elements is required. Also, in many cases these are more area

and power efficient compared to using optimized arithmetic operators, despite their higher

computational complexity.

Nyckelord

Abstract

In this theses techniques for high-speed digital delta-sigma modulator (DDSM) structures are considered. Four techniques are applied and evaluated: unfolding, increasing the number of delay elements in the inner loop, pipelining/retiming, and optimizations provided by the synthesis tool. Of interest is to see the speed-area-power trade-offs.

For implementation, three different modulators meeting the same requirements are implemented. Each modulator has a 16-bit input and results in a 3-bit output. The baseline case is a second-order modulator, which has one delay element in its inner loop. Through optimization, two new structures are found: to provide two delay elements in the inner loop, a fourth-order modulator is required, while to provide three delay elements, a thirteenth-order modulator is obtained.

The results show that in general it is better to unfold the modulator than to obtain the speed-up through optimizing the arithmetic operators with the synthesis tool. Using correct pipelining/retiming is also crucial. Finally, for very high-speed im-plementation, using the structures with more delay elements is required. Also, in many cases these are more area and power efficient compared to using optimized arithmetic operators, despite their higher computational complexity.

Acknowledgments

At first, I would like to express my gratitude to my examiner, Professor Oscar Gustafsson for giving me this chance to have this chance for doing this work in Linkóping university. I appreciate his guidance, assistance and leading. Second, thank for my supervisor, PH.D. students Syed Asad Alam for helping me on not only technical part but also the right and positive attitude to do the thesis right.

Next, I want to say "thank you" to my friends who take same class, do the lab and study with me, Hiwa, Stefan, Markus, Mats and so many friends that this page is not enough to list all of you. I would also thank Hans, who share his room with me when I did not find a place to stay. Also, for all the friends, I meet in Sweden and Taiwan. Having all of you is nice.

Then, I can not describe how thankful it is to my classmate, friend and opponent, Ming-Jie, Yang. I would not come here if he did not tell me about the information to study here. Without his help, I would not be here and finish this work. I can only say that I have it in my mind.

Finally, thank my parents for supporting me to here. With your support, I get the power to face every day’s new challenge and conquer it.

Linköping, January 2016 Hsu Ching

Abbreviations

DDSM Digital Delta-sigma Modulator ADC Analog-to-Digital Converter DAC Digital-to-Analog Converter STF Signal Transfer Function

NTF Noise Transfer Function

1 Introduction 1

1.1 Delta-Sigma Modulator . . . 1

1.2 Digital Delta-Sigma Modulators . . . 3

1.2.1 Signal Feedback ∆Σ Modulators . . . 3

1.2.2 Error feedback ∆Σ Modulators . . . 4

1.2.2.1 Implementation Details of the Error Feedback Mod-ulators . . . 5 1.3 Motivation . . . 7 1.4 Contribution . . . 7 1.5 Thesis Organization . . . 7 2 DDSMs and Methods 9 2.1 Introduction . . . 9 2.2 Method . . . 10 2.2.1 Higher Order . . . 10 2.2.2 Unfolding . . . 11

2.2.3 Pipelining and Retiming . . . 13

2.2.4 Synthesis tool . . . 14

3 Implementation and Result 15 3.1 Second Order . . . 15

3.1.1 Pipelining and Retiming . . . 15

3.1.2 Unfolding . . . 17

3.1.3 Conclusion . . . 20

3.2 Fourth Order . . . 22

3.2.1 Pipelining and Retiming . . . 22

3.2.2 Unfolding . . . 24

3.2.3 Conclusion . . . 29

3.3 Thirteen Order . . . 30

3.3.1 Pipelining and Retiming . . . 30

3.3.2 Unfolding . . . 32

3.3.3 Conclusion . . . 37

Contents ix

4 Conclusion and Future Works 39

4.1 Conclusion . . . 39 4.2 Discussion . . . 45 4.3 Future Works . . . 46

1

Introduction

1.1

Delta-Sigma Modulator

Delta-Sigma(∆Σ) modulators are widely used in ADC (analog-to-digital converter) or DAC (digital-to-analog converter). Simplified structure of ∆Σ and its z-domain looks like Fig 1.1[1].

In

₊

_

Out

ADC

DAC

Integrator

(a) ∆ΣADC modulator

In

₊

_

+

Out

Q

1

z

Integrator

Quantizer

(b) ∆ΣADC modulator in z-domain

Figure 1.1:Block diagram of ∆Σ ADC modulator and its z-domain

The input signal goes through the quantizer by an integrator, and the quantized output returns to subtract from the input signal. This feedback path forces out-put to follow up the average inout-put. Any consecutive differences between inout-put signals will be tracked down in the integrator and ultimately revises itself. ∆Σ modulator can be easily understood with the linear model in z-domain as [2]

Out(z) = I n(z) ∗ ST F(z) + N oise(z) ∗ N T F(z), (1.1)

where In, Out, Noise denote the input signal introduced to ∆Σ modulator, the out-put signal and the quantization error added by the quantizer. In general cases, the STF (Signal Transfer Function) denotes a low-pass or all-pass function and the NTF (Noise Transfer Function) denotes a high-pass function. These will be discussed in next section of this chapter.

Next, in the real world, a simplified oversampling ∆Σ DAC system looks like Fig 1.2. Digital signal input will use the oversampling method which samples sig-nal in much beyond sigsig-nal bandwidth and transmits into digital ∆Σ modulator. Then, the result will be converted to analog and sent out.

Digital Signal Processing Oversampling & Filtering Digital ΔΣ Modulator Digital-to-Analog Conversion Analog Signal Processing Oversampling ΔΣDAC

Digital Domain Analog Domain

Figure 1.2:Simplified block diagram of oversampling digital ∆Σ DAC[3]

Oversampling

According to Nyquist sampling theorem, in order to ensure the correctness of data, the signal must be sampled in twice higher than its base frequency. The aliasing will occur if the Nyquist criteria are not satisfied which aliasing is an effect that makes signal to become unreliable when sampled. The way to avoid aliasing is called oversampling. It can increase the measurement resolution, and improve the quantization noise.

1.2 Digital Delta-Sigma Modulators 3

1.2

Digital Delta-Sigma Modulators

Digital Delta-Sigma modulators (DDSMs) are adapted from ∆Σ modulator, and it looks like Fig 1.3 with N bits digital input, an adder, a delay element, a bus-split, and a M bits digital output. The bus split will split the signal to output and feedback loop. Then, the result of feedback loop will sum up with the input. Then, as [4] with higher order multibit ∆ Σ data converters has been presented. The same thing can be done as DDSMS, such as [5] with multibit digital delta-sigma modulator or [6] with adaptable digital Delta-Sigma modulator on 2,3 and 4-order. N bits Digital In + M bits Digitial Out Bus split T N M-N M-N

x[n]

y[n]

y[n-1]

Figure 1.3:Block diagram of Digital ∆Σ Modulator

There are two topologies on digital ∆Σ modulator known as signal-feedback mod-ulator and error-feedback modmod-ulator.

1.2.1

Signal Feedback ∆Σ Modulators

As shown in fig 1.4[7], first-order ∆Σ modulator has a feedback and subtract to the input of the modulator. The feedback loop is for sending back the output and correcting the signal. The model for the signal feedback contains of an input signal X[n], eQ denotes as the quantization bits and Y [n] is the output of the

modulator. The mathematical equation of Fig 1.4 is shown as below.

X[n]

_Σ

_

Σ

Y[n]

e

Σ

+

T

X

[n]

X

[n]

X

[n-1]

X1[n] = X[n] − Y [n], (1.2)

X2[n] = X1[n] + X2[n − 1], (1.3)

Y [n] = X2[n − 1] + eQ. (1.4)

Transferring equation 1.2, 1.3, and 1.4 into z-domain, the equation will turn into

X1(z) = X(z) − Y (z), (1.5) X2(z) = X1(z) + X2(z)z −₁ , (1.6) Y (z) = X2(z)z −₁ + eQ. (1.7)

The output Y (z) is solved by equation 1.5, 1.6, and 1.7 in terms of X(z), and eQ.

The output Y (z) is obtained as

Y (z) = X(z)z−1+ (1 − z−1)eQ (1.8)

When eQ is zero which represents no quantization noise, the equation 1.8 will

become

Y (z) X(z) = z

−₁

= ST F, (1.9)

which behaves like all-pass filter. When the source failed or lost which means that X(z) is zero, the equation 1.8 will become

Y (z) eQ

= 1 − z−1= N T F, (1.10)

which behaves like high-pass filter.

1.2.2

Error feedback ∆Σ Modulators

X

₊

Y

+

H

Loop Filter

T

E

P

-g

Figure 1.5:Block diagram of error feedback ∆Σ

In Fig 1.5[3], the quantization error is sent back to the loop filter of transfer func-tion H(z) for noise shaping. The equafunc-tion can be obtained as

1.2 Digital Delta-Sigma Modulators 5

However, output must contain error which represent as (z). So, we get

gY (z) = T (z) − (z), (1.12)

Then, take it back to equation 1.11 and get

E(z) = −(z). (1.13)

Also, sum of fig 1.5 will be obtained as P (z) = H(z)E(z), and the X, is the input to the quantizer. The loop progress in this way and T can be transferred in z-domain as

T (z) = X(z) + E(z)H(z)

= X(z) − (z)H(z) (1.14)

Then, switching T (z) from 1.14 to 1.11, the equation will be

gY (z) = X(z) + (z)(1 − H(z)), (1.15)

where we can get

N T F = 1 − H(z), (1.16) while the STF(z) = 1.

1.2.2.1 Implementation Details of the Error Feedback Modulators

Y

+

T

E

-t

e

y

2

T

t

Y

y

E

e

Bus splitter

Figure 1.6: Block diagram of switching quantization and subtraction to a bus-split operation[3]

The loop filter has two main blocks which is r-delay (sequential circuitry) and

θ (combinatorial circuitry). The progress is evolved from figure 1.7(a) to figure

E

H

P

p

e

Figure 1.7:Block diagram of how loop filter evolved[3]

r - delays e P p θ _H t Y y MSB LSB X x + T

Figure 1.8: Schematic diagram of rth-order error feedback modulator in combination of figs 1.7, 1.8[3]

With the analysis of signal feedback modulator and error feedback modulator, the characteristic of DDSM is shown and helps us to create higher order DDSM with better resolution.

1.3 Motivation 7

1.3

Motivation

The motivation of this thesis is to construct a high-speed DDSMs with three tech-niques and analysis the benefit and weakness for each techtech-niques. With the speed increment, it companies with the payment on area cost, and power consumption cost also. The trading between costs and speed is also a fascinating topic to dis-cuss in this work.

1.4

Contribution

In order to achieve the high-speed demands, there are few steps to do. First, dif-ferent order of DDSM structures need to be simulated with MatLab on its spec-trum and NTF. The specspec-trum will show what the output looks like and NTF is for eliminating the noise [1]. Second, different order of DDSM structures will be redesigned with three new techniques. Third, it will be coded in Very High-Speed Integrated Circuit Hardware Description Language(VHDL) and simulated in MODELSIM to make sure the correctness of result. Lastly, all the redesigned structures will be synthesised in 65-nm standard cell library provided by the foundry.

To sum up, plenty of DDSMs are presented in this thesis with the record of esti-mation of area, power consumption and the speed. All the proposed designs are operable in faster speed than each order of DDSMs.

1.5

Thesis Organization

In chapter 2, different order of DDSMs will be described and more details about technique which we are going to use. Moreover, the detail of how to implement the techniques and what it may effect is shown in this chapter.

In chapter 3, the block diagram in different techniques and the synthesis result will be presented. Moreover, we will also analysis how the result goes and why.

In chapter 4, the conclusion will be made and discussion about future works. The advantages and disadvantages of redesigned DDSMs will be discussed here.

2

DDSMs and Methods

2.1

Introduction

Figure 2.1:Second Order DDSM

As mentioned in fig 1.9, with two delays in the feedback loop, the second order DDSM has been created and looks like fig 2.1 with two adders, two delay ele-ments, and a bus-splitter.

In this work, input is 16-bits digital value and the output is 3-bits digital value. These are the standard criterion for all DDSMs and its reliable with fair dates. Because no matter what input or output is selected, it should have close trend with similar results. But, all the DDSMs in VHDL code are written with dynamic N bits input and M bits output which can simulate in any situation.

2.2

Method

2.2.1

Higher Order

The order is decided by how many delay elements that put inside the DDSMs. The bigger N-order will lead a better resolution because of more integrator which has the stronger ability to shape the quantization noise. In the following chapter, N will be denoted as the number of order for DDSMs. Some research has be done such as [8] with higher order delta-sigma, [9] with 3-order delta-sigma ADC and [10] with 1,2,3,4-order delta-sigma comparison.

However, in this work, N=2, 4, 13 will be taken for candidates order to form DDSMs. The reason for using 2, 4, 13-Order DDSM is the growing amount of de-lay elements in its shortest path. As a coincident, 2, 4, 13-Order DDSM happens to be the candidates.

+

D

+

D

x(n)

y(n)

+

D

D

-(a)fourth order DDSM

+

x(n)

y(n)

D

D

D

D

+

D

D

+

D

+

D

D

D

+

D

D

D

Figure 2.2:Block diagram of fourth and thirdteenth order DDSM

The NTF is obtained as

N T F(z) = 1 − H(z),

which is derived before. Each NTF can be obtained by

Second Order : 1 − (−z−2+ 2z−1) Fourth Order : 1 − (−z−4+ 2z−2− z −₂ 2 ) T hirteenth Order : 1 − (z −₁₃ 4 − z−9 32 −z −₇₋ z −₆ 4 + 2z −₃ ) The comparison result with spectrum and NTF is shown in Figure 2.3.

2.2 Method 11 0 50 100 150 200 250 300 -200 -180 -160 -140 -120 -100 -80 -60 -40 -20 (a)N=2,M=1 0 50 100 150 200 250 300 -140 -120 -100 -80 -60 -40 -20 0 (b)N=4,M=1 0 50 100 150 200 250 300 -110 -100 -90 -80 -70 -60 -50 -40 -30 (c)N=13,M=1 0 50 100 150 200 250 300 -160 -140 -120 -100 -80 -60 -40 -20 0 13 Order 4 Order 2 Order (d)Total

Figure 2.3:NTF Spectrum in MATLAB

The speed should be same or less than previous order because the bigger N will get longer critical path also. With the N-order increasing, the amount of integra-tors increased so as area and power consumption.

2.2.2

Unfolding

Unfolding [11] is a technique to express an algorithm processing many samples per iteration. Mostly, unfolding applies to high-speed and low power ASIC ar-chitectures. In later chapters, M will be denoted as the unfolding factor. First, draw the data flow graph(DFG) of the structure. Second, duplicate each node N in the Original with M function blocks as Ni, i = 0, 1, 2, ... M-1. Third, calculate

the internal state by j = (i+L)%M and k = bi+L_M c_{where Ni denote the start point,}

Nj denote the destination, L is the amount of delay elements in the edge and k

is the new amount of delay elements between Ni to Nj. An example shows for

x(n)

+

y(n)

T

+

y(2n)

T

x(2n)

+

y(2n+1)

x(2n+1)

Unfold-2

Figure 2.4:Unfold-2 example

First, all the operations must be done before the next iteration started. So, there is an iteration period bound, T∞which can be desribed as

T∞= max_i P Op. in loop iTL,k Ni = 1 fmax , (2.1)

which Ni denotes the number of delay element in loop i, TL,kdenotes the sample

period for different computations. In Fig 2.4, the iteration bound are

T∞_{,bef ore}=

TL,add

1 , and T∞,af ter =

2 × TL,add

1 .

However, after unfolding, the strucutre are processing two samples per iteration, the sample frequency will be _T∞2

,af ter and the original is

1

T∞_{,bef ore}. If, TL,add is same

value, the sample frequency for before and after unfolding will be same. How-ever, in reality, two consequtive adders does not take twice large of execution time than one adder which makes the unfolding structure run faster than origi-nal.

2.2 Method 13

2.2.3

Pipelining and Retiming

Pipeline [11] is a technique to add registers along a path. By doing so, it will cut combinational logic into multiple cycles and causes the changing of clock rate, throughput, and latency. The critical path is also changed and lead increasing or reducing of speed. The goal is to introduce delay element into the critical path. Retiming is a technique on moving the position of delay element. However, both of technique have highly related to the amount of N delay elements. When N is small, it will be hard to cut the critical loop. Besides, pipelining, and retiming will be called as P in this work.

The speed will change due to the applying of pipelining, and retiming. Com-paring with the original case, the area and power consumption should be almost the same because the amount of structure is still the same. The process can be

x(n)

+

y(n)

T

+

y(n)

x(n)

PL

T

T

T

Figure 2.5:Pipelining example

described as follow.

y(n) = x(n) + y(n − 2)

After the pipelining, and retiming, the process is changed into follow.

x(n)

+

T

y(n)

+

y(n)

x(n)

Retime

T

T

T

Figure 2.6:Retiming example

The process can be described as follow.

y(n) = x(n − 2) + y(n − 2)

After the retiming, the process is changed into follow.

y(n) = x(n − 1) + y(n − 2)

The different is that for fig 2.5. Pipeline introduced a delay element in the sig-nal input and retimed with the delay element in the feedback loop. Due to the same destination for these two delay elements, they can be retimed into the same path and combined into one delay element. In conclusion, the signal function is changing but the time for input signal does not change and so as the feedback value. By doing this, the critical path length will be modified, and the result will stay the same.

2.2.4

Synthesis tool

The synthesis tool can resize the adder and rearrange the type of adder. When the ∆Σmodulator is running in its upper limit, the synthesis tool will try to resize and rearrange the type of adder to push up the sample rate. So, it influences the area cost and increases the sample rate.

3

Implementation and Result

3.1

Second Order

3.1.1

Pipelining and Retiming

N = 2, M = 1, P modulator is proposed which N, M, P represents for n order,

unfold-M, pipelining, and retiming. In Fig 3.1, one delay element has been pipelined, and retimed. It reduces the critical path from a subtractor and an adder to one adder only.

+ D + D x(n) y(n) 2 -v1 v2 (a)N=2,M=1,P

Figure 3.1:Block diagram of N=2, M=1 after pipelining and retiming

0 500 1000 1500 2000 0.5 0.7 0.9 1.1 1.3 1.5 1.7 1.9 2.1 A re a [( μ m) 2] GHz N=2,M=1 N=2,M=1,P

Figure 3.2:Area and frequency comparsion after pipelining and retiming

0 500 1000 1500 2000 2500 0.5 0.7 0.9 1.1 1.3 1.5 1.7 1.9 2.1 P o w e r [μ w] GHz N=2,M=1 N=2,M=1,P

Figure 3.3:Power and frequency comparsion after pipelining and retiming

After the pipelining and retiming, N = 2, M = 1, P can run up 2.1GHz which enhances 0.3GHz from non-pipelined. Moreover, it also implies with the effort of synthesis tool to resize and rearrange the type of adder. But, it is hard to see what synthesis tool does. In Fig 3.2, N = 2, M = 1, P takes more area cost when it runs in lower than 1.7GHz. In fig 3.3, the power cost are nearly same when it runs lower than 1.5GHz. With the pipelining and retiming, N = 2, M = 1, P can operate in faster sample rate with nearly no cost when it runs at 1.9GHz.

3.1 Second Order 17

3.1.2

Unfolding

In Fig 3.4(a), second order DDSM has been unfold two times and formed as N = 2, M = 2, P which N denotes order, M denotes unfolding factor, and P denotes for pipelining and retiming. However, there are only two delay elements in the structure and there is no other way to intorduce more delay elements. Because it will change the recursive loop. So, the critical path length is same as non-pipelined without any change. In Fig 3.4(b), second order DDSM has been unfold three times, and the critical path length increases one more adder. Fewer delay elements problem happened in Fig 3.4(c) also. But the sample rate which is the speed will be multiplied by M factor and the growth of critical length is not faster than M factor. The speed order should be N = 2, M = 4, P > N = 2, M = 3, P >

N = 2, M = 2, P . + + x(2n) y(2n) D + x(2n+1) D + y(2n+1) -2 2 -v1 v2 (a)N=2,M=2,P + x(3n+1) y(3n) + x(3n+2) + y(3n+1) + x(3n) + y(3n+2) 2 -2 2 -D D v1 v2 + (b)N=2,M=3,P + + x(4n+1) y(4n) + x(4n+3) + y(4n+1) + x(4n) + y(4n+2) D 2 -2 2 -D v1 v2 x(4n+2) + + y(4n+3) 2 -(c)N=2,M=4,P

+ + x(5n+1) y(5n) + x(5n+4) + y(5n+1) + x(5n) + y(5n+2) D 2 -2 2 -D v1 v2 x(5n+2) + + y(5n+3) 2 -x(5n+3) + + y(5n+4) 2 -(a)N=2,M=5,P + + x(6n+1) y(6n) + x(6n+5) + y(6n+1) + x(6n) + y(6n+2) D 2 -2 2 -D v1 v2 x(6n+2) + + y(6n+3) 2 -x(6n+3) + + y(6n+4) 2 -x(6n+4) + + y(6n+5) 2 -(b)N=2,M=6,P

Figure 3.5:Block diagram of unfold-5 and unfold-6

In Fig 3.5(a), the critical length is five adders. In Fig 3.5(b), the critical length is six adders. Due to the lack of delay elements, the critical path increases with the M factor. But, with the growth of M factor, it is hard to tell if N = 2, M = 5 is slower than N = 2, M = 6 or not.

3.1 Second Order 19 0 1000 2000 3000 4000 5000 6000 1 1.5 2 2.5 3 3.5 A re a [( μ m) 2] GHz N=2,M=1,P N=2,M=2,P N=2,M=3,P N=2,M=4,P N=2,M=5,P N=2,M=6,P

Figure 3.6:Area and frequency comparsion in different unfolding

0 1000 2000 3000 4000 1 1.5 2 2.5 3 3.5 P o w e r [μ w] GHz N=2,M=1,P N=2,M=2,P N=2,M=3,P N=2,M=4,P N=2,M=5,P N=2,M=6,P

Figure 3.7:Power and frequency comparsion in different unfolding

With the higher unfolding, pipelining, and retiming, the more speed it gains. However, there exists a maximum speed for 2-order DDSM as N = 2, M = 5, P which runs in 3.8GHz. So, the higher unfolding does not guarantee to have the highest sample rate. In Fig 3.6, the growth rate of area cost increases until Un-5. N = 2, M = 6, P has different situation when the speed is higher than 3GHz.

N = 2, M = 3, P runs in 2.1GHz with less area than N = 2, M = 1. However,

according to block diagram, N = 2, M = 3, P has 6 adders, 3 multipliers, 3 bus-splitters, and 2 delay elements which has more component than N = 2, M = 1 with 2 adders, 1 bus-splitter and 2 delay elements. The reason is that the adder of N = 2, M = 3, P has been resized and rearranged. Synthesis tool may use smaller adders and change the type of adder to carry save adder. Then, it causes the reduction of area. So, with unfolding, and synthesis tool, DDSM can run

faster with no more cost on area. In Fig 3.7, power consumption reduces with the increasing of unfold factor which shows the potential for power saving.

3.1.3

Conclusion

According to Fig 3.1, 3.4, and 3.5, the iteration period bounds are

T∞_{,N =2,M=1,P} = TL,add 1 , T∞,N =2,M=2,P = 2 × TL,add 1 , T∞,N =2,M=3,P = 3 × TL,add 1 , T∞_{,N =2,M=4,P} = 4 × TL,add 1 , T∞,N =2,M=5,P = 5 × TL,add 1 , T∞,N =2,M=6,P = 6 × TL,add 1 .

However, in Fig 3.8, the clock frequency does not drop with ratio as the increasing number of adders which shows that k number of delay element does not take k execution times. 2.1 1.3 1 _0.9 0.76 0.6 0.5 1 1.5 2 1 2 3 4 5 6 C lo ck F re q M Clock Freq

Figure 3.8:Comparision of M and highest clock frequency

In Fig 3.9, Fmax line stands for running at its highest speed and shows that Un-5 take the most area cost. Fmax/M line stands for how much does it take for each unfold block, and shows that Un-6 is the most efficient among others. 500MHz lines stands for executing in 500MHz, and shows that it has a stable increasing rate. 500MHz/M line stands for operating in 500MHz, then divided by M factor. It shows that each block is using the same area costs.

3.1 Second Order 21 0 1000 2000 3000 4000 5000 6000 7000 1 2 3 4 5 6 A re a [( μ m) 2] M 500MHz Fmax 500MHz/M Fmax/M

Figure 3.9:Comparision of M on area and area/M

0 1000 2000 3000 4000 5000 1 2 3 4 5 6 P o w e r [( μ w )] M 500MHz Fmax 500MHz/M Fmax/M

Figure 3.10:Comparision of M on power and power/M

In Fig 3.10, Fmax line shows that Un-5 use the most power consumption.

To sum up, with the use of unfold and pipeling, much faster DDSMs can be cre-ated. But, there is no speed increment with M=6.

3.2

Fourth Order

3.2.1

Pipelining and Retiming

In Fig 3.11, four delay elements have been pipelined, and retimed to different path. The critical path is only one adder which has same length as N = 2, M = 1, P .

+

+

D

x(n)

y(n)

+

D

-

D

D

-Figure 3.11:Block diagram of N=4,M=1 after pipelining, and retiming

0 500 1000 1500 2000 2500 0.5 1 1.5 A re a [( μ m) 2] GHz N=4,M=1 N=4,M=1,P

3.2 Fourth Order 23 0 500 1000 1500 2000 2500 3000 0.5 1 1.5 P o w e r [μ w] GHz N=4,M=1 N=4,M=1,P

Figure 3.13:Power and frequency comparison after pipelining, and retiming

N = 4, M = 1, P can run up 1.8GHz which enhances 0.3GHz than N = 4, M = 1.

Although the critical path is same in the diagram, it doesn’t mean that the synthe-sis result will be the same as N = 2, M = 1, P . In Fig 3.12, N = 4, M = 1, P uses more area cost when it executes in lower than 1.3GHz, and uses less area cost when it executes in higher than 1.3GHz except the highest speed. In Fig 3.13,

N = 4, M = 1, P consumes almost same power consumption as N = 4, M = 1

3.2.2

Unfolding

PA denotes for the same order, and same unfold which has different pipelining,

and retiming results. Figs 3.14(a) and 3.14(c) are distinctive cases from unfolding. Two blocks are working individually as DDSM without any connection.

+ + D x(2n+1) y(2n) + D 2 2-1 + D + x(2n) y(2n+1) + D 2 2-1 -v1 v2 v3 v4 -(a)N=4,M=2,P_A + + D x(3n) y(3n) + 2 2-1 + D + x(3n+2) y(3n+2) + 2 2-1 + D + x(3n+2) y(3n+1) + 2 2-1 D -v1 v3 v4 v2 -(b)N=4,M=3,P + D + x(4n+1) y(4n) + D 2 2-1 -+ + x(4n+3) y(4n+2) + 2 2-1 -v1 v2 + D + x(4n+2) y(4n+1) + D 2 2-1 -+ + x(4n) y(4n+3) + 2 2-1 -v3 v4 -(c)N=4,M=4,PA

Figure 3.14:Block diagram of unfold-2, unfold-3 and unfold-4

There are two ways to explain it. The intuitive way to explain is that if you take a look on N = 4, M = 1. In each feedback loop, there are two or four delay ele-ments in the path and when you doing unfold with even M. It certainly divided

3.2 Fourth Order 25

into even blocks. The other way to explain is by the formula j = (i + L)modM as written in chapter 2 in unfold section. If (i+L) and M is always an even number, the answer will be even number also which cause even blocks. In Fig 3.14(a), the critical path is two serial adders which are one adder longer than N = 4, M = 1, P . In Fig 3.14(b), the critical path is v4 → v1 with three adders. In Fig 3.14(c), the critical path is v4 → v3 with three adders.

+ + D x(2n+1) y(2n) + D 2 2-1 -v1 v2 + + D x(2n) y(2n+1) + D 2 2-1 -v3 v4 -(a)N=4,M=2,PB + D + x(4n+1) y(4n) + D 2 2-1 -+ + x(4n+3) y(4n+2) + 2 2-1 -v1 v2 + D + x(4n+2) y(4n+1) + D 2 2-1 -+ + x(4n) y(4n+3) + 2 2-1 -v3 v4 -(b)N=4,M=4,PB

Figure 3.15:Block diagram of unfold-2, and unfold-4 in different pipelining and retiming

In Fig 3.15(a), the critical path is v2 → v2 or v4 → v4 with two adders. The dif-ference with Fig 3.14(a) is that two delay elements are combined and the blocks become the same. In Fig 3.15(b), the critical path is v2 → v2 or v4 → v4 with four adders. The critical path increases one more adder but the blocks becomes the same. It will be much easier to optimized, and get better performance.

0 1000 2000 3000 4000 5000 1 1.5 2 2.5 3 A re a [( μ m) 2] GHz N=4,M=2,P N=4,M=2,P A B

Figure 3.16:Area and frequency comparison in different pipelining and re-timing 0 1000 2000 3000 4000 5000 6000 1 1.5 2 2.5 3 P o w e r [μ w] GHz N=4,M=2,P N=4,M=2,P A B

Figure 3.17: Power and frequency comparison in different pipelining and retiming

PAand PBdenote for a different way of the pipelining, and retiming. N = 4, M =

3.2 Fourth Order 27 0 2000 4000 6000 8000 1 1.5 2 2.5 3 3.5 4 A re a [( μ m) 2] GHz N=4,M=4,P N=4,M=4,P A B

Figure 3.18:Area and frequency comparison in different pipelining and re-timing 0 1000 2000 3000 4000 5000 1 1.5 2 2.5 3 3.5 4 P o w e r [μ w] GHz N=4,M=4,P N=4,M=4,P A B

Figure 3.19: Power and frequency comparison in different pipelining and retiming

0 2000 4000 6000 8000 1 1.5 2 2.5 3 3.5 4 A re a [( μ m) 2] GHz N=4,M=1,P N=4,M=2,P N=4,M=3,P N=4,M=4,PB B

Figure 3.20:Area and frequency comparison in different unfolding

0 1000 2000 3000 4000 5000 6000 1 1.5 2 2.5 3 3.5 4 P o w e r [μ w] GHz N=4,M=1,P N=4,M=2,P N=4,M=3,P N=4,M=4,P B B

Figure 3.21:Power and frequency comparison in different unfolding

N = 4, M = 1, P can run in 1.8GHz. N = 4, M = 2, PBcan run in 3.4GHz which is

2 × 1.7. N = 4, M = 3, P can run in 3.3GHz which is 3 × 1.1. N = 4, M = 4, PBcan

run in 4GHz which is 4 × 1. With higher Unfold, DDSM can run faster with less area and power consumption when it runs faster than 3.2GHz.

3.2 Fourth Order 29

3.2.3

Conclusion

In Fig 3.22, the clock frequency does not drop that much as Fig 3.8 because there are more delay elements available to cut the critical path.

1.8 _1.7 1.1 ₁ 0.5 1 1.5 2 1 2 3 4 C lo ck F re q M Clock Freq

Figure 3.22:Comparision of M and highest clock frequency

In Fig 3.23, Fmax/M line shows that unfold-4 is the most efficient with the lowest point. 0 2000 4000 6000 8000 1 2 3 4 A re a [( μ m) 2] M 500MHz Fmax 500MHz/M Fmax/M

0 1000 2000 3000 4000 5000 6000 1 2 3 4 P o w e r [( μ w )] M 500MHz Fmax 500MHz/M Fmax/M

Figure 3.24:Comparision of M on power and power/M

In Fig 3.24, Fmax/M line shows that unfold-4 is the most efficient with the low-est point. Fmax line shows that it takes almost same power cost as unfold-2, and unfold-3.

With unfolding, pipelining, and retiming, the new DDSMs have growth of speed.

N = 4, M = 4, PB can run in 3.2GHz with more area cost and same power

con-sumption. N = 2, M = 2, PB can run in 2GHz with same area, and less power

consumption.

3.3

Thirteen Order

3.3.1

Pipelining and Retiming

In Fig 3.25, the critical path is v13 → v1 with one adder.

+

x(n)

y(n)

D

D

D

D

+

D

D

+

D

+

D

D

D

+

D

D

D

3.3 Thirteen Order 31 0 1000 2000 3000 4000 5000 6000 0.5 0.7 0.9 1.1 1.3 1.5 1.7 1.9 A re a [( μ m) 2] GHz N=13,M=1 N=13,M=1,P

Figure 3.26:Area and frequency comparison after pipelining and retiming

0 1000 2000 3000 4000 5000 6000 0.5 0.7 0.9 1.1 1.3 1.5 1.7 1.9 P o w e r [μ w] GHz N=13,M=1 N=13,M=1,P

Figure 3.27:Power and frequency comparison after pipelining and retiming

N = 13, M = 1, P can run in 1.9GHz which enhance 0.6GHz. In fig 3.26, N =

13, M = 1, P takes more area cost when it executes in lower than 1.2GHz. In fig 3.27, the power consumption cost is nearly same when it executes in lower than 1.2GHz. As shown in Figs 3.26 and 3.27, N = 13, N = 1, P can run in 1.5 without any further cost on area, and power.

3.3.2

Unfolding

In Fig 3.28(a), the critical path is v12 → v2 or v5 → v9 vs v5 → v3 or v7 →

v8 with two adders. In Fig 3.28(b), the critical path is v12 → v2 or v5 → v6

with three adders. In Fig 3.28(c), the critical path is four adders. But they have potential to be pipelined, and retimed to have faster speed.

+ x(2n+1) y(2n) D D + D + D + D D D D D D 1/4 -1/32 -1 -1/4 + x(2n+1) D D + D + + -1/4 + + y(2n+1) 2 v1 v2 v3 v4 v5 v6 v7 v9 v10 v11 v12 v13 1/4 -1/32 -1 2 v8 (a)N=13,M=2,PA + x(3n+1) y(3n) + + + 1/4 + D D D v1 v2 + x(3n+2) D + + + D + y(3n+1) D D D + x(3n) + D + D + + D D y(3n+2) D -1/4 v3 v4 v5 v6 v7 v8 v9 v13 v10 v12 v11 1/4 -1/32 -1/32 -1/32 -1 -1 -1 -1/4 -1/4 -1/4 2 2 2 (b)N=13,M=3,PA + x(4n+3) y(4n) + + + 1/4 -1/32 -1 + 2 D + + 1/4 -1/32 D x(4n) D D D D + + -1/4 + y(4n+1) -1 2 -1/4 + + 1/4 -1/32 D x(4n+1) v11 + D + + y(4n+2) 2 -1/4 D + + x(4n+2) D D + -1 + + 2 y(4n+3) -1 -1/4 -1/32 1/4 v10 v7 v12 v8 v4 v5 v13 v1 v2 D v6 v9 (c)N=13,M=4

3.3 Thirteen Order 33 + x(2n+1) y(2n) D D + D + + D D D D D D D 1/4 -1/32 -1 -1/4 + x(2n) D + D D + + -1/4 + + y(2n+1) 2 v1 v2 v3 v4 v5 v6 v7 v9 v10 v11 v12 v13 1/4 -1/32 -1 2 v8 (a)N=13,M=2,P_B + x(3n+1) y(3n) + + + 1/4 + D D D v1 v2 + x(3n+2) + D + + D + y(3n+1) D D D + x(3n) + + D + + D D y(3n+2) D -1/4 v3 v4 v5 v6 v7 v8 v9 v13 v10 v12 v11 1/4 -1/32 -1/32 -1/32 -1 -1 -1 -1/4 -1/4 -1/4 2 2 2 D (b)N=13,M=3,PB

Figure 3.29:Block diagram of unfold-2, and unfold-3 in different pipelining and retiming

In Fig 3.29(a), the critical path is one adder. In Fig 3.29(b), the critical path is two adders.

0 2000 4000 6000 8000 10000 1 1.5 2 2.5 3 3.5 A re a [( μ m) 2] GHz N=13,M=2,P N=13,M=2,P A B

Figure 3.30:Area and frequency comparison in different pipelining and re-timing 0 2000 4000 6000 8000 10000 1 1.5 2 2.5 3 3.5 P o w e r [μ w] GHz N=13,M=2,P N=13,M=2,P A B

Figure 3.31: Power and frequency comparison in different pipelining and retiming

N = 13, M = 2, PB can run into 3.4GHz with nearly same cost as N = 13, M =

3.3 Thirteen Order 35 0 2000 4000 6000 8000 1 1.5 2 2.5 3 3.5 4 4.5 A re a [( μ m) 2] GHz N=13,M=3,P N=13,M=3,P A B

Figure 3.32:Area and frequency comparison in different pipelining and re-timing 0 2000 4000 6000 8000 1 1.5 2 2.5 3 3.5 4 4.5 P o w e r [μ w] GHz N=13,M=3,P N=13,M=3,P A B

Figure 3.33: Power and frequency comparison in different pipelining and retiming

N = 13, M = 3, PBcan run into 3.9GHz with nearly same cost on area and power

0 2000 4000 6000 8000 10000 1 1.5 2 2.5 3 3.5 4 4.5 A re a [( μ m )2 ] GHz N=13,M=1,P N=13,M=2,P N=13,M=3,P N=13,M=4,P B B

Figure 3.34:Area and frequency comparison in different unfolding

0 2000 4000 6000 8000 10000 1 1.5 2 2.5 3 3.5 4 4.5 P o w e r [μ w] GHz N=13,M=1,P N=13,M=2,P N=13,M=3,P N=13,M=4,P B B

Figure 3.35:Power and frequency comparison in different unfolding

N = 13, M = 1, P can run in 1.9GHz. N = 13, M = 2, PBcan run in 3.8GHz which

is 2 × 1.9. N = 13, M = 3, PBcan run in 4.5GHz which is 3 × 1.3. N = 13, M = 4, P

can run in 4.8GHz which is 4 × 1.2. With the unfolding, pipelining, and retiming, faster DDSMs are created. N = 13, M = 2, PB runs in 3GHz without any extra

3.3 Thirteen Order 37

3.3.3

Conclusion

In Fig 3.36, the clock frequency drops slower than Fig 3.22 because of more delay elements inside the path.

1.9 1.9 1.5 1.2 0.5 1 1.5 2 1 2 3 4 C lo ck F re q M Clock Freq

Figure 3.36:Comparision of M and highest clock frequency

In Fig 3.37, unfold-4 is the most efficient as shown in Fmax/M line with the most efficient block. In Fmax lines, it takes same area cost as unfold-2, and unfold-3.

0 2000 4000 6000 8000 10000 1 2 3 4 A re a [( μ m) 2] M 500MHz Fmax 500MHz/M Fmax/M

0 2000 4000 6000 8000 10000 1 2 3 4 P o w e r [( μ w )] M 500MHz Fmax 500MHz/M Fmax/M

Figure 3.38:Comparision of M on power and power/M

In Fig 3.38, unfold-4 is the most efficient as shown in Fmax/M line.

Very high speed DDSM has been proposed as N = 13, M = 4, P runs in 4.8GHz. However, it hasn’t been analysed with other orders. So, next chapter will have more discuss on how the performance goes with the different order of DDSMs.

4

Conclusion and Future Works

4.1

Conclusion

The result shows that unfolding decreases both area and power cost in certain high sample rate.; Higher order increases both area and power.; Pipelining, and retiming have nearly same area and power consumption. However, what is going to happen if all three techniques merged hasn’t been analysed yet. This chapter will discuss this.

As shown in Figs 3.8, 3.22 and 3.36, the maximum clock frequency range is be-coming concentrated and higher with the growth of n order. Besides, higher unfold is also the most efficient block in each order.

In Fig 4.1 shows all the redesigned DDSMs. Each order of DDSMs is concentrated together as where thirteenth order, fourth order, and second order DDSMs gather-ing at top, middle and bottom side. The speed order is roughly threetenth order > fourth order > second order.

0 2000 4000 6000 8000 10000 1 1.5 2 2.5 3 3.5 4 4.5 A re a [( μ m) 2] GHz N=2,M=1 N=2,M=1,P N=2,M=2,P N=2,M=3,P N=2,M=4,P N=2,M=5,P N=2,M=6,P N=4,M=1,P N=4,M=2,P N=4,M=3,P N=4,M=4,P N=13,M=1,P N=13,M=2,P N=13,M=3,P N=13,M=4,P B B B B

4.1 Conclusion 41 0 2000 4000 6000 8000 10000 1 1.5 2 2.5 3 3.5 4 4.5 P ow e r [μ w] GHz N=2,M=1 N=2,M=1,P N=2,M=2,P N=2,M=3,P N=2,M=4,P N=2,M=5,P N=2,M=6,P N=4,M=1,P N=4,M=2,P N=4,M=3,P N=4,M=4,P N=13,M=1,P N=13,M=2,P_B N=13,M=3,P N=13,M=4,P B B B

Figure 4.2:Power and frequency comparison for each best

In Fig 4.2, thirteenth order, fourth, and second order are in the different position of the diagram as top, bottom, and middle side.

In Figs 4.1, and 4.2, it is difficult to distinguish because too many DDSMs may have a close result as others. Next, the cearly bad results such as N = 13, M = 1, P will be eliminated.

0 1000 2000 3000 4000 5000 6000 7000 8000 9000 10000 1 1.5 2 2.5 3 3.5 4 4.5 A re a [( μ m) 2] GHz N=2,M=1 N=2,M=2,P N=2,M=3,P N=2,M=6,P N=4,M=4,P N=13,M=4,P B

4.1 Conclusion 43 0 1000 2000 3000 4000 5000 6000 7000 8000 1 1.5 2 2.5 3 3.5 4 4.5 P ow e r [μ w] GHz N=2,M=1 N=2,M=3,P N=2,M=5,P N=2,M=6,P N=4,M=4,P N=13,M=4,P B

Figure 4.4:Best power comparison in frequency domain

As the result, most of the good outcome are second order DDSMs because it does not need to take much cost as other with a little improvement. N = 2, M = 3, P runs in 2.1GHz with less power than N = 2, M = 1. With the help of unfold, pipelining, retiming and synthesis took, it already increases the sample rate to 3.6GHz. If 3.6GHz is still not high enough, the higher order can be used and push up the sample rate to 4.8GHz.

However, if both area and power factor are equally important. The result may be different. In the next section, area and power factor will be multiplied together as a new factor for further discussion.

5.4 5.9 6.4 6.9 7.4 7.9 1 1.5 2 2.5 3 3.5 4 4.5 A re a* P ow e r [d B ] GHz N=2,M=1 N=2,M=1,P N=2,M=2,P N=2,M=3,P N=2,M=4,P N=2,M=5,P N=2,M=6,P N=4,M=1,P N=4,M=2,P N=4,M=3,P N=4,M=4,P N=13,M=1,P N=13,M=2,P N=13,M=3,P N=13,M=4,P B B B B Figure 4.5:Area*Power[dB]

Thirteenth order, fourth, and second DDSMs are centered in top, middle and bottom position. However, there exist costly DDSMs such as N = 13, M = 1, P consumes more cost and does not run faster than others. So, these unfortunate result will be eliminated and only focus on good ones.

4.2 Discussion 45 5.4 5.9 6.4 6.9 7.4 7.9 1 1.5 2 2.5 3 3.5 4 4.5 A re a* P ow e r [d B ] GHz N=2,M=1 N=2,M=2,P N=2,M=3,P N=2,M=5,P N=2,M=6,P N=13,M=4,P Figure 4.6:Area*Power[dB]

As a result, N = 2, M = 5, P runs in 2.8GHz with same cost as N = 2, M = 1.

In conclusion, the redesigned DDSMs can be categorized into three types. First, slightly faster speed of DDSMs with less power consumption are proposed. Sec-ond, faster speed of DDSMs with the cost of area or power cost are created. Fi-nally, very fast speed of DDSMs with huge cost on area and power are build.

4.2

Discussion

Unfolding is the best technique than others to reduce the power consumption. Moreover, synthesis tool will resize and rearrange the adder. Then, it causes the reduction of area. Pipelining and retiming can have a small improvement on ∆Σ modulator but it is not that powerful as unfolding. If the speed increment is not

enough, the higher order will be applied with the consequence of more area and power consumption.

4.3

Future Works

Although, synthesis tool has already resized and rearranged the type of adder. There is still existing some potential to arrange the carry save adder(CSA). As there are serial adders showing in the structure, the CSA may be useful on im-proving the critical path. Carry Save adder can eliminate serial adders and re-duce the critical path. The significant point of CSA is that it doesn’t calculate the real value until the last step. So, it does not need to wait for the result while calculating. However, it requires some additional hardware register to store the value temporarily.

Bibliography

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[2] Sleiman Bou Sleiman and Mohammed Ismail. Multimode reconfigurable digital modulator architecture for fractional-PLLs. Circuits and Systems II: Express Briefs, IEEE Transactions on, 57(8):592–596, 2010.

[3] Nadeem Afzal. Complexity and power reduction in digital delta-sigma mod-ulators. 2014.

[4] Vaibhav Kumar and Degang Chen. An overview and behavioral modeling of higher order multi-bit sigmadelta A/D converters. In EIT, pages 128–133, 2008.

[5] Wen-Rong Yang, Yuan-Yuan Cheng, and Jiong-ming Wang. Simulation of multi-bit digital delta-sigma modulator. In Electronic Packaging Technol-ogy & High Density Packaging, 2008. ICEPT-HDP 2008. International Con-ference on, pages 1–3. IEEE, 2008.

[6] Yu Song, Eric C Moule, and Zeljko Ignjatovic. Adaptable digital delta-sigma modulator for multiband frequency synthesizer. In Circuits and Systems, 2008. MWSCAS 2008. 51st Midwest Symposium on, pages 842–845. IEEE, 2008.

[7] Ali Shah, Syed Asmat, and Sohaib Ayaz Qazi. Design of an all-digital, recon-figurable sigma-deltamodulator. 2012.

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