Evaluation of critical fault scenarios for operation with inherent overload in HVDC stations

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UPTEC E18024

Examensarbete 30 hp Juli 2018

Evaluation of critical fault

scenarios for operation with inherent overload in HVDC stations

Lisa Sander

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Teknisk- naturvetenskaplig fakultet UTH-enheten

Besöksadress:

Ångströmlaboratoriet Lägerhyddsvägen 1 Hus 4, Plan 0 Postadress:

Box 536 751 21 Uppsala Telefon:

018 – 471 30 03 Telefax:

018 – 471 30 00 Hemsida:

http://www.teknat.uu.se/student

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Sammanfattning

Elkraftsöverföring med hjälp av högspänd likström, High Voltage Direct Current (HVDC), har idag kommit att bli en nyckelkomponent när gäller uppgradering av vårt energisystem till ett förnybart, effektivt och hållbart system. HVDC-teknologin möjliggör anslutning av storskalig havsbaserad vindkraft till elnätet, men också hopkoppling av asynkrona elnät [1]. En möjlighet som det ibland talas om är att bygga ett s.k. super-grid, ett likströmsnät utöver de vanliga ac-näten som spänner över ett stort område och möjliggör storskalig anslutning av elkraft och transmission av elektricitet [2,3].

Likriktare (eng. rectifier) och växelriktare (eng. inverter) med ett gemensamt namn kallad omriktare (eng. converter), är själva hjärtat i HVDC-stationen. Det är här omvandlingen från växelström till likström, eller likström till växelström sker. En flexibel HVDC- omrikare som bla. ger möjligheten att styra aktiv effekt (P) och reaktiv effekt (Q) oberoende av varandra är den spänningsstyva omrikaren, (eng. Voltage Source Convertern, VSC ). VSC-teknologin baseras på transistorer som kan stängas av (släckas) och sättas på (tändas) när som helst, och fungerar som en kontrollerbar spänningskälla.

Den första spänningsstyva omrikaren var en tvånivåomriktare, där späningen på ac-terminalen endast kan anta två diskreta nivåer. Den senaste VSC teknologin är baserad

på seriekopplade celler bestående av kondensatorer och transistorer med motriktade dioder som kopplas i och ur och kan ge en mängd olika spänningsnivåer på ac-terminalen.

Den aktiva och reaktiva effekt som en HVDC station ska kunna hantera specificeras av kunden. Denna specifikation definierar en garanterad PQ-area, inom vilken HVDC stationen ska kunna operera under alla omständigheter. Dimensionering av utrustning i stationen baseras på den garanterade PQ-arean. Under vissa omständigheter, t.ex. under kort tid, eller vid låga utomhustemperaturer, är det möjligt att köra en station utanför den garanterande PQ-arean. Detta kallas att man kör stationen med ärvd överlast (eng.

inherent overload). För att hitta en PQ-area som gäller vid transienta förlopp, bl.a. vid olika typer av felfall, måste simuleringar utföras för att kontrollera att dimensioneringen av apparaterna i stationen inte överskrids. Detta examensarbete fokuserar på just detta, att finna en utökad PQ-area som gäller för de ström- och spännings-transienter som uppkommer vid de tre mest kritiska felfallen som kan inträffa i en HVDC station. Dessa tre fel är: trefasigt jordfel på omriktarbussen, enfasigt jordfel på omrikarbussen och pol till pol fel på dc-sidan.

För att hitta en utökad PQ-area härleds ekvationer för kortslutningsströmmen och nätspänningen på ac-sidan baserad på det trefasiga jordfelet på omriktarbussen. Sedan skapas ett program som beräknar kortslutningsström, nätspänning och den drivande spänningen vid felet för olika aktiva och reaktiva effekter, d.v.s. olika P och Q. Dessa parametrar beräknas för ett referensfall som utgörs av den punkt på den garanterade PQ- arean som skickar den största aktiva effekten till dc-sidan och absorberar den största

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reaktiva effekten från ac-nätet. Genom att begränsa den drivande spänningen vid felet för en mängd olika punkter i en PQ-area kan en utökad PQ-area definieras. Baserad på den utökade PQ-aren väljs olika PQ-punkter, både på randen, innanför och utanför den utökade PQ-arean. Simuleringar utförs i PSCAD/EMTDC för de tre kritiska felfallen och resultaten jämförs med resultaten för referenspunkten. Två givna PSCAD- modeller används, en för transienta strömmar och en för transienta spänningar.

Resultatet från studien av transienta strömmar vilken inkluderar det trefasiga jordfelet på omrikarbussen och pol till pol felet, visar att skillnaden mellan peak- och rms-strömmar för de olika PQ punkterna är så små att de kan bortses från vad gäller transient dimensionering av utrustning i HVDC stationen. Dock är resultaten intressanta för att lära sig mer om peak- och rms-strömmarnas beroende av varandra och dess beroende av P och Q. Bl.a. visar resultatet från simuleringarna av de transienta strömmarna att peakströmmarna får ett högre värde för lägre absorption av Q jämfört med en större absorption av Q. Resultatet från studien av transienta överspänningar, dvs det enfasiga jordfelet på omrikarbussen, visar att armspänningarna efter att cellkondensatorerna nått maximal uppladdning är lägre för referenspunkten än för alla andra punkter på randen samt en av punkterna innanför den utökade PQ-arean. Detta betyder att den utökade PQ- arean inte gäller för transienta spänningar.

Vad gäller transient dimensionering av utrustning så är det de högsta strömmarna som är av intresse. Därför har alla simuleringar och beräkningar utförts med ett starkt ac nät, dvs stor kortslutningseffekt och liten nätimpedans. Detta har påverkan på resultatet och för att se beroendet av P och Q tydligare så är ett förslag till framtida studier att utföra samma simuleringar fast för ett svagt nät.

Den viktigaste slutsatsen från detta arbete är att en utökad PQ area kan definieras som beskrivet i rapporten med avseende på transienta strömmar. Det står även klart att överspänningarna som uppkommer vid det enfasiga jordfelet på omrikarbussen behöver utredas vidare för att hitta en utökad PQ-area som gäller även för transienta spänningar.

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Acknowledgement

I would like to thank Arif Haider, and the manager at the Main Circuit Design (TSD) department at ABB HVDC in Ludvika, Joakim Lindell for giving me the opportunity to come to ABB HVDC.

I would also like to thank my supervisor Joakim Odnegård at the TSD department at ABB HVDC in Ludvika, for being supportive and guiding me throughout the whole thesis. Thanks for always taking your time, answering my questions and steering me in the right direction whenever needed.

For giving me support and assistance concerning the PSCAD modelling and

simulations, I would like to thank Hector-Armando Avila, Hassan Fidai and Shahid Mehmood, at the System Technology department at HVDC in Ludvika.

I would like to acknowledge Mikael Bergkvist at department of Electricity at Uppsala University as the University supervisor of my thesis work.

Finally, I would like to thank the entire TSD team for welcoming me, and being supportive during the whole thesis.

Ludvika, juni 2018 Lisa Sander

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1. Introduction

Customers demand for efficient and innovative solutions drive the development of High Voltage Direct Current (HVDC) technology. Ability to deliver inherent overload under well-defined conditions is a way to strengthen the overall efficiency and robustness of HVDC transmission. The modern Voltage Source Converter (VSC) HVDC technology is a key to access clean and sustainable electricity, due to the ability of linking offshore wind power plants to mainland grid ensuring a robust performance and minimal losses [1].

HVDC technology also provides a possibility of building a wide-area transmission network of multi terminal HVDC stations, on top of the existing grid, a so-called super grid, which enables transport of high volumes of energy across long distances [2,3].

Interconnection of asynchronous ac networks, long distance bulk power delivery and underground or submarine cable transmission, are the most common applications for HVDC transmission. Advantages such as built-in-redundancy, higher efficiency and lower harmonics, is taken to another level with the fairly new Modular Multilevel Converters (MMC). Together all of this advantages play a big role when it comes to investing and upgrading the energy system to a renewable, sustainable and efficient system.

The HVDC technology was first developed in 1930s by ASEA Sweden and Germany, when the mercury arc rectifiers were invented. The first order was placed in 1941, a 60MW, 115km underground cable to supply the city of Berlin with electricity. Due to World War II the system never came into operation. [4] Instead the world’s first commercial HVDC transmission system was built by ASEA in 1954 between the Island of Gotland and the Swedish mainland. Since the 1960s HVDC transmission systems is a mature technology based on thyristor valves. Development of new and higher rated semiconductors together with new application areas drove the development of the voltage source converters. In 1997 ABB launched their VSC-concept, HVDC Light, based on the new converter system developed at the ABB test range between Hällsjön-Grängesberg in the central of Sweden. The first VSC were a two-level converter consisting of a large number of IGBT modules connected in series to withstand the high voltage [5]. The top of the line technology for HVDC transmission system today is the Multi Modular Converter (MMC). The MMC consists of series connected half bridge modules comprised of two IGBTs with antiparallel diodes connected in parallel with a dc storage capacitor.

World’s first MMC for HVDC transmission is the Trans Bay Cable link, installed in the US, 2010 [6].

This thesis work has been performed at ABB Power Grid, HVDC, in Ludvika. It deals with analyzing transient currents and voltages arising at the decisive fault cases when the HVDC system is operating with inherent overload. The report is structured as follows.

Chapter 1 gives a brief introduction to the HVDC technology, different configurations and converter topologies. This chapter includes a description of the thesis, its objective and a definition of the scope of the work under section 1.6, “Limitations”. Chapter 2,

“Method”, explains how the work has been performed and describes the simulation

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process. In chapter 3 the theory relevant for the work is explained, including RL-transients and power calculations. Chapter 4 describes the main part of the work -how the short circuit current is derived and what assumptions has been made in order of define an extended PQ-area for transient currents and voltages, which is valid during inherent overload operation. Chapter 5 describes the characteristics of the three decisive fault cases considered in the report. Chapter 6 states and explains all the important simulation parameters. In chapter 7 all results from the simulations are presented. Finally, chapter 8 discuss the major findings, and chapter 9 concludes the work and present suggestions for future work.

1.1 Configurations

HVDC VSC can be designed for two configurations, symmetric and asymmetric converters. Two asymmetrical converters, one operating at positive dc voltage and one operating at negative dc voltage can be joined into a bipolar configuration [7].

An asymmetrical converter is operating with one dc-terminal connected to earth and the other terminal connected to the transmission cable or line, operating on either positive or negative dc voltage. The terminal connected to earth is called the neutral terminal and is designed for a low voltage. The neutral terminal of both stations can be connected to ground or the neutral terminals of the stations can be connected with a metallic return and then connected to ground. Figure 1 shows the asymmetrical monopole configurations and its return connections.

Figure 1. Different connections of the asymmetrical monopole configuration. a) ground return b) metallic return.

The symmetrical converter operates at a symmetric dc voltage i.e. one of the terminals is connected to a cable or overhead line operating at positive polarity, and the other terminal operating at negative polarity. Figure 2 shows the symmetrical monopole configuration.

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Figure 2. Symmetrical monopole configuration.

As stated earlier two asymmetrical converters can be joined into a bipole. A bipole configuration can be designed with earth connection at both stations as in Figure 3, or with a metallic return. The advantage of the bipolar converter is that either pole can be operated as a monopole [8]. This configuration is used when high power capacity is required or when more redundancy is needed.

Figure 3. Bipole configuration.

1.2 Converter technologies

There are two main technologies when considering HVDC transmission systems. Those are the Current Source Converters (CSC) operating by natural commutation, and the Voltage Source Converters (VSC) operating by forced commutation. CSCs were originally used for conversion from ac to dc to provide direct voltage for dc motors and industrial processes [9]. Naturally commutated converters uses thyristors which lacks turn off capability and is mainly used for HVDC power transmission at extremely high power levels. VSC based on power semiconductors which has the turn off capability allows for forced commutation and can be controlled independently from the grid. The possibility to control active and reactive power independently and supporting the grid by running HVDC-stations in standalone mode has made the VSC the most favorable converter for HVDC transmission [10].

A voltage source converter can be said to act like a controllable voltage source. It functions as a lot of small voltage sources which are switched on and off by power electronic switches. The most basic VSC is the two-level voltage source converter. Like all VSCs it is equipped with capacitors on the dc side to maintain the dc voltage constant.

The two-level converter is build up by series connected cells to handle the dc voltage required. Each cell consists of a controllable switch, typically an insulated-gate-bipolar transistor (IGBT) connected in antiparallel with a diode. The basic function is when the IGBT modules are fired it connects to the midpoint on the ac-side, VA to either +Vd/2 or -Vd/2, see Figure 4. By operating the IGBTs at a much higher frequency than the fundamental, a desired ac-side voltage can be achieved. The ac output voltage will not at all behave like a sine wave, but the output voltage is controlled. To achieve a more sinusoidal-like output voltage, a multilevel converter where the ac terminal can be

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clamped on to a higher number of voltage levels, can be constructed. With these multilevel converters the harmonics of the converter can be reduced drastically.

Figure 4. Two-level three phase converter.

1.2.1 Modular Multilevel Converter

The overall structure of the Modular Multilevel Converters (MMC) is the same as for the two level converter. The following section is based on [11]. The three phase MMC has three phase legs consisting of six phase arms. One leg is formed from two arms, each arm is connected to one of the dc rails with a midpoint connection to the ac terminal. Three of these legs are connected in parallel forming the three phase MMC as shown in Figure 5.

The converter has inductors in each phase arm which is needed to prevent potentially high current transients arising between the phase legs due to direct parallel connection of the

“voltage sources” implemented by the phase arms.

Figure 5. Three phase MMC with half bridge submodules.

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The phase arms are constructed from series connected converter elements called submodules forming the submodule strings. One submodule contains the fundamental building blocks; the dc capacitors, i.e. the cell capacitor, and the unidirectional semiconductor valves were the commutation circuits are internal to the submodules. The two basic submodules, the half-bride and full-bridge submodule, shown in Figure 6, are based on the two-level phase leg converter. The half bridge submodule consists of one two-level phase leg in parallel with a capacitor that is big enough to maintain the dc voltage level. Two possible switching states exists. Bypass is when the lower semiconductor, S2 is conducting and the ac terminal voltage is zero. Insertion is when the upper semiconductor in series with the capacitor, S1, conducts and the ac terminal voltage is equal to the capacitor voltage minus semiconductor losses. A third state called blocking, is achieved when both semiconductor valves are turned off allowing only the diodes to conduct. The diode that is conducting depends on the current direction. For a half-bridge module the two switching stated gives two discrete output voltages, +Vc and 0. The full- bridge module has two phase legs connected in parallel to the same capacitor which gives four different switching states and three output voltage levels, +Vc, 0 and –Vc.

Figure 6. Converter submodules and their corresponding output levels.

1.3 HVDC – general description

The main circuit equipment in the HVDC station is the AC-breaker, the converter transformer, the converter reactors and the valves. Figure 7 shows a basic one line diagram of a HVDC station including the some possible fault scenarios. The coming section will give a small overview of the main equipment included in a HVDC station.

Section 1.3.1, “Faults”, describes the possible fault cases considered for transient current and voltage studies. Section 1.3.2, “Active and reactive power flow”, explains the controllability of active and reactive power and section 1.3.3, “PQ-diagram”, gives a short background about PQ-diagrams.

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Figure 7. Basic line diagram of a HVDC station including possible fault scenarios.

A basic structure of a HVDC station and its main circuit equipment is shown in the one line diagram in Figure 7. P and Q defined as in the figure indicates delivery of active and reactive power to the ac network. The purpose of the AC-breaker is to energize the HVDC station and protect the station against faults. The converter transformer is designed with a tap changer with sufficient number of steps in order to deliver the amount of active and reactive power required. Considerations such as transformer winding connection, auxiliary power, tap changer design and short circuit impedance are taken into account when designing the transformer. On each phase arm, between the transformer and the cells, is the converter reactor. The converter reactor is very important and allows for control of active and reactive power by controlling the valve bus voltage as described in section 1.3.2, “Active and reactive power flow”. Converter reactors are also needed to avoid direct parallel connection of phase arms causing high transient currents. The submodules composing the valve are build up by cell capacitors and semiconductors as described in section 1.2.1, “Multi Modular Converter”. The cell capacitors are inserted or bypassed to form a sinusoidal voltage on the valve bus. Smoothing reactors are needed for filtering harmonics and to protect the station from high voltages at a dc-side fault.

1.3.1 Faults

There are several faults of importance which needs to be studied when designing a HVDC link. The characteristics of the faults introduces problems with transient overvoltage’s and transient overcurrent’s. Some faults locations might cause extensive problems. In particular it is the converter bus fault, which is referring to a fault between the converter reactor and the transformer, and the pole to pole fault referring to a fault after the smoothing reactor between the dc rails. Both of these fault locations is marked in Figure 7.

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The highest transient currents decisive for the transformer is caused by a three phase fault on the converter bus. A grounded three phase fault on the converter bus will connect all three phases on the converter bus to ground, forcing the converter bus phase voltage to zero. The impedance of the apparatus connected between the ac network and the fault and the impedance of the ac network will limit the current, but a high transient will occur. The peak value of the transient depends on at what time, or where on the voltage sinewave the fault occurs. The fault causing the highest currents through the valves is the pole to pole fault on the dc side. This fault creates a current path between the positive and negative dc rails and the voltage on the pole busses reaches zero forcing high currents through the valves.

Problem with transient overvoltages, which charges the cell capacitors and the dc-side capacitance, is introduced by the phase to ground fault on the converter bus. A phase to ground fault will cause the faulted phase voltage on the converter bus to go to zero and the voltage on the other phases to increase. This will cause the diodes in both the upper and lower arms of the unfaulty phases to conduct. The current flowing through the diodes charges the capacitors and increases the arm overvoltages which creates cell overvoltages.

1.3.2 Active and reactive power flow

The HVDC MMC behaves like a controllable voltage source which can output a sinusoidal voltage by following a voltage reference. The voltage reference depends on the active and reactive power set by the operator and other network conditions and constraints, such as voltage and current constraints from equipment. Since the ac system can be represented by a voltage source in series with a impedance, the interaction between the converter and ac system voltage sources, creates a power flow through the station.

This power flow is determined by the ac bus voltage and the valve ac bus voltage. The power flow is said to be controlled over the converter reactor and the active power 𝑃_{𝑐𝑜𝑛𝑣}, and reactive power 𝑄_{𝑐𝑜𝑛𝑣}can be calculated as:

𝑃

_{𝑐𝑜𝑛𝑣}

=

^𝑈^{𝑐𝑜𝑛𝑣}_𝑋^𝑈^𝑣^{𝑠𝑖𝑛𝛿}

𝑣⁄2

Equation (1)

𝑄

_{𝑐𝑜𝑛𝑣}

=

^𝑈^{𝑐𝑜𝑛𝑣}^(𝑈^{𝑐𝑜𝑛𝑣}_𝑋 ^−𝑈^𝑣^{𝑐𝑜𝑠 𝛿)}

𝑣⁄2

Equation (2)

Where 𝑈_{𝑐𝑜𝑛𝑣} is the converter bus voltage, 𝑈_𝑣 is the valve bus voltage, 𝑋_𝑣 is the reactance of the converter reactor and 𝛿 is the load angle, i.e. the angle between 𝑈_{𝑐𝑜𝑛𝑣} and 𝑈_𝑣. The load angle is in general a small angle.

The HVDC link based on the VSC technology is bidirectional meaning that a HVDC station can operate either as a rectifier or as an inverter. By studying the triangles in Figure 8, the following can be stated for the active power flow:

 If 𝑈_𝑣 lags 𝑈_{𝑐𝑜𝑛𝑣}  power flow from ac to dc side  converter is in rectifier operation

 If 𝑈_𝑣 leads 𝑈_{𝑐𝑜𝑛𝑣}  power flow from dc to ac side  converter is in inverter operation

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Figure 8. Power flow triangles.

For a small load angle 𝑠𝑖𝑛𝛿 can be approximated as 𝛿. Applying this approximation to Equation (1), it shows that the active power is governed by the load angle, which is controlled by changing the phase of the voltage at the valve bus. The voltage angle at the valve bus is controlled by the HVDC control system.

The reactive power flow of all HVDC stations is independent of the other HVDC stations in the link. By studying the triangles in Figure 9, the following can be stated for the reactive power flow assuming the active power is balanced:

 If |𝑈_𝑣| > |𝑈_{𝑐𝑜𝑛𝑣}|  reactive power is generated

 If |𝑈_𝑣| < |𝑈_{𝑐𝑜𝑛𝑣}| reactive power is consumed

Figure 9. Reactive power flow.

For the reactive power this small load angle implies that 𝑐𝑜𝑠𝛿 in Equation (2) can be approximated as 1, which shows that the reactive power flow is governed by the magnitude of the voltage difference between the converter bus voltage 𝑈_{𝑐𝑜𝑛𝑣} and the valve bus voltage 𝑈_𝑣. Both the voltage magnitude and the angle at the valve bus is controlled by the HVDC control system and can be changed rapidly.

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A PQ-diagram specifies the power capability of a HVDC link, i.e the active and reactive power that can be consumed or delivered by a HVDC station. Within this report the flow of active and reactive power is defined as positive towards the ac network. Applying this definition to a typical PQ-diagram specified by the customer, it can be constructed as shown in Figure 10, where the 1^st and 2^nd quadrant represents inverter operation and the 3rq and 4^th quadrant represents rectifier operation. A positive value of Q indicates delivery of reactive power and a negative value of Q indicated consumption or absorption of reactive power. A PQ-diagram is typically valid within the whole steady-state AC network range.

Figure 10. Example of a PQ-diagram and defining rectifier and inverter operation and generation or consumption of reactive power.

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1.4 Thesis problem description

In the tender stage, the guaranteed PQ operating area of the HVDC link is specified by the customer. Transient rating of high voltage equipment, derived from transient current and voltages studies, are performed based on this guaranteed PQ operating area. Under certain conditions a HVDC-station can be operating outside the specified PQ area, known as inherent overload operation. During certain conditions i.e. short-term and low ambient temperatures, operation with inherent overload is possible even without extending the current equipment rating. A part of the inherent overload investigation is to perform system studies for the decisive fault cases during inherent overload operation. The decisive fault cases for the symmetrical monopole configuration are:

 Three phase to ground fault on the converter bus

 One phase to ground fault on the converter bus

 Pole to pole fault

1.5 Objective

The purpose of this thesis work is to investigate what is happening during the decisive fault cases when the HVDC-station is operating with inherent overload. First an extended PQ-area needs to be defined based on the fact that the pre-fault voltage is constant.

Operation points defined in this area will be used to perform transient current and voltage studies in PSCAD. The aim of the thesis work is to set constraints for the extended operating PQ-area, which includes inherent overload operation, to guarantee that the system ratings are not exceeded.

1.6 Limitations

The scope of work is restricted to one of the two major converter technologies, the Voltage Source Converter (VSC). Current Source Converters (CSC) are not considered.

The converter topology considered is the multilevel VSC, the so-called Modular Multilevel Converter (MMC), consisting of cascaded half bride modules. Only the decisive fault cases of symmetrical monopole configuration of the modular multilevel VSC operating in rectifier mode will be covered by this thesis work.

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2. Method

The work is approached by theoretically determining the extended PQ-area and chose the operation points accordingly. Modifications were done to an existing simulation models given by ABB, and used to run the simulations. Analysis of the result were made by comparing the simulation results for the operation point’s chosen to the simulations results achieved for a reference case. The reference case or reference point, is defined as the PQ point where the HVDC station is operating at the highest P (rectifier) and highest Q (absorption), all the time staying within the guaranteed PQ-area. The working process is illustrated by Figure 11.

Hand calculations and derivation of formulas

MCT calculation

Matlab function definition

Defining extended PC-

area

Selection of

PQ-points Simulation Analysis of

results

Figure 11. Flow chart of the work process.

2.1 Selection of operating points

The definition of the operating PQ-area investigated is based on setting the driving voltage at the fault for the most decisive fault cases constant. A formula for the short circuit current is derived based on the equivalent impedance and the driving voltage at the fault. Another formula for the driving voltage at the fault is derived based on the active and reactive power at the point of common coupling. A Matlab function is defined to calculate the short circuit current, the driving voltage at the fault and other parameters of importance. To calculate the driving voltage at the fault, the worst tap changer position corresponding the selected steady state operating point, needs to be found. This is done by using a Matlab based tool called Main Circuit Toolbox (MCT). MCT is developed by ABB for steady state calculations of a HVDC systems. Calculating and comparing the driving voltage at the fault for the reference point with the PQ-pairs in the interior of a well-defined PQ-area, gives the extended PQ-area. From this extended PQ-area some arbitrary PQ-pairs were chosen and simulations were run in an existing ABB model of a HVDC link.

2.2 Simulation process

The program used for the simulations is called PSCAD/EMTDC, which is a graphical software simulation tool for power system transient simulations. Simulations were performed in PSCAD-models of a HVDC-system including the HVDC-cable, stations and a Thevenin representation of the AC networks. Two different PSCAD models were

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used, one for the transient current study and one for the transient overvoltage study. Slight modifications were applied to the models due to the operation point and tap changer position selected. The simulations process is described in Figure 12.

Adjust the model

Run snapshot

Multiple run - Three Phase to ground fault on

the converter bus

Multiple run - Pole to pole fault

Multiple run - Single Phase to ground fault on

the converter bus

Choose Fault time

Run final simulation

Choose Fault time Choose Fault time

Run final simulation Run final simulation Iterate

n-1 times

Compare results with the reference case Evaluate Irms and Ipeak at the

converter bus Evaluate Idc,peak at the fault Evaluate arm,- and converter bus voltages

Figure 12. Flowchart of simulation process. n= number of operation points.

First the PSCAD-model were adjusted and all PQ, points and ac network voltages were defined. After that a snapshot is performed when the HVDC system is running in steady state. The snapshot saves all the settings and values at the specific time when the snapshot is taken and can be used as starting values for other simulations. Based on the snapshot, a multiple run is performed for all three fault cases. The multiple run function runs the simulation 20 times and applies the fault at different times, starting at 20 ms and increasing the fault insertion time with a time step of 1 ms. Based on the result from the multiple run, the fault time which causes the highest voltages or currents (depending on the fault case) is chosen and the final simulation is performed in order to obtain all graphs and data. The procedure is performed for all operation points, i.e. n-1 times, where n is the number of operation points. Thereafter the rms- and peak-currents entering the converter bus is evaluated for the three phase fault on the converter bus, the dc peak current at the fault is evaluated for the pole to pole fault and the arm- and converter-bus voltages is evaluated at the single phase to ground fault on the converter bus. Finally, all results are compared with the results for the reference case.

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3. Theory

This chapter explains the theory relevant for this thesis work, including power system calculations and fault current theory.

3.1 R-L transients

This theory section is based on “Power System Analysis and Design” [12]. Considering the R-L circuit in Figure 13, the angle of the ratio between the reactance X and the resistance R, 𝜃 describes the realation between 𝑅 and 𝑋 = 𝜔𝐿 according to Equation (3)

𝜃 = 𝑡𝑎𝑛^{−1 𝑋}

𝑅 = 𝑡𝑎𝑛^{−1 𝜔𝐿}

𝑅 Equation (3)

Where L is the circuit inductance and 𝜔 is the angular frequency.

Figure 13. R-L circuit with ac voltage source.

The first order approximation of a short circuit current can be achieved by applying Kirchhoff’s Voltage Law (KVL) to the circuit in Figure 13, which yields:

𝐿𝑑𝑖(𝑡)

𝑑𝑡 + 𝑅𝑖(𝑡) = √2𝑉𝑠𝑖𝑛(𝜔𝑡 + 𝛼) t ≥ 0 Equation (4)

Where V is the peak voltage of the voltage source and α is the phase angle of the voltage source. The solution to the differential equation consists of two components, one dc- component and one ac-component

𝑖(𝑡) = 𝑖_𝑎𝑐(𝑡) + 𝑖_𝑑𝑐(𝑡) =^𝑉^𝑚𝑎𝑥

𝑍 (𝑠𝑖𝑛(𝜔𝑡 + 𝛼 − 𝜃) − 𝑠𝑖𝑛(𝛼 − 𝜃)𝑒⁻^𝑇^𝑡 Equation (5)

Where 𝑉_𝑚𝑎𝑥 is the peak voltage, Z is the magnitude of the impedance Equation (6), 𝜃 is the angle of the X/R-ratio Equation (3) and T is the time constant Equation (7)

𝑍 = √𝑅²+ 𝑋² Equation (6)

𝑇 =

^𝐿

𝑅 Equation (7)

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The total fault current called the asymmetrical fault current, Equation (5), consists of the symmetrical fault current, also called ac fault current, Equation (8), which is a sinusoidal steady state fault current and the dc-offset current, also called dc fault current, Equation (9), which is an exponential decaying sinusoidal current.

𝑖_𝑎𝑐(𝑡) =^𝑉^𝑚𝑎𝑥

𝑍 𝑠𝑖𝑛(𝜔𝑡 + 𝛼 − 𝜃) Equation (8)

𝑖_𝑑𝑐(𝑡) = −^𝑉^𝑚𝑎𝑥

𝑍 𝑠𝑖𝑛(𝛼 − 𝜃)𝑒^−𝑡/𝑇 Equation (9)

The magnitude of the dc offset depends on the phase angle of the voltage, α, i.e where on the voltage wave the short circuit occurs. When α= 𝜃 the dc offset is 0 and when 𝛼 = 𝜃 ± 𝜋/2, the maximum dc offset is reached which means that the highest peak value of 𝑖 occurs. Note that the highest peak current occur close to the zero crossing of the voltage, and that varying values of R and X will change the parameter 𝜃 dramatically, which implies a big impact on the behavior of the fault current. Figure 14 shows the voltage waveform, the ac, - and dc fault current and the total fault current described above.

Figure 14. Theoretical short circuit current.

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3.2 Complex power in a three phase system

The following theory section is based on “Power System Analysis and Design” [13].

Active power P, and reactive power Q, are usually calculated from the complex power, 𝑆 defined by:

𝑆 = 𝑈𝐼^∗ = 𝑈∠𝛿 ∙ 𝐼∠𝛽^∗ = 𝑈𝐼∠𝛿 − 𝛽 Equation (10)

Where (𝛿 − 𝛽) is the angle between the voltage and current. The three phase complex power can be recognized as Equation (11) and the conjugate of the line current, 𝐼^∗ as Equation (12).

𝑆_3𝜙 = 𝑃_3𝜙+ 𝑗𝑄_3𝜙 Equation (11)

𝐼^∗ = 𝐼_𝑃+ 𝑗𝐼_𝑄 Equation (12)

𝐼_𝑝 is the real part of the current consumed by an active load. 𝐼_𝑄 is the imaginary part of the current consumed by an inductive or capacitive load.. The three phase apparent power is constructed from the one phase apparent power according to Equation (13).

𝑆_3𝜙 = 3𝑆_1𝜙 Equation (13)

Applying Equation (10) to the single phase power by using the definition of the current in Equation (12) and inserting these equations into Equation (13) yields

𝑆_3𝜙 = 3𝑈_𝐿𝑁𝐼_𝐿^∗ = 3^𝑈^𝐿𝐿

√3 (𝐼_𝑃− 𝑗𝐼_𝑄) = √3𝑈_𝐿𝐿(𝐼_𝑃 − 𝑗𝐼_𝑄) Equation (14)

Where 𝑈_𝐿𝑁 is the line to neutral voltage and 𝑈_𝐿𝐿 is the line to line voltage. Identifying the coefficients for the active and reactive power in Equation (11) by comparing them with the coefficients of Equation (14) yields

𝑃_3𝜙 =√3𝑈_𝐿𝐿𝐼_𝑃 Equation (15)

𝑄_3𝜙 =√3𝑈_𝐿𝐿𝐼_𝑄 Equation (16)

Thus Equation (15) represents the three phase active power calculated from the system line to line voltage and the real part of the current. Equation (16) represents the three phase reactive power again calculated from the systems’ line to line voltage and the imaginary part of the current.

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3.3 Voltage calculations for an infinite source

Consider Figure 15 below.

Figure 15. Illustration of active and reactive power exchange with an infinite source.

Calculation of the voltage delivered by an infinite source, provided the voltage at the point of common coupling, is done by applying Kirchhoff’s voltage law:

𝑈_𝑖𝑛𝑓^𝐿𝐿

√3 ∠𝛼_𝑖𝑛𝑓 =^𝑉^𝑏𝑢𝑠

𝐿𝐿

√3 ∠𝛼_𝑏𝑢𝑠+ 𝑉_{𝑑𝑟𝑜𝑝}∠𝛼_{𝑑𝑟𝑜𝑝} Equation (17)

Where 𝑈_𝑖𝑛𝑓^𝐿𝐿 is the magnitude of the voltage and 𝛼_𝑖𝑛𝑓 is the angel of the line to line voltage of the infinite source. 𝑉_bus is the magnitude of the voltage and 𝛼_bus is the angle of the line to line voltage at the point of common coupling. 𝑉_{𝑑𝑟𝑜𝑝} is the magnitude of the voltage drop and 𝛼_drop is the voltage angle over the impedance.

The voltage drop over the impedance can be represented by the one phase complex impedance 𝑍 = 𝑅_𝑛𝑒𝑡+ 𝑗𝑋_𝑛𝑒𝑡 times the current passing through the impedance, Equation (12). Inserting the impedance and current into Equation (10) and solving for 𝑈_𝑖𝑛𝑓^𝐿𝐿 ∠α_inf the expression yields:

𝑈_𝑖𝑛𝑓^𝐿𝐿∠𝛼_𝑖𝑛𝑓 = 𝑈_𝑏𝑢𝑠^𝐿𝐿 ∠𝛼_𝑏𝑢𝑠+ 𝐼𝑍 = 𝑈_𝑏𝑢𝑠^𝐿𝐿 ∠𝛼_𝑏𝑢𝑠+ (𝐼_𝑝+ 𝑗𝐼_𝑞)(𝑅_𝑛𝑒𝑡+ 𝑗𝑋_𝑛𝑒𝑡) Equation (18)

3.4 Charging of capacitor

The voltage over the terminals of a capacitor is the time integral from 𝑡₀ to 𝑡 over the current (𝑖_𝑐) which is charging the capacitor, Equation (19).

𝑉_𝑐 = ¹

𝐶∫ 𝑖_𝑡^𝑡 _𝑐(𝑡)𝑑𝑡

0 Equation (19)

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4. Process of deriving extended PQ-area

The converter bus grounded three phase fault is used as the limiting case for deriving the PQ-area for operation with inherent overload with respect to transient currents. The fault current entering the converter bus at a three phase grounded fault on the converter bus, is a composition of a network contribution and a contribution from the valves. Only the network contribution is considered since the valve contribution is much less, and the valves are blocked shortly after fault initiation. This fault is dimensioning for the transformer since it will cause the highest currents through the transformer windings.

Figure 4 shows a line diagram of a part of a HVDC- station, representing the network voltage Unet and network impedance Znet, as a Thevenin ekvivalent. The one line diagram includes the converter transformer connected to the point of common coupling (PCC) and the converter bus, and the converter reactor connected between the converter bus and the valve bus. Applying Kirchhoff’s voltage law to the one line diagram in Figure 16 yields

𝑈_𝑛𝑒𝑡 = 𝑈_𝑃𝐶𝐶+ 𝑖𝑍_𝑛𝑒𝑡 Equation (20)

Figure 16. Line diagram for a grounded three phase fault on the converter bus.

A grounded three phase fault is initiated on the converter bus. From the circuit in Figure 16, a general formula for the short circuit current can be derived. The following sections, section 4.1.1, “Network Impedance”, 4.1.2, “Transformer Impedance” and 4.1.3, “Tap changer”, comprise a general description of all parameters included in the derivation of the short circuit current.

4.1.1 Network Impedance

The network impedance will affect the short circuit current. The one phase equivalent network impedance, Z_sc in Equation (21) can be calculated from the short circuit capacity of the ac network, 𝐼_𝑠𝑐 and the voltage at the point of common coupling, 𝑈_𝑝𝑐𝑐. The short circuit capacity and the voltage at the point of common coupling is specified by the customer.

𝑍

_𝑠𝑐

= 𝑍

_𝑛𝑒𝑡

=

^𝑈^{𝑝𝑐𝑐,𝐿𝐿}

√3∙𝐼𝑠𝑐

Equation (21)

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Based on the network impedance the following definition for the network strength yields:

 Strong network ↔ high short circuit current ↔ low short circuit impedance/network impedance.

 Weak network ↔ low short circuit current ↔ high short circuit impedance/network impedance

4.1.2 Transformer Impedance

Since the transformer is connected between the driving voltage of the fault and the fault location, the transformer impedance will limit the fault current. The equivalent transformer reactance in Ohm, 𝑋_𝑡𝑟 is calculated according to Equation (22), by using the p.u reactance of the transformer 𝑋_{𝑡𝑟,𝑝𝑢}, the rated three phase power of the transformer S_3ϕ, and the rated line to line voltage on the secondary- or valve-side of the transformer U_2n,LL [6].

𝑋

_𝑡𝑟

=

^𝑈^{2𝑛,𝐿𝐿}²

𝑆_3𝜙

∙ 𝑋

_{𝑡𝑟,𝑝𝑢} Equation (22)

For the calculation of the transformer reactance, Equation (22), the tap changer is located on the line side. This means that the number of turns in the primary winding can be changed, thus changing the inductance of the primary winding and the voltage on the primary side. Considering the tap changer is located on the primary- or line-side of the transformer, the line side voltage will vary due to the switching of the tap changer. The reactance as seen from the secondary side will be constant since the secondary side has no tap changer, meaning that all parameters in Equation (22) are constant. The transformer reactance seen from the side without the tap changer is always constant, in this case the valve side reactance [14].

4.1.3 Tap changer

The function of the tap changer is to connect or disconnect turns in one of the transformer windings to change the turns-ratio in order to adjust for voltage changes on the primary side or changing the output voltage on the secondary side. For an ideal transformer the transformer ratio, a, is defined as:

𝑈₁ 𝑈₂

=

^𝑁¹

𝑁₂

= 𝑎

 𝑈2=𝑈₁

𝑎 Equation (23)

According to Figure 16, 𝑈₁ is the voltage at the PCC and 𝑈₂ is the voltage at the converter bus. 𝑁₁ is the number of turns in the primary winding and 𝑁₂ is the number of turns in the secondary winding. Changing the turns ratio will change the voltage on the converter bus for any given network voltage. If the tap changer is located on the line side i.e the primary side of the transformer, the following voltage change is initiated by positive and negative tap changer steps respectively see Equation (23).

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 positive steps  increasing the number of turns  decreased converter bus voltage

 negative steps  decreasing the number of turns  increased converter bus voltage

4.2 Derived formula for short circuit current

Consider the line diagram in Figure 16. Moving the network voltage Unet and network impedance Znet, to the secondary side of the transformer using the transformer ratio, gives the following expression for the equivalent network impedance Z_net′, Equation (24) and the equivalent network voltage U_net′, Equation (25).

𝑍

_𝑛𝑒𝑡

′ = (

^𝑈²

𝑈₁

)

²

𝑍

_𝑛𝑒𝑡

Equation (24)

𝑈

_𝑛𝑒𝑡

′ =

^𝑈²

𝑈₁

𝑈

_𝑛𝑒𝑡

Equation (25)

Applying Equation (24) and Equation (25) to the line diagram in Figure 16, the equivalent line diagram will look as shown in Figure 17.

Figure 17. Simplified line diagram for short circuit current calculation.

From Figure 17 the short circuit current 𝐼_𝑠𝑐, is:

𝐼

_𝑠𝑐

=

^𝑈^𝑛𝑒𝑡

𝑈2 𝑈1

√3(𝑍𝑡𝑟+𝑍_𝑛𝑒𝑡′) Equation (26)

Introducing the tap changer on the line side, 𝑈₁can be rewritten as:

𝑈₁ = 𝑈_1𝑛(1 + 𝑡𝑐𝑝∆) Equation (27)

where 𝑈_1𝑛 is the nominal rated voltage on the primary side of the transformer, 𝑡𝑐𝑝 is the tap position and ∆ is the tap changer step size in p.u. [15]. Inserting Equation (24) and Equation (27) into Equation (26) yields the final expression for the short circuit current:

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𝐼

_𝑠𝑐

=

^𝑈^𝑛𝑒𝑡

𝑈2 𝑈1𝑛(1+𝑡𝑐𝑝∆)

√3(𝑍𝑛𝑒𝑡( ^𝑈2

𝑈1𝑛(1+𝑡𝑐𝑝∆))²+𝑍_𝑡𝑟) Equation (28)

where 𝑈_1𝑛 is the nominal voltage on the primary side of the transformer, 𝑈₂ is the nominal voltage on the secondary side of the transformer, 𝑡𝑐𝑝 is the tap changer position, ∆ is the tap changer step size, 𝑍_𝑡𝑟 is the transformer impedance in Ohm, 𝑍_𝑛𝑒𝑡 is the equivalent impedance for the ac network which is the same impedance as the short circuit impedance 𝑍_𝑠𝑐 calculated from the short circuit current given by the customer, Equation (21).

4.3 Critical parameters

From the short circuit current in Equation (28), two critical parameters can be defined.

These are the driving voltage at the fault Uci0 and the network impedance Z_net. Both of these parameters are coupled to the network voltage 𝑈_𝑛𝑒𝑡. By limiting one of these parameters and keeping the other constant, the change of the short circuit current can be predicted.

4.3.1 Uci0

Uci0 is defined as the voltage at the converter bus when the converter is blocked, Equation (29), i.e when no load is connected. In simple words it is the transformer ratio multiplied by the network voltage, and for the three phase fault at the converter bus Uci0 is the voltage driving the fault current.

𝑈

_𝑐𝑖0

= 𝑈

_𝑛𝑒𝑡 ^𝑈^2𝑛

𝑈_1𝑛(1+𝑡𝑐𝑝∆)

Equation (29)

4.3.2 Znet

Z_net is the network impedance as described in section 4.1.1. The characteristics of the ac network at the time of the fault impacts the short circuit current. Indirectly the voltage over the network impedance, which depends on the current through the impedance, determined form the power delivery or consumption, (Figure 16, Equation (20)) has an impact on the short circuit current. From this reasoning it is clear that Z_net has an impact on the network voltage 𝑈_𝑛𝑒𝑡.

4.4 Network voltage

As described above both of the critical parameters are affected by the network voltage.

The network voltage is determined from the voltage at the point of common coupling plus the network impedance multiplied by the current, as described in Equation (20). The current depends on the power consumed or delivered by the HVDC station. An expression for the network voltage as a function of active and reactive power, 𝑈_𝑃𝐶𝐶 and 𝑍_𝑛𝑒𝑡 can be derived. By writing the current and impedance in Equation (20) on complex form and

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replacing the active and reactive current by Equation (15) and Equation (16), an expression for the network voltage can be derived, Equation (30).

|𝑈_𝑛𝑒𝑡| = √(𝑈_𝑝𝑐𝑐− 𝑅𝑛𝑒𝑡∙ ^𝑃^𝑝𝑐𝑐

√3∙𝑈_𝑝𝑐𝑐− 𝑋𝑛𝑒𝑡∙ ^𝑄^𝑝𝑐𝑐

√3∙𝑈_𝑝𝑐𝑐)

2

+ (𝑅𝑛𝑒𝑡∙ ^𝑄^𝑝𝑐𝑐

√3∙𝑈_𝑝𝑐𝑐− 𝑋𝑛𝑒𝑡∙ ^𝑃^𝑝𝑐𝑐

√3∙𝑈_𝑝𝑐𝑐)

2

Equation (30)

4.5 Determination of inherent overload capability

The inherent overload capability for rectifier operation is based on the fact that 𝑈_𝑛𝑒𝑡 is equal or less compared to 𝑈_𝑛𝑒𝑡 for a reference case. The reference case is when one station is operating at maximum active power delivery and maximum reactive power absorption, i.e the left corner of the PQ-diagram. In order to define a PQ-diagram for the inherent overload capability, the following assumptions are made:

 The tap changer position if fixed during the fault

 The network impedance 𝑍_𝑛𝑒𝑡 is small.

 𝑈_𝑛𝑒𝑡 is equal compared to 𝑈_𝑛𝑒𝑡 for a reference case

By calculating 𝑈_𝑛𝑒𝑡 for the reference case and comparing 𝑈_𝑛𝑒𝑡 for a whole set of operation points outside the guarantied operating area, gives an allowed area within were the maximum current limit is not passed. For a converter operating in rectifier mode absorbing 700MW and 230MVAr from the grid, the extended PQ area is shown in Figure 18.

Figure 18. PQ-diagram for converter operating as a rectifier absorbing reactive power with guaranteed operating point at P=700 MW and Q=-230 MVAr.

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4.6 Selection of operation points

From the PQ-diagram defined in section 4.5, specific operating points are chosen for investigating the fault rating behavior. The operating points are chosen according to Table 1. The first operating point is the reference point. The points 2-5, are laying on the boundary, where 𝑈_𝑛𝑒𝑡 is constant, and the rest are chosen arbitrary at maximum and minimum active power delivery. Simulations for all three fault cases are performed for operation point 1 to 9.

Table 1. Operation point selected from the PQ-area in Figure 18.

Op. point Operation points

Number P [MW] Q [MVAr]

1 -700 -230

2 -525 -252

3 -350 -274

4 -175 -293

5 0 -311

6 0 -280

7 -700 -311

8 -700 -350

9 -700 -200

Figure 19 shows the extended PQ-area with the operation points marked with red circles. Note that absorption of P, indicated as –P, means that the converter is operating as a rectifier. Referring to the guaranteed operating PQ-area in Figure 10, the area in Figure 19 extends the area in the third quadrant.

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Figure 19. PQ-diagram showing the extended PQ-area with the operation points from Table 1 marked with red circles.

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5. Fault characteristics

The following sections in chapter 5 briefly discuss the converter characteristics of the fault. The three decisive fault cases included in the thesis work will be described. Voltages and currents in the HVDC-station relevant for the fault, both before and after the fault has occurred, are analyzed. Section 5.1 describes the three phase grounded fault on the converter bus and section 5.3 describes the pole to pole fault on the dc side. Since these two faults faces problems with transient currents, they are included in the so-called transient current study. Section 5.2 describes the single phase to ground fault on the converter bus, which faces problems with transient voltages, thus included in the transient

voltage study. Figure 20 shows a very simplified line diagram of a three phase multi modular VSC showing the fault locations and the currents and voltages calculated.

Figure 20. Three phase VSC with the fault locations indicated.

5.1 Three phase grounded converter bus fault

Before the fault occurs the converter is assumed to operate in steady state, meaning that all station equipment, cell and pole capacitors are energized. When the fault occurs the converter bus voltage drops to zero, Figure 21 a). The converter valves will quickly be blocked by the control system and the only remaining path for a fault current from the dc side is through the diodes. However, since the positive dc rail voltage is higher, and the negative dc rail voltage is lower compared to the converter bus voltage, which is zero, the diodes will be reverse biased. The only fault current contribution of significance is the current from the ac side which will keep a high stress on the transformer until the ac breaker is opened. The converter bus current from the ac side is shown in Figure 21 a).

The current increases drastically when the fault occurs and the peak current depends on the magnitude of the voltage on each phase at the time of the fault, explained in the theory, section 3.1. The dc-component of the converter bus current decreases exponentially.

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Figure 21. Converter three phase to ground fault. a) Converter bus voltages. b) Converter bus current.

5.2 Converter bus single phase to ground fault

Before the single phase fault on the converter occurs, the converter is operating in steady state. The converter bus voltage is a symmetrical three phase voltage as described in previous section. Shortly after the fault occurs it is detected by the protection and the valves are blocked. The voltage on the phase that is short circuited drops to zero and the voltages on the unfaulty phases grows. Since the voltage of the unfaulty phases on the converter bus increases above the dc positive pole voltage, the upper diode in each cell of the positive healthy arms will be forward biased resulting in a current flow that is charging the dc-side capacitance, increasing the positive dc voltage level. The voltage of the healthy phases on the converter bus is also decreasing below the negative pole voltage, resulting in a current flow through the lower diodes on the healthy negative arms, charging the negative pole capacitor and the dc-side capacitance, decreasing the negative dc voltage further. The cell capacitor will be charged as well. The cell capacitors on the positive healthy arms is charged when the dc voltage on the positive dc terminal minus the phase voltage on the converter bus is higher than the sum of the cell voltages across the arm. The cell capacitors on the negative healthy arms are charged when the dc voltage on the negative dc terminal plus the phase voltage on the converter bus is lower than the sum of the cell voltages across the arm.

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Figure 22. Converter single phase to ground fault. a) Converter bus voltage (blue, red, yellow), positive pole voltage (purple) and negative pole voltage (green). b) Arm currents. c) Arm voltages.

It is clear that the charging of capacitors quickly increases the dc pole voltages and cause a high voltage drop across the unfaulty converter arms, resulting in high voltages stress for the cell capacitors. Comparing the phase voltage on the converter bus with the pole voltages and pole voltage minus the voltage over the arms, Figure 22 a), shows which diodes that are forward biased. Figure 22 b) shows how the current is flowing in the converter arms. Capacitors and the dc cable are charged corresponding to the current flow through the arms, the voltage drop over the converter arms is shown in Figure 22 c).

Analysis of the graphs in Figure 22 shows that a positive current flow through the arms are charging the cell capacitors and a negative current flow is charging the dc side capacitance.

5.3 Pole to pole fault

Again the converter is assumed to operate in steady state at the time the pole to pole fault occurs. The converter bus voltage is a symmetrical three phase voltage as described in section 5.1, and the symmetrical dc pole voltage reaches the nominal voltage of ±320kV.

When a short circuit between the positive and negative pol occurs, the pole voltages drops to zero directly, see Figure 23 a). A current path from the positive to the negative pole is introduced, conducting currents from the ac side and causing high fault currents through both the upper and lower converter arms. This fault current is shown in Figure 23 b), the peak current is reached within 20ms and decays slowly.

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Figure 23. Pole to pole fault. a) Positive pol voltage (blue) and negative pol voltage (red). b) Dc fault current.

Evaluation of critical fault scenarios for operation with inherent overload in HVDC stations

Examensarbete 30 hp Juli 2018