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ESKI - MODULE DOCUMENTATIONCAMERA INTERFACE

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ESKI - MODULE DOCUMENTATION CAMERA INTERFACE

RESET

DIM_MEM<7:0>

FSYNCO

CAMERA INTERFACE

PIXS_MEM PIXS_CAM SAVE_IM

DIM_CAM<7:0>

CLK_O ONCE

EV_SECOND

EN_FC EN_BUFF

CONFIGURE

STORED

CLK_I SNAP_VIDEO

GAIN<3:0>

EN_AUT_OFF TH1<7:0>

CONFIGURED

AUTO_UPD OFFSET_I<5:0>

TH2<7:0>

SLOPE1<13:0>

SLOPE2<13:0>

Module responsible _______________________

Specification responsible Mattias O'Nils

Designers ____________________________________________

General description: The Camera interface module performs configuration and image capture from a National VGA image sensor. The captured image can be saved to a frame memory or fed to an output. The output can be two pixels from the same spatial position; one from the frame memory and one from the image sensor

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CONTENTS

Page

1. SPECIFICATION...3

1.1 INTERFACEDESCRIPTIONDIGITALSIGNALS...3

1.2 HIERARCHY...4

1.3 FUNCTIONALITY...4

1.4 DESIGNGOALS...4

DESCRIPTION OF IMPLEMENTATION...5

2. VERIFICATION...5

3. DELIVERABLES...5

3.1 DIGITALMODULES...5

Rev Date Description of modification Sign

0 Initial issue

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1. Specification

1.1 Interface description digital signals Inputs and outputs in alphabetic order.

Input signals

Signal name From Input delay Description

SAVE_FR Processor - Indicates that a frame should be buff.

ONCE Processor 20 ns Save one frame only

EV_SECOND Processor 20 ns Save every second image.

EN_BUFF Processor 20 ns Enable output of buffered frame EN_FC Processor 20 ns Enable capturing of image from IS CONFIGURE ImageSensor 20 ns Init image sensor

RESET External 20 ns Reset

CLK_I External 20 ns Reference clock signal

SNAP_VIDEO Processor 20 ns Enable snapshot or video mode

GAIN<3:0> AGC 20 ns Pixel gain

TH1 AGC 20 ns Part of PWL-gamma function

TH2 AGC 20 ns Part of PWL-gamma function

SLOPE1 AGC 20 ns Part of PWL-gamma function

SLOPE2 AGC 20 ns Part of PWL-gamma function

AUTO_UPD AGC 20 ns Update gain and gamma

automatically OFFSET_I<5:0> Processor 20 ns Static offset value

EN_AUTO_OFF Processor 20 ns Enable automatic update of offset Output signals

Signal name To Output delay Description

DIM_MEM<7:0

>

ImProc 20 ns Buffered pixel value from frame- memory

DIM_CAM<7:0> ImProc 20 ns Unbuffered pixel value from camera

CLK_O ImProc 20 ns Clock synched with pixel rate

PIXS_MEM ImProc 20 ns Buffered pixel value valid PIXS_CAM ImProc 20 ns Unbuffered pixel value valid

FSYNC ImProc 20 ns Frame synchronization

CONFIGURED Processor 20 ns Indicates that init. was successful STORED Processor 20 ns Indicates that a frame was stored

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1.2 Hierarchy

Hierarchy of module Camera interface:

IS – Image sensor (Standard component, National LM9618) CC – Camera configurator

IC – Image capture

BC – Frame memory controller

FM – Frame memory (Standard component, Vdd= 3.3V and should store one frame) 1.3 Functionality

The CAMERA INTERFACE has three main functions: 1. Image capturing, 2. Configuration of image sensor (camera), and 3 Controlling a buffer memory.

SAVE_FR ONCE E_SECOND Type of compression

0 - - Frame buffering dissabled

1 0 0 Undefined

1 0 1 Every second frame is stored in the frame memory,

other frames are sent direct to the port.

1 1 0 Store one frame only.

1 1 1 Undefined

Detailed descriptions are given in the module documentation for the CC, IC and FMC modules and in the datasheets for the IS and FM components.

1.4 Design goals Frequency: 15 MHz

CAMERA INTERFACE

IS CC IC FMC FM

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2. Description of implementation

The implementation strategy should be described here. If special techniques have been used to fulfill the Design goal demands, this should be pointed out.

3. Verification

Describe the strategy used for verifying that the module works according to specification.

 How is the module simulated?

 Is a prototype needed to verify the function?

 Which functions and parameters are covered and which are not covered by the simulations? (referred to specification)

 How is the other functions and parameters verified?

 What are the results compared to (Matlab model, C-program, Behavioral model, manually from specification, other)

4. Deliverables

4.1 Digital modules

The following documents should be included in the module documentation:

 RTL-code(s)

 Schematics

 Test bench(es)

 Prototype

The following documents may be included in the module documentation (optional):

 Result from simulation

 Synthesis script

 Synthesis constraints (if other than project common constraints)

 Synthesis report(s)

Page 5 of 5

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