Adding DRAM and SRAM support for the NoC Generator

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Adding DRAM and SRAM support for the NoC

Generator

Kandidatexamensarbete

VIKTOR ÖBERG

Supervisor: Johnny Öberg and Francesco Robino

Examiner: William Sandqvist

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Abstract

A NoC generator tool that generate an arbitrarily large Multi-core

platform, targeted for single-chip FPGA platforms was developed in

2011 by Johnny Öberg and Francesco Robino in the department of

elec-tronic system, KTH, Sweden. In the current implementation of the

platform, only on-chip memory is supported. However, the size of the

data the system needs to handle is often too large to fit in those

memo-ries. Thus, external memory access to both SRAM and SDRAM on the

FPGA board is needed. Adding external memories to an FPGA system

takes a lot of time and hard studies in the Altera platform handbooks.

Adding this feature to the NoC generator would save a lot of time for

the platform developers

In this thesis, an example design using external memories is analysed

to obtain the necessary information needed to update the NoC generator

to support SRAM and SDRAM.

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Introduction

Multiprocessor system-on-a-chip is becoming more common to use in embedded

systems. The size of the data the systems need to process is also increasing. To

be able to grant this expansion the multiprocessor need to access both SRAM and

SDRAM on the FPGA board.

Both type of memories provide a larger size of

memory than the on-chip memory. The SRAM is just a few megabyte but is much

more faster then the SDRAM but on the other hand the SDRAM can store much

more data. So you have to consider which of this memories is best fitted for your

application. Johnny Öberg and Francesco Robino in the department of electronic

system, KTH, Sweden has development a NoC generator tool that allows you to

generate an arbitrarily large Multi-core platform from an XML configuration file,

targeted for single-chip FPGA platforms. In the XML file, the system designer

selects the target technology, the type of NoC topology, which kind of routers and

interconnection schemes that should be generated. For each processor node, a simple

configuration can be done[1].

In this thesis, a study how to add external SDRAM and SRAM for the existing

NoC generator is presented. It will describe the changes that have to be done for

the existing .sopc-file and what you need to add to make it work. The SDRAM

only communicate with the cpu 0 and the SRAM only communicate with cpu 1, to

access the memories you have to communicate with respective cpu.

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Chapter 2

Design

2.1 Structure of SOPC file

The NoC generator generates the system .sopc-file for target Altera platform[1], the

.sopc-file contains the hardware contents of the SOPC builder system. It’s divided

in three sections that describes the hardware configuration of the platform.

1. Element- Contain basic information of all the components such as name and

id.

2. Module- Describes what kind of component it is and the value of the

param-eters for the component.

3. Connection- Describes which components that are connected to each other.

In figure 2.1 is a example of how a clock is described in the .sopc-file.

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CHAPTER 2. DESIGN

2.2 The _hw.tcl structure

To define SOPC Builder components you can make a Hardware Component

De-scription File (_hw.tcl) that contains declarations of their properties and behavior.

Each _hw.tcl-file represents one component instance which you can add to an SOPC

Builder system.

A typical _hw.tcl file contains the following information[2] :

1. Basic component information-includes the components name, version, and

description, a link to its documentation, and pointers to HDL implementation

files for synthesis and simulation.

2. Parameter Declarations-Parameters are values that the user of your

compo-nent can set that affect how the compocompo-nent is implemented, such as the size

of a memory. Properties of each parameter include the parameter’s name,

whether or not it is visible, and, if visible, the text to display when

describ-ing it. When the SOPC Builder system is generated, the parameters can be

applied to the component as Verilog HDL parameters or VHDL generics.

3. Interface Properties-The interfaces of a component define how to connect it

to the rest of the system and determine how other components in the system

interact with it. When you add interfaces to a component, you declare which

signals make up each interface. You also define interface properties, such as

wait states for an Avalon

®

Memory-Mapped (Avalon-MM) interface.

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Chapter 3

External SRAM and SDRAM

Both SRAM and SDRAM are volatile memories. Volatile memories can only hold

their contents while power is applied to the memories. When the power is removed,

the memories loses their contents. Volatile memories are unusable for application

that have to retain data when the memory is switched off.

3.1 External SRAM

SRAM is a static RAM device that is connected externally to a FPGA. There are

many varieties of external SRAM devices. The application is what determine what

type of external SRAM to choose. It is both advantages and disadvantages to design

with SRAM memories.

3.1.1 Advantages

SRAM can store a larger amount of data than on-chip memories and is quite fast,

but not as fast as on-chip memories. The typical SRAMs have capacities ranging

from around 128 Kbytes to 10 Mbytes[3]. SRAMs are very low latency and high

throughput devices. They are slower than on-chip memories because they connect

to the FPGA over a shared bidirectional bus. The SRAM interface is very simple

and connecting a SRAM to an FPGA is a simple design task. SRAM buses can be

shared with other external SRAM devices, or even with external memories of other

types, such as flash or SDRAM.

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CHAPTER 3. EXTERNAL SRAM AND SDRAM

3.1.2 Disadvantages

The main disadvantages of external SRAM in FPGA-based embedded system are

cost and the space it needs on the board. SRAM are more expensive per Mbyte

than other high-capacity memory types such as SDRAM[3]. They also consume

more board space per Mbyte than both SDRAM and FPGA on-chip memory[3].

The FPGA on-chip memory does not consume any space.

3.1.3 Best Applications

An external SRAM is effective to use as a fast buffer for medium-size blocks of

data[3]. An application is to use SRAM to buffer data that does not fit in

on-chip memory and requires lower latency than a SDRAM can provide. SRAM is

a excellent choice for accessing random data.

External SRAM can be used as

execution memory for a processor without cache. The low latency properties of

external SRAM improves the processor performance if the processor does not have

a cache to mask the higher latency of other memories[3].

3.1.4 Poor Applications

For systems which require large amounts of storage and systems which are

cost-effective, external SRAMs are not a good implementation choice. If the system

requires a block of memory that is larger than 10 Mbytes , you may chose a different

type of memory[3]. SDRAM can fit the block and is less expensive.

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3.2. SDRAM

3.2 SDRAM

SDRAM is also a volatile memory. The different between SDRAM and SRAM

is that it is dynamic and must be refreshed periodically to maintain its content.

SDRAM uses dynamic memory cells that are much smaller than the static cell

the SRAM uses. The interface of SDRAM is very complex and require a special

controller hardware. The memory space in SDRAM is divided into banks,rows and

columns. SDRAM multiplexes the row and column over then same address lines,

this reduces the number of pins that a given size of SDRAM need[3].

The SDRAM controller manages all the access to the memory, this allows the

rest of the system to access the memory without any demand to know its internal

architecture. Many embedded system use SDRAM because of its high-capacity and

low-cost.

3.2.1 Advantages

The biggest advantage for SDRAM is their high capacity and low cost. No other of

RAM is near this combination. That makes it a very popular choice. SRAM also

uses less pins on FPGA because row and column addresses are multiplexed over the

same address pins [3]. The power consumption is often lower for SDRAM compared

to same capacity SRAM devices.

3.2.2 Disadvantage

The interface for SDRAM is complex and requires an SDRAM controller to manage

SDRAM refresh cycles,address multiplexing and interface timing [3]. The controller

consumes FPGA logic elements that could be used for other logic on the FGPA.

SDRAM has long access time, this force the controller to make preparations to

minimize the latencies. The latency for SDRAM is always higher than for SRAM

and the FPGA on-chip memory. After the initial access latency is overcome, the

throughput of the SDRAM is quit high[6].

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CHAPTER 3. EXTERNAL SRAM AND SDRAM

3.2.3 Best Applications

The large capacity SDRAM can provide makes it very suitable for buffering large

data blocks. This is common used in network packets, video and audio buffers. It

could also be used to store large programs for microprocessor software, this improves

the performance for the software.

3.2.4 Poor Applications

If you need to access a block of data with low latency and the first-access latency is

to high for the application, you should consider low latency memories. The FGPA

logic elements are limited and if your application does not need the capacity from a

SDRAM it could be a smarter choice to use SRAM or the FPGA on-chip memory

that does not consume as many FPGA logic element as the SDRAM controller does.

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Chapter 4

Adding external SRAM and SDRAM

4.1 External SRAM

First you need to add a Avolon-MM Tristate Bridge on the FPGA, it is required

to let you access the external SRAM memory chip. By adding the Avolon-MM

Tristate Bridge in the SOPC builder you can extract the code that describes the

tristate bridge in a generated .sopc-fille. The code that describes the components

that were added to the system is documented in the Appendix.

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CHAPTER 4. ADDING EXTERNAL SRAM AND SDRAM

Figure 4.1. Example Design Block Diagram

To add the SRAM component you have to use the SOPC builder component

editor and define the interface. In the SOPC builder component editor you can

choose to use templates for a typical Avolon-MM Tristate Slave. You have to look

at the datasheet for your external SRAM memory chip, the datasheet provides you

with information about the chip such as signal it need to communicate and timing

to be able to talk with the tristate bridge. All the parameters can be changed and

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4.2. ADDING SDRAM

added in the SOPC builder component editor. When you are done the component

is saved as a _hw.tcl-file that represents a component which can be added to the

SOPC builder system. The _hw.tcl-file for the SRAM memory chip on the altera

DE2-115 board is documented in the appendix. The generated code in the .sopc-file

that describes the relationship with the FPGA-chip and SRAM is also documented

in the appendix.

4.2 Adding SDRAM

The Altera DE2-115 board contains 2 SDRAM chips that can each store 64 Mbytes

of data. Each chip is organized as 8M x 16 bits x 4 banks [4]. The SDRAM chips

require careful timing control. To provide access to the SDRAM chips, the SOPC

Builder implements an SDRAM Controller circuit. This circuit generates the signals

needed to deal with the SDRAM chips.

The signals needed to communicate with a chip are shown in Figure 4.2. All of

the signals, except the clock, can be provided by the SDRAM Controller generated

by the SOPC builder. The clock signal is provided separately. It has to meet the

clock-skew requirements.

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CHAPTER 4. ADDING EXTERNAL SRAM AND SDRAM

Figure 4.3. SDRAM contoller and SDRAM chip

The clock skew depends on physical characteristics of the DE2-115 board. For

proper operation of the SDRAM chip, it is necessary that its clock signal, SDRAM

Clock, leads the Nios II system clock, by 3 nanoseconds.[5] This can be accomplished

by using a phase-locked loop (PLL) circuit which can be manually created using

the MegaWizard plug-in from Altera and make a new ALTPLL.The PLL have one

in signal from the system clock and two output signals. One of the output signal

is the same as the system clock and is connected to the SDRAM controller, the

other output signal is phase with -3 ns and is connected to the SDRAM chip. Both

the SDRAM Contoller and the PLL curcit are added in the SOPC builder and the

code from the generated .sopc-file is extracted for each component and documented

in the Appendix. Because the NoC generator generates a .sopc file from an xml

document it is important to extract the code for each component, you should be

able to choose if you want to add SRAM, SDRAM or both in the NoC generator.

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Chapter 5

Conclusion and future work

By adding support for SRAM and SDRAM it becomes easier for the software

devel-opers to work with the Multi-core platform. It opens up for using larger programs.

Adding memories to an FPGA system takes lot of time and hard studies in the

handbooks about the Altera platform. Adding this feature to the NoC generator

saves a lot of time for the software developers.

In the future, CPU nodes in the Multi-core platofrm should be able to share the

connected external memories with other CPU nodes on the platform by requesting

data from them using some kind of Message Passing (MP) protocol. Also, at the

moment only Altera platforms is supported but in the future Xilinx and Leon3

systems will be supported.

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Bibliography

[1] Johnny Öberg, Francesco Robino,2011

A NoC System Generator for the

Sea-of-Cores Era,

[2] Quartus II Handbook Version 12.0

Volume 1: Design and Synthesis, june 2012,

[3] Altera,

Embedded Design Handbook ©February 2010 Altera Corporation,

[4] Altera,

Using the SDRAM on Alteras DE2-115 Board with Verilog Designs, July

2010

[5] Altera,

Using the SDRAM on Alteras DE2-115 Board with Verilog Designs, May

2012,

[6] Vinodh Cuppu, Bruce Jacob, Brian Davis, Trevor Mudge,1999

A Performance

Comparison of Contemporary DRAM Architectures

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Appendix A

Source code

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APPENDIX

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CODE

Bilaga A.1. Code for SDRAM and PLL

1−−−−−−−ELEMENTS−−−−−−−−−−−−−− 2 e l e m e n t s d r a m _ p l l . c 0 3 { 4 datum _clockDomain 5 { 6 v a l u e = " cl k _ 0 "; 7 t y p e = " S t r i n g "; 8 } 9 } 10 e l e m e n t s d r a m _ p l l . c 1 11 { 12 datum _clockDomain 13 { 14 v a l u e = " sdram_clk "; 15 t y p e = " S t r i n g "; 16 } 17 } 18 e l e m e n t s d r a m _ p l l . p l l _ s l a v e 19 { 20 datum _ l o c k e d A d d r e s s 21 { 22 v a l u e = " 0 "; 23 t y p e = " b o o l e a n "; 24 } 25 datum b a s e A d d r e s s 26 { 27 v a l u e = " 16 384 "; 28 t y p e = " l o n g "; 29 } 30 } 31 e l e m e n t sdram . s 1 32 { 33 datum _ l o c k e d A d d r e s s 34 { 35 v a l u e = " 1 "; 36 t y p e = " b o o l e a n "; 37 } 38 datum b a s e A d d r e s s 39 { 40 v a l u e = " 1 3 4 2 1 7 7 2 8 ";

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41 t y p e = " l o n g "; 42 } 43 } 44 e l e m e n t sdram 45 { 46 datum _ s o r t I n d e x 47 { 48 v a l u e = " 16 "; 49 t y p e = " i n t "; 50 } 51 datum m e g a w i z a r d _ u i p r e f e r e n c e s 52 { 53 v a l u e = " { o u t p u t _ l a n g u a g e=VHDL, o u t p u t _ d i r e c t o r y=C : \ \ . . . } "; 54 t y p e = " S t r i n g "; 55 } 56 } 57 e l e m e n t s d r a m _ p l l 58 { 59 datum _ s o r t I n d e x 60 { 61 v a l u e = " 15 "; 62 t y p e = " i n t "; 63 } 64 } 65−−−−−−−MODULE−−−−−−−−−−−−−− 66

67 <module k i n d=" a l t e r a _ n i o s 2 " v e r s i o n=" 1 0 . 0 " e n a b l e d=" 1 " name=" cpu_0 ">

68 . . . .

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APPENDIX

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APPENDIX

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CODE

PORT_UNUSED CT#PORT_PHASEUPDOWN PORT_UNUSED CT#PORT_extclk3 PORT_UNUSED CT#PORT_extclk2 PORT_UNUSED CT# PORT_extclk1 PORT_UNUSED CT#PORT_PHASECOUNTERSELECT PORT_UNUSED CT#PORT_extclk0 PORT_UNUSED CT#

PORT_ACTIVECLOCK PORT_UNUSED CT#CLK0_DUTY_CYCLE 50 CT#CLK0_DIVIDE_BY 1 CT#CLK1_DIVIDE_BY 1 CT#PORT_LOCKED PORT_UNUSED

233 PT#GLOCKED_FEATURE_ENABLED 0 PT#SPREAD_FEATURE_ENABLED 0 PT#BANDWIDTH_FREQ_UNIT MHz PT#CUR_DEDICATED_CLK c 0 PT#INCLK0_FREQ_EDIT 5 0 . 0 0 0 PT#BANDWIDTH_PRESET Low PT#PLL_LVDS_PLL_CHECK 0 PT# BANDWIDTH_USE_PRESET 0 PT#AVALON_USE_SEPARATE_SYSCLK NO PT#PLL_ENHPLL_CHECK 0 PT#OUTPUT_FREQ_UNIT1 MHz PT# OUTPUT_FREQ_UNIT0 MHz PT#PHASE_RECONFIG_FEATURE_ENABLED 1 PT#CREATE_CLKBAD_CHECK 0 PT#CLKSWITCH_CHECK 0 PT# INCLK1_FREQ_EDIT 1 0 0 . 0 0 0 PT#NORMAL_MODE_RADIO 1 PT#SRC_SYNCH_COMP_RADIO 0 PT#PLL_ARESET_CHECK 0 PT#

LONG_SCAN_RADIO 1 PT#SCAN_FEATURE_ENABLED 1 PT#PHASE_RECONFIG_INPUTS_CHECK 0 PT#USE_CLK1 1 PT#USE_CLK0 1 PT# PRIMARY_CLK_COMBO i n c l k 0 PT#BANDWIDTH 1 . 0 0 0 PT#GLOCKED_COUNTER_EDIT_CHANGED 1 PT#PLL_FASTPLL_CHECK 0 PT# SPREAD_FREQ_UNIT KHz PT#PLL_AUTOPLL_CHECK 1 PT#LVDS_PHASE_SHIFT_UNIT1 deg PT#LVDS_PHASE_SHIFT_UNIT0 deg PT# OUTPUT_FREQ_MODE1 0 PT#SWITCHOVER_FEATURE_ENABLED 0 PT#MIG_DEVICE_SPEED_GRADE Any PT#OUTPUT_FREQ_MODE0 0 PT# BANDWIDTH_FEATURE_ENABLED 1 PT#INCLK0_FREQ_UNIT_COMBO MHz PT#ZERO_DELAY_RADIO 0 PT#OUTPUT_FREQ1 1 0 0 . 0 0 0 0 0 0 0 0 PT#OUTPUT_FREQ0 1 0 0 . 0 0 0 0 0 0 0 0 PT#SHORT_SCAN_RADIO 0 PT#LVDS_MODE_DATA_RATE_DIRTY 0 PT#CUR_FBIN_CLK c 0 PT# PLL_ADVANCED_PARAM_CHECK 0 PT#CLKBAD_SWITCHOVER_CHECK 0 PT#PHASE_SHIFT_STEP_ENABLED_CHECK 0 PT#

DEVICE_SPEED_GRADE Any PT#PLL_FBMIMIC_CHECK 0 PT#LVDS_MODE_DATA_RATE { Not A v a i l a b l e } PT#LOCKED_OUTPUT_CHECK 0 PT#SPREAD_PERCENT 0 . 5 0 0 PT#PHASE_SHIFT1 −3.00000000 PT#PHASE_SHIFT0 0 . 0 0 0 0 0 0 0 0 PT#DIV_FACTOR1 1 PT#DIV_FACTOR0

1 PT#CNX_NO_COMPENSATE_RADIO 0 PT#USE_CLKENA1 0 PT#USE_CLKENA0 0 PT#CREATE_INCLK1_CHECK 0 PT# GLOCK_COUNTER_EDIT 1 0 4 8 5 7 5 PT#INCLK1_FREQ_UNIT_COMBO MHz PT#EFF_OUTPUT_FREQ_VALUE1 5 0 . 0 0 0 0 0 0 PT#

EFF_OUTPUT_FREQ_VALUE0 5 0 . 0 0 0 0 0 0 PT#SPREAD_FREQ 5 0 . 0 0 0 PT#USE_MIL_SPEED_GRADE 0 PT#EXPLICIT_SWITCHOVER_COUNTER 0 PT#STICKY_CLK1 1 PT#STICKY_CLK0 1 PT#EXT_FEEDBACK_RADIO 0 PT#MIRROR_CLK1 0 PT#MIRROR_CLK0 0 PT#

SWITCHOVER_COUNT_EDIT 1 PT#SELF_RESET_LOCK_LOSS 0 PT#PLL_PFDENA_CHECK 0 PT#INT_FEEDBACK__MODE_RADIO 1 PT# INCLK1_FREQ_EDIT_CHANGED 1 PT#CLKLOSS_CHECK 0 PT#SYNTH_WRAPPER_GEN_POSTFIX 0 PT#PHASE_SHIFT_UNIT1 ns PT# PHASE_SHIFT_UNIT0 deg PT#BANDWIDTH_USE_AUTO 1 PT#HAS_MANUAL_SWITCHOVER 1 PT#MULT_FACTOR1 1 PT#MULT_FACTOR0 1 PT#SPREAD_USE 0 PT#GLOCKED_MODE_CHECK 0 PT#SACN_INPUTS_CHECK 0 PT#DUTY_CYCLE1 5 0 . 0 0 0 0 0 0 0 0 PT#

INTENDED_DEVICE_FAMILY { C y c l o n e IV E} PT#DUTY_CYCLE0 5 0 . 0 0 0 0 0 0 0 0 PT#PLL_TARGET_HARCOPY_CHECK 0 PT# INCLK1_FREQ_UNIT_CHANGED 1 PT#RECONFIG_FILE ALTPLL1335359197336492 . m i f PT#ACTIVECLK_CHECK 0

234 UP#c 1 u s e d UP#c 0 u s e d UP#i n c l k 0 used

235 IN#WIDTH_CLOCK 1 IN#CLK0_DUTY_CYCLE 1 IN#PLL_TARGET_HARCOPY_CHECK 1 IN# CLK1_MULTIPLY_BY 1 IN#SWITCHOVER_COUNT_EDIT 1 IN#INCLK0_INPUT_FREQUENCY 1 IN#PLL_LVDS_PLL_CHECK 1 IN# PLL_AUTOPLL_CHECK 1 IN#PLL_FASTPLL_CHECK 1 IN#CLK1_DUTY_CYCLE 1 IN#PLL_ENHPLL_CHECK 1 IN#DIV_FACTOR1 1 IN# DIV_FACTOR0 1 IN#LVDS_MODE_DATA_RATE_DIRTY 1 IN#GLOCK_COUNTER_EDIT 1 IN#CLK0_DIVIDE_BY 1 IN#MULT_FACTOR1 1 IN# MULT_FACTOR0 1 IN#CLK0_MULTIPLY_BY 1 IN#USE_MIL_SPEED_GRADE 1 IN#CLK1_DIVIDE_BY 1

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237 IF#l o c k e d { o u t p u t 0} IF#r e s e t { i n p u t 0} IF#c l k { i n p u t 0} IF#r e a d d a t a { o u t p u t 32} IF#w r i t e { i n p u t 0} IF#p h a s e d o n e { o u t p u t 0} IF#a d d r e s s { i n p u t 2} IF#c 1 { o u t p u t 0} IF#c 0 { o u t p u t 0} IF#

w r i t e d a t a { i n p u t 32} IF#r e a d { i n p u t 0}

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241 </module> 242 243 <module 244 k i n d=" a l t e r a _ a v a l o n _ n e w _ s d r a m _ c o n t r o l l e r " 245 v e r s i o n=" 1 0 . 0 " 246 e n a b l e d=" 1 " 247 name=" sdram "> 248 249 250 251 252 253 254 255 256 257 258 259 260 261

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APPENDIX

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282 k i n d=" a v a l o n " 283 v e r s i o n=" 6 . 1 " 284 s t a r t=" cpu_0 . i n s t r u c t i o n _ m a s t e r " 285 end=" sdram . s 1 "> 286 287 288 </ c o n n e c t i o n >

289 <c o n n e c t i o n k i n d=" a v a l o n " v e r s i o n=" 6 . 1 " s t a r t=" cpu_0 . data_master " end=" sdram . s 1 ">

290 291 292 </ c o n n e c t i o n > 293 <c o n n e c t i o n 294 k i n d=" c l o c k " 295 v e r s i o n=" 1 0 . 0 " 296 s t a r t=" s y s _ c l k . c l k " 297 end=" s d r a m _ p l l . i n c l k _ i n t e r f a c e " /> 298 <c o n n e c t i o n k i n d=" c l o c k " v e r s i o n=" 1 0 . 0 " s t a r t=" s y s _ c l k . c l k " end=" sdram . c l k " />

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Bilaga A.2. Code for SRAM and Tristate Bridge

1−−−−−−−ELEMENTS−−−−−−−−−−−−−− 2 e l e m e n t sram_1024Kx16bit . a v a l o n _ t r i s t a t e _ s l a v e 3 { 4 datum b a s e A d d r e s s 5 { 6 v a l u e = " 4 1 9 4 3 0 4 "; 7 t y p e = " l o n g "; 8 } 9 } 10 e l e m e n t sram_1024Kx16bit 11 { 12 datum _ s o r t I n d e x 13 { 14 v a l u e = " 17 "; 15 t y p e = " i n t "; 16 } 17 } 18 e l e m e n t t r i _ s t a t e _ b r i d g e _ 0 19 { 20 datum _ s o r t I n d e x 21 { 22 v a l u e = " 18 "; 23 t y p e = " i n t "; 24 } 25 datum m e g a w i z a r d _ u i p r e f e r e n c e s 26 {

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APPENDIX

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39 <module 40 k i n d=" sram_1024Kx16bit " 41 v e r s i o n=" 1 . 0 " 42 e n a b l e d=" 1 " 43 name=" sram_1024Kx16bit "> 44 45 </module> 46 <module 47 k i n d=" a l t e r a _ a v a l o n _ t r i _ s t a t e _ b r i d g e " 48 v e r s i o n=" 1 0 . 0 " 49 e n a b l e d=" 1 " 50 name=" t r i _ s t a t e _ b r i d g e _ 0 "> 51 52 </module> 53 54−−−−CONNECTION−−−−−−−−−−−−−−−− 55 <c o n n e c t i o n 56 k i n d=" a v a l o n " 57 v e r s i o n=" 6 . 1 " 58 s t a r t=" cpu_1 . i n s t r u c t i o n _ m a s t e r " 59 end=" t r i _ s t a t e _ b r i d g e _ 0 . a v a l o n _ s l a v e "> 60 61 62 </ c o n n e c t i o n > 63 64 65 <c o n n e c t i o n 66 k i n d=" a v a l o n " 67 v e r s i o n=" 6 . 1 " 68 s t a r t=" cpu_1 . data_master " 69 end=" t r i _ s t a t e _ b r i d g e _ 0 . a v a l o n _ s l a v e "> 70 71 72 </ c o n n e c t i o n > 73 74 <c o n n e c t i o n 75 k i n d=" a v a l o n _ t r i s t a t e " 76 v e r s i o n=" 1 0 . 0 " 77 s t a r t=" t r i _ s t a t e _ b r i d g e _ 0 . t r i s t a t e _ m a s t e r " 78 end=" sram_1024Kx16bit . a v a l o n _ t r i s t a t e _ s l a v e "> 79

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80 81 </ c o n n e c t i o n > 82 83 <c o n n e c t i o n 84 k i n d=" c l o c k " 85 v e r s i o n=" 1 0 . 0 " 86 s t a r t=" s y s _ c l k . c l k " 87 end=" t r i _ s t a t e _ b r i d g e _ 0 . c l k " />

Bilaga A.3. Tcl code for SRAM

1 #TCL F i l e G e n e r a t e d by Component E d i t o r 1 0 . 0

2 #Wed Apr 25 1 5 : 1 5 : 4 4 CEST 2012

3 #DO NOT MODIFY 4 5 6 #+−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−− 7 # | 8 # | sram_1024Kx16bit " sram_1024Kx16bit " v1 . 0 9 # | n u l l 2 0 1 2 . 0 4 . 2 5 . 1 5 : 1 5 : 4 4 10 # | 11 # | 12 #+−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−− 13 14 #+−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−− 15 # | r e q u e s t TCL p a c k a g e from ACDS 1 0 . 0 16 # |

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APPENDIX

A. SOUR

CE

CODE

31 s e t _ m o d u l e _ p r o p e r t y ANALYZE_HDL TRUE 32 # | 33 #+−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−− 34 35 #+−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−− 36 # | f i l e s 37 # | 38 # | 39 #+−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−− 40 41 #+−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−− 42 # | p a r a m e t e r s 43 # | 44 # | 45 #+−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−− 46 47 #+−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−− 48 # | d i s p l a y i t e m s 49 # | 50 # | 51 #+−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−− 52 53 #+−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−− 54 # | c o n n e c t i o n p o i n t a v a l o n _ t r i s t a t e _ s l a v e 55 # | 56 a d d _ i n t e r f a c e a v a l o n _ t r i s t a t e _ s l a v e a v a l o n _ t r i s t a t e end

57 s e t _ i n t e r f a c e _ p r o p e r t y a v a l o n _ t r i s t a t e _ s l a v e a ctiveCSTh roughReadL atency f a l s e

58 s e t _ i n t e r f a c e _ p r o p e r t y a v a l o n _ t r i s t a t e _ s l a v e e x p l i c i t A d d r e s s S p a n 0 59 s e t _ i n t e r f a c e _ p r o p e r t y a v a l o n _ t r i s t a t e _ s l a v e holdTime 5 60 s e t _ i n t e r f a c e _ p r o p e r t y a v a l o n _ t r i s t a t e _ s l a v e isMemoryDevice t r u e 61 s e t _ i n t e r f a c e _ p r o p e r t y a v a l o n _ t r i s t a t e _ s l a v e i s N o n V o l a t i l e S t o r a g e f a l s e 62 s e t _ i n t e r f a c e _ p r o p e r t y a v a l o n _ t r i s t a t e _ s l a v e maximumPendingReadTransactions 0 63 s e t _ i n t e r f a c e _ p r o p e r t y a v a l o n _ t r i s t a t e _ s l a v e p r i n t a b l e D e v i c e f a l s e 64 s e t _ i n t e r f a c e _ p r o p e r t y a v a l o n _ t r i s t a t e _ s l a v e r e a d L a t e n c y 0 65 s e t _ i n t e r f a c e _ p r o p e r t y a v a l o n _ t r i s t a t e _ s l a v e r e a d W a i t S t a t e s 15 66 s e t _ i n t e r f a c e _ p r o p e r t y a v a l o n _ t r i s t a t e _ s l a v e readWaitTime 15 67 s e t _ i n t e r f a c e _ p r o p e r t y a v a l o n _ t r i s t a t e _ s l a v e setupTime 5 68 s e t _ i n t e r f a c e _ p r o p e r t y a v a l o n _ t r i s t a t e _ s l a v e t i m i n g U n i t s N a n o s e c o n d s 69 s e t _ i n t e r f a c e _ p r o p e r t y a v a l o n _ t r i s t a t e _ s l a v e w r i t e W a i t S t a t e s 10 70 s e t _ i n t e r f a c e _ p r o p e r t y a v a l o n _ t r i s t a t e _ s l a v e writeWaitTime 10 71

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72 s e t _ i n t e r f a c e _ p r o p e r t y a v a l o n _ t r i s t a t e _ s l a v e ASSOCIATED_CLOCK " " 73 s e t _ i n t e r f a c e _ p r o p e r t y a v a l o n _ t r i s t a t e _ s l a v e ENABLED t r u e 74 75 a d d _ i n t e r f a c e _ p o r t a v a l o n _ t r i s t a t e _ s l a v e d a t a d a t a B i d i r 16 76 a d d _ i n t e r f a c e _ p o r t a v a l o n _ t r i s t a t e _ s l a v e cs_n c h i p s e l e c t _ n I n p u t 1 77 a d d _ i n t e r f a c e _ p o r t a v a l o n _ t r i s t a t e _ s l a v e a d d r e s s a d d r e s s I n p u t 20 78 a d d _ i n t e r f a c e _ p o r t a v a l o n _ t r i s t a t e _ s l a v e oe_n o u t p u t e n a b l e _ n I n p u t 1 79 a d d _ i n t e r f a c e _ p o r t a v a l o n _ t r i s t a t e _ s l a v e we_n w r i t e _ n I n p u t 1 80 a d d _ i n t e r f a c e _ p o r t a v a l o n _ t r i s t a t e _ s l a v e be_n b y t e e n a b l e _ n I n p u t 2 81 # | 82 #+−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−

Adding DRAM and SRAM support for the NoC Generator