Institutionen för systemteknik
Department of Electrical Engineering
Master’s Thesis
Power Efficient Digital Decimation Filters for
Σ∆-ADCs
Master’s Thesis conducted in Electronic Devices at The Institute of Technology, Linköping University
by
Love Cederström
LiTH-ISY-EX--09/4279--SE
Linköping 2009
Department of Electrical Engineering Linköpings tekniska högskola Linköpings universitet Linköpings universitet SE-581 83 Linköping, Sweden 581 83 Linköping
Power Efficient Digital Decimation Filters for
Σ∆-ADCs
Master’s Thesis conducted in Electronic Devices at
The Institute of Technology, Linköping University
by
Love Cederström
LiTH-ISY-EX--09/4279--SE
Supervisor: Atila Alvandpour
isy, Linköping University
Co-Supervisor: Ali Fazli Yeknami
isy, Linköping University
Examinator: Atila Alvandpour
isy, Linköping University
Avdelning, Institution Division, Department
Division of Electronic Devices Department of Electrical Engineering Linköpings universitet
SE-581 83 Linköping, Sweden
Datum Date 2009-06-12 Språk Language Svenska/Swedish Engelska/English ⊠ Rapporttyp Report category Licentiatavhandling Examensarbete C-uppsats D-uppsats Övrig rapport ⊠
URL för elektronisk version
http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-51464
ISBN — ISRN
LiTH-ISY-EX--09/4279--SE Serietitel och serienummer Title of series, numbering
ISSN —
Titel
Title Effektsnåla digitala decimeringsfilter för Σ∆-ADC:erPower Efficient Digital Decimation Filters for Σ∆-ADCs
Författare
Author Love Cederström
Sammanfattning Abstract
The development of integrated circuit technology seen in the last decades has enabled a large variety of battery operated equipment to emerge, such as small sensors and medical implants. These applications often has low requirements on sampling frequency but require a very low power consumption to achieve a long battery life.
This thesis investigates one aspect of implementing a low power and low fre-quency analog to digital converter (ADC) using a technique called Σ∆-modulation. The Σ∆-ADC uses few analog components but instead it requires a digital filter to extract the wanted resolution. It is this filter which is under investigation in this work.
To investigate the power consumption under the presumption that the filter would be a custom circuit implemented on-chip, a simplistic approach has been taken. Based on a high-level algorithmic investigation and the fact that it is popularly used together with Σ∆-modulators the Cascaded Integrator Comb (CIC) filter was chosen for implementation.
The CIC-filter uses only adders and delay elements which is a great advantage when aiming at a low power consumption. The drawback is that this filter has a poor passband which can introduce distortion within the signal band. Using the Spectre simulator provided in the Cadence Virtuoso suite the lowest power consumption achieved was 16 nW, extracting 80 % of the theoretically available resolution.
Nyckelord
Abstract
The development of integrated circuit technology seen in the last decades has enabled a large variety of battery operated equipment to emerge, such as small sensors and medical implants. These applications often has low requirements on sampling frequency but require a very low power consumption to achieve a long battery life.
This thesis investigates one aspect of implementing a low power and low fre-quency analog to digital converter (ADC) using a technique called Σ∆-modulation. The Σ∆-ADC uses few analog components but instead it requires a digital filter to extract the wanted resolution. It is this filter which is under investigation in this work.
To investigate the power consumption under the presumption that the filter would be a custom circuit implemented on-chip, a simplistic approach has been taken. Based on a high-level algorithmic investigation and the fact that it is popularly used together with Σ∆-modulators the Cascaded Integrator Comb (CIC) filter was chosen for implementation.
The CIC-filter uses only adders and delay elements which is a great advantage when aiming at a low power consumption. The drawback is that this filter has a poor passband which can introduce distortion within the signal band. Using the Spectre simulator provided in the Cadence Virtuoso suite the lowest power consumption achieved was 16 nW, extracting 80 % of the theoretically available resolution.
Acknowledgments
I would like to thank Professor Atila Alvandpour for the opportunity to do my thesis at the Division of Electronic Devices. Further I would like to thank Ali Fazli Yeknami for all the technical discussions, and not to mention the other PhD students at the division.
My thoughts also go to my office mates, Fahad and Saeed, thanks for being there for bouncing ideas, about everything between heaven and earth.
I would also like to thank the annoying people who dragged me away on too long coffee breaks, you know who you are. Last, but not least, I thank my family for all the support through the years.
Contents
I
Background
1 Introduction 1 1.1 Motivation . . . 1 1.2 Thesis Objective . . . 1 1.2.1 Specifications . . . 1 1.2.2 Limitations . . . 2 1.2.3 Prerequisites . . . 3 1.3 Thesis Overview . . . 3 2 Semiconductor Technology 5 2.1 VLSI Technology . . . 5 2.1.1 Brief History . . . 5 2.1.2 Process Variations . . . 6 2.2 The MOSFET . . . 7 2.2.1 Analog Operation . . . 8 2.2.2 Digital Operation . . . 8 2.2.3 Sub-Threshold Operation . . . 9 2.2.4 Power dissipation . . . 9 2.3 Circuit Design . . . 10 2.3.1 Device Sizing . . . 102.3.2 The CMOS Inverter . . . 10
2.3.3 The Transmission Gate . . . 11
2.3.4 The D-Flip-Flop . . . 11
2.3.5 The Adder . . . 12
3 A/D-Conversion 15 3.1 The Basics of A/D-Conversion . . . 15
3.1.1 Direct A/D-Conversion . . . 16 3.1.2 D/A Conversion . . . 17 3.1.3 The SAR-ADC . . . 17 3.2 The Σ∆-ADC . . . 19 3.2.1 The Modulator . . . 19 3.2.2 Linear Model . . . 20 3.2.3 Noise Analysis . . . 21 ix
x Contents 3.3 Trade-offs . . . 23 3.3.1 Flash-ADC . . . 23 3.3.2 SAR-ADC . . . 23 3.3.3 Σ∆-ADC . . . 23 3.4 Summary . . . 24 4 Digital Decimation 25 4.1 The Basic Concepts . . . 25
4.1.1 Multistage Decimation . . . 25
4.1.2 Polyphase Decomposition . . . 26
4.2 Filter Design . . . 28
4.2.1 Design Choices . . . 29
4.2.2 Design Flow . . . 29
4.3 The Cascaded Integrator Comb Filter . . . 29
4.4 Trade-offs . . . 31
II
Implementation
5 Design 35 5.1 Filter Requirements . . . 35 5.2 Filter Evaluation . . . 36 5.2.1 Specification . . . 36 5.2.2 ENOB Evaluation . . . 37 5.3 Multistage Decimation . . . 395.3.1 The sincN-Filter . . . 40
5.3.2 Generic FIR-filters . . . 40
5.4 Simulations . . . 41
5.5 Summary . . . 44
6 HDL Implementation 45 6.1 Cadence and VerilogA . . . 45
6.2 The Σ∆-Modulator . . . 45
6.2.1 First Order Modulator . . . 46
6.2.2 Second Order Modulator . . . 46
6.3 The Cascaded Integrator Comb . . . 46
6.3.1 The Integrator Section . . . 47
6.3.2 The Comb Section . . . 48
6.3.3 The Components . . . 48
6.4 Simulations . . . 48
6.4.1 System Simulation Results . . . 48
Contents xi 7 Circuit Implementation 51 7.1 Practical Aspects . . . 51 7.1.1 Implementation Philosophy . . . 51 7.1.2 ST Microelectronics 90 nm Process . . . 51 7.2 The DFF . . . 52 7.3 The FA . . . 52
7.3.1 Low Transistor count FA’s . . . 53
7.3.2 The Static CMOS 28 Transistor FA . . . 53
7.3.3 The 24 Transistor Mirror FA . . . 54
7.4 The DFF and the 24T FA in the CIC . . . 55
7.5 Simulations . . . 57
7.5.1 System Simulation Results . . . 57
7.5.2 Power Consumption . . . 57 8 Conclusions 59 8.1 Previous Work . . . 59 8.2 Concluding Remarks . . . 60 8.3 Future Work . . . 60
III
Appendices
Bibliography 63 A Matlab Code 67 A.1 Modulator Specifications . . . 67A.2 Filter Evaluation . . . 68
A.2.1 NTF and Filter Specification . . . 68
A.2.2 Comparison with Ideal Filter . . . 70
A.2.3 ENOB Calculation . . . 71
A.3 The sincN Filter . . . 72
A.3.1 The Filter . . . 72
A.3.2 Evaluation Loop . . . 72
A.4 Generic FIR using Parks-McClellan Algorithm . . . 72
A.5 Multistage Decimation . . . 73
A.5.1 Single Stage, sincN . . . 73
A.5.2 Two Stage, sincN→ sincN . . . 74
A.5.3 Two Stage, FIR → FIR . . . 76
A.6 Filter Implementation Evaluation . . . 78
A.6.1 Cadence Filter Evaluation . . . 78
A.6.2 Cadence ENOB Evaluation . . . 78
B VerilogA Code 80 B.1 Modulator . . . 80
B.1.1 ADC . . . 80
B.1.2 DAC . . . 81
xii Contents B.1.4 Integrator . . . 82 B.2 Decimation Filter . . . 82 B.2.1 The FA . . . 82 B.2.2 The DFF . . . 83 C Nomenclature 84 C.1 Symbols . . . 84 C.2 Abbreviations . . . 84
Part I
Chapter 1
Introduction
In which the background and objectives of this thesis are presented and a short orientational overview is given.
1.1
Motivation
The last decades has seen a tremendous development of integrated circuits. This has enabled a large variety of portable applications that depend on power efficient solutions. The cornerstone of every piece of equipment that should respond to the surrounding environment is the analog to digital converter (ADC). Examples of applications where data should be retrieved and made available for digital process-ing are many types of sensors and medical implants. In these cases a low samplprocess-ing rate can be adequate to describe the measured signal.
With the requirement on long battery life in these applications the requirements on power efficient ADC’s has increased. The conventional approach when deciding on an ADC architecture with low sample rate and low power consumption is to use a successive approximation register (SAR) type ADC. To challenge the common practice the idea is to see if a Σ∆-ADC is a viable option.
1.2
Thesis Objective
The main goal of this master’s thesis is to investigate how much power dissipation is to be expected from the digital decimation filter in a low frequency Σ∆-ADC of moderate resolution.
1.2.1
Specifications
Specifying the signal frequency bandwidth (fb) and a required resolution is
funda-mental to enable investigation of how to design an ADC and in this case a deci-mation filter is part of the ADC. To specify the signal frequency bandwidth for a low frequency applications in general is difficult. Because the aim is low power,
2 Introduction
cardiac applications has been chosen to set the requirements on signal bandwidth, since these applications present cases where extreme low power consumption is required (pacemakers). What the frequency bandwidth of cardiac signals is differs depending on source.
Two reasonably recent (2001 and 2003) IEEE publications on the topic of decimation and A/D conversion for cardiac applications states that the signal bandwidth ranges from 20 to 150 Hz [21] and 150 to 200 Hz [6] respectively. An-other, older (1973), IEEE publication states that waveforms are distorted with filter cutoff frequencies lower than 500 Hz [13].
Outside the scope of IEEE, the American Heart Association and the journal Circulation recommends a minimum sampling rate of 500 Hz (fb= 250 Hz). It is
also concluded that a bandwidth of at least 500 Hz is required if all measurable frequency components of interest are to be reproduced [18].
The other property, the resolution, is more difficult to specify because it de-pends on what application the ADC is intended for. However it is known that the SAR-ADC is very efficient up to 10 or 12 bits but after that linearity issues makes it necessary to add calibration circuitry [17]. Since the Σ∆-ADC is meant to challenge the SAR-ADC a 12-bit resolution at the SAR’s upper limit is very interesting when a 10-bit is not.
The choice for the implementation and simulation is a 90 nm process from ST Microelectronics. The 90 nm process‘ has issues with leakage due to short channel effects and is therefore representative for todays technologies. The trade-offs associated with leaky technologies are very much present in this 90 nm process. Consequently the choice of process technology was made because it represents a mid-range technology which makes it a viable option for real circuits.
The specifications can be summarized to that a decimation filter for a Σ∆-ADC should be implemented in a 90 nm technology, the signal frequency bandwidth is 500 Hz and the required resolution (Wreq.) is 12 bits.
1.2.2
Limitations
This thesis has an implementational perspective on the subject of the decimation filter. This means that the focus is not on an optimization that would yield the best possible characteristics of the filter. Instead it is the actual achievable power consumption that is the main focus.
Another limitation is that the application is not strictly specified, this implies that the signal that is going to be A/D-converted is unknown. The focus of this thesis is the pure circuit implementational aspects and trade-offs of Σ∆-ADC’s, therefore there is no emphasis on how different applications would respond to different phase characteristics and other aspects of a digital filter.
Because the aim is a power efficient ADC the choice of Σ∆-modulator can be narrowed. The fact that a low frequency application enables high oversampling ratios makes the simplicity of a 1:st order Σ∆-modulator with a 1-bit quantizer possible.
1.3 Thesis Overview 3
1.2.3
Prerequisites
The reader is assumed to know the basic concepts of electrical circuits and basic filter theory i.e. aliasing and the Nyquist theorem [19]. The ambition is that the end result and conclusions should be understood even if the reader does not have a rock solid background in electrical engineering and circuit design.
1.3
Thesis Overview
This thesis is divided into three parts where Part I gives a background, Part II describes the implementation and conclusions and Part III contains bibliography and appendices.
Part I, Background
Chapter 2, Technology: In modern technologies there are a lot off issues
con-cerning the basic operation of a transistor, this chapter gives a short overview of these issues.
Chapter 3, A/D-Conversion: This chapter addresses the basics of A/D-conversion
and gives a background to why the decimation filter is needed and why the Σ∆-ADC is of interest.
Chapter 4, Digital Decimation: This chapter gives a background on what a
digital decimation filter is and addresses different challenges in decimation filter design.
Part II, Implementation
Chapter 5, Design: To investigate different filters simulations at an algorithmic
level were conducted. In the light of the previous chapters this chapter concludes why the CIC-filter was chosen for implementation.
Chapter 6, HDL Implementation: The CIC-filters is described on an
architec-tural and component level. Simulations has been performed using VerilogA descriptions of the components.
Chapter 7, Circuit Implementation: In this chapter the individual transistor
models of the used components are described together with the resulting power consumption.
Chapter 8, Conclusions: To situate this work in a larger perspective a
compar-ative study of decimation filters is presented and the conclusions drawn from this work are presented.
Part III, Appendices
Bibliography: The Bibliography contain all sources used in the writing of this
thesis.
Appendix A, Matlab Code: This Appendix contains the code used in the
4 Introduction Appendix B, VerilogA Code: The HDL-descriptions of the different
compo-nents is included in the Appendix.
Appendix C, Nomenclature: Here the reoccurring symbols and abbreviations
Chapter 2
Semiconductor Technology
In which the fundamental device of modern integrated circuits, the transistor, is described together with some historical perspective. There is also a short section on circuit design and on the operation of an adder and a storage element. For the most part this chapter has its source material in three commonly used and available books; Rabaey et al. [5], Razavi [22] and Streetman et al. [25].
2.1
VLSI Technology
With the scaling in technology seen the past decades more and more functional-ity can be located on a very small area, this is called Very Large Scale Integra-tion (VLSI). This has made it cost efficient to migrate more and more funcIntegra-tional blocks onto the same chip. Consequently the ADC’s also has made it on-chip. With ADC’s implemented directly on-chip the requirement for the high volume semiconductor technologies to provide both analog and digital functionality has emerged.
2.1.1
Brief History
The transistor was invented in 1947 at Bell Telephone Laboratories [5, pp. 4]. The history of electrical computational technology started in the 1940’s with, amongst others, the vacuum tube computer ENIAC (completed 1946). ENIAC consisted of 18,000 vacuum tubes, consumed 140 kW [2] and was not using the digital number system like modern computers but had 10 different voltage levels represent the numbers 0-10.
The utilization of the binary numerical system and implementations with dis-crete transistors increased the complexity and performance of computers to a great extent. But it was not until the invention of the integrated circuit (IC) in 1958 that the development gained real speed. The IC enabled transistors and passive devices like resistors and capacitors to be integrated in the same component, which lead the way to complex systems of a small area. Consumer products became available
6 Semiconductor Technology
in the form of handheld calculators in the late 60’s and in 1971 Texas Instru-ments introduced the “calculator on chip” circuit which made the truly handheld pocket calculator commonly available. Almost simultaneously with Texas Instru-ments the Intel corporation introduced their 4004 microprocessor for calculators and from there the development took of at a staggering speed [1]. As seen in Table 2.1, the 4004 microprocessor was only the beginning.
Table 2.1: Intel Microprocessor Development Year Description Transistor
count Operating frequency Feature size 1958 The first IC 1 - -1971 Intel 4004 2,300 108 KHz 10 µm 1979 Intel 8088 29,000 8 MHz 3 µm 1985 Intel 386 DX 275,000 33 MHz 1 µm 1997 Intel Pentium 2 7.5 million 300 MHz 0.35 µm 2008 Intel Core2 Quad 820 million 2.83 GHz 45 nm
Today the semiconductor technology is present in almost all consumer elec-tronic products and the performance is still increasing at a very high rate, e.g. a standard 3G mobile phone has approximately the same computational perfor-mance as the Pentium 4 from 2000. A more low power application specific example of this is the pacemaker which, not very surprisingly, contain several digital com-ponents. But it is still mesmerizingly amazing that one pacemaker can contain 20 million transistors, more than twice of that of a high performance processor from 1997, and have a battery life of 7 to 10 years [24].
2.1.2
Process Variations
Components in an IC have a certain minimum distance between the adjacent layers and regions of material that make each device. When discussing IC’s it is customary to specify which manufacturing process it is made in, e.g a 45 nm process has a minimum feature size of 45 nm (very simplified). Some measures are even smaller, one example is the gate oxide in a MOSFET (see the next section) which is reaching its fundamental limit. Today the insulation is only a few atom layers thick, approximately 1 nm with new insulator materials [29].
As seen in the previous section a modern IC contains several millions of transis-tors. This makes it impossible to manipulate the individual atoms since large scale manufacturing processes utilizing lithography to process scores of components at the same time is used. This implies that no two devices in a component will have the same exact size and specification, and it makes it impossible to use e.g. capacitors of exactly specified values.
These variations are called process variations and are especially crucial for the performance of on-chip analog devices since the operation of an analog circuit can depend on the size of a capacitor, resistor or transistor in analog operation. Nonetheless it is possible to use analog devices because two adjacent devices will
2.2 The MOSFET 7
be very closely matched even though they are not of a well defined value. This is done by relying on the ratio between passive devices (i.e. capacitors or resistors) instead of the actual specification (i.e. capacitance or resistance) of the device.
Process variations has an impact on digital circuitry as well as analog, but not at all to an extent comparable with that of analog devices. This is because digital devices are acting as switches with certain voltage level bands considered logic ’1’ or logic ’0’. The mismatch between transistors in digital operation can however have an impact on the required supply voltage and the maximum operating frequency at which correct operation is possible.
The most obvious way to avoid the impact of process variations as much as possible is to make use of as few passive components and transistors involved in analog operation as possible.
2.2
The MOSFET
The Metal Oxide Semiconductor Field Effect Transistor (MOSFET) is the most common device in digital circuitry today. It is the device of choice for most appli-cations because of the availability of cheap manufacturing processes.
The MOSFET is a 4 terminal device with the schematic view seen in Figure 2.1. The basic operation is that the gate (G) voltage (VG) controls the resistance
in the channel between source (S) and drain (D). The fourth terminal is the bulk (B) terminal, and this is connected to a fixed voltage (VB) to give the channel a
point of reference.
D G
S B
Figure 2.1: The MOSFET as a schematic symbol, in this case the NMOS. There are two types of MOSFET’s, P-type and N-type, and they are referred to as PMOS and NMOS. The difference between them is that a positive VG (VG>
VB) reduces the resistance between source and drain on the NMOS and negative
VG(VG< VB) reduces the resistance on the PMOS. These properties are the result
of the different types of carriers used to conduct current through the channel in the different devices. The NMOS uses electrons (negatively charged, hence the N) and the PMOS uses holes (positively charged, hence the P). The holes are actually only lack of electrons which implies that the carriers moving are actually electrons, the interested reader is referred to Streetman et al. [25]. The key point of this is that holes are much slower than electrons simply because a hole moving is a large quantity of electrons moving, thus making the PMOS a slower device than the NMOS.
In a schematic view the PMOS is distinguished by having a small circle on the gate terminal input to indicate the inverted behavior to that of the NMOS. In normal operation the bulk terminal is connected to a supply voltage (Vdd) for
8 Semiconductor Technology
PMOS and ground (Vss) for NMOS. Because this is the standard way of operation
the transistors are most often viewed as three terminal devices where the bulk is assumed to be correctly biased.
ID
VDS
VGS1
VGS2
VGS3
Figure 2.2: The current-voltage characteristics of a NMOS transistor, VGS3 >
VGS2> VGS1> 0.
The behavior of the transistor is illustrated in Figure 2.2 where the NMOS source and drain are connected to Vss and Vdd respectively. The drawn
voltage-current characteristics show the drain voltage-current (ID) as a function of the drain source
voltage (VDS = VD−VS) for different gate source voltages (VGS = VG−VS). The
transistor is considered to be on if VGS is larger than a certain threshold voltage,
VT.
2.2.1
Analog Operation
In analog circuitry the MOSFET can be operated as many different analog devices, one example is the amplifier. As seen in Figure 2.2, ID increases with increasing
VGSand this is the basic concept of an amplifier. Here there is no specified state
where the transistor is considered to be on, but the important thing is that it has a linear behavior and that its specification is the same as other devices on chip that should act the same way.
2.2.2
Digital Operation
In digital circuitry the transistor is operated as a switch where the gate voltage controls if the resistance between the two other terminals is high or low. These switches can be put together to perform logical (boolean) operations on binary numbers.
2.2 The MOSFET 9
This way of operating the transistor makes it possible to use high switching speeds and a large number of transistors because there is no need for the transistors to produce the exact same output given a certain input. The only requirement is that the transistor is on when VGis larger than VT. Using a Vddthat is sufficiently
larger than VTand use this Vddas ’1’ will give high switching speeds which enable
the circuit to be run at a high clock frequency.
The NMOS conducts a ’0’ better than a ’1’ and the PMOS has the opposite characteristic. This is a phenomenon inherited from how the bulk is biased. The NMOS bulk and implicitly the channel is biased to Vss (’0’) and the PMOS is
biased to Vdd (’1’).
To clarify this a NMOS device can be considered to be “on”, and that it should conduct a ’0’ or in other words discharge the drain to Vss. Because the bulk and
hence the channel is biased to Vss the drain can be fully discharged to Vss.
If the same thought experiment is made on a PMOS device where the channel is biased to Vdd it becomes obvious that the PMOS cannot discharge the drain to
Vss through a channel connected to Vdd, instead it will be able to discharge it to
VS- VT.
2.2.3
Sub-Threshold Operation
A transistor can be used in digital circuitry and operated with a Vddlower than VT,
this is called sub-threshold operation. It might seem awkward that the transistor can be operated with a Vdd (and hence a ’1’) that would never allow voltages at
the gate which makes the transistor to be considered on. But as seen in Figure 2.2 the transistor still conducts although VG is low, but not at all as much as in
normal digital operation.
This sub-threshold operation makes the transistors switch very slow compared to the speeds seen in normal operation. Another impact of sub-threshold operation is that devices are more sensitive to process variations. What in normal operation is only a minor voltage fluctuation well within the bounds for a well defined ’1’ or ’0’ can mean a malfunctioning circuit.
2.2.4
Power dissipation
Power is consumed by drawing charges from the power supply an then discharging them to ground. In a transistor there are a lot of parasitic capacitors. Charging and discharging these capacitors is called dynamic power consumption, but there is also a static power consumption that is present because the transistors are actually leaking a small amount of current even when they are off. This leakage current has come to be a major factor in recent years when the feature sizes has gone into the deep sub-micron domain.
Power is dissipated as heat through the friction when carriers are moving in an electric circuit. When an circuit is operated a lot of capacitors are being charged and discharged. The power consumption is known to be [26]:
10 Semiconductor Technology
Equation 2.1 is a very useful tool for measuring the power consumption of a circuit, all that is needed is a number on the average current and knowledge of what the power supply voltage is.
2.3
Circuit Design
There are a lot of circuit design techniques, one of them is Complementary Metal Oxide Semiconductor or CMOS for short. The static CMOS technique is a very commonly used technique and is the one used in this thesis. The CMOS technique is based on the duality of NMOS and PMOS transistors where a Pull Up Network (PUN) of PMOS transistors are used to pull the output up to Vdd (’1’) and a Pull
Down Network (PDN) of NMOS transistors are used to pull the output down to Vss (’0’).
To illustrate the principle of constructing logic functions the transistor imple-mentation of the CMOS inverter and the transmission gate is introduced after a section on the sizing of transistors.
2.3.1
Device Sizing
When designing circuits with transistors of a specific manufacturing process there are usually two parameters that the designer can change. These two are the channel length and the channel width. The width and length of the channel decide the resistance in the channel because the number of available carriers is proportional to the amount of material present. Since the PMOS device is slower than the NMOS device the PMOS needs to be sized differently, i.e. with a larger width to allow the devices to be operated at the same speed.
Now the seemingly simple solution to make a device as fast as possible would be to size the transistors as large as possible because the delay is known to be proportional to the resistance and capacitance of a device. But a large channel creates a large gate area, and since the gate and channel with insulation between them acts as a plate capacitor, the capacitance of the device would increase as the resistance decrease. So instead the fastest transistors are the ones sized as small as possible.
Another aspect of device sizing is the driving capability of the transistor. The current a device can draw from the power supply is proportional to the resistance in the device, in other words the width should be large enabling a low resistance in the channel.
Ultimately this discussion shows that there is a trade-off between the need for speed and the capability of the output of a device driving other devices.
2.3.2
The CMOS Inverter
The simplest circuit in CMOS design is the inverter, seen in Figure 2.3. The inverter has the function of giving an output opposite to that of the input, i.e. a ’1’ at the input would result in a ’0’ at the output and vice versa.
2.3 Circuit Design 11
x ¯x M1
M2
Figure 2.3: The CMOS inverter.
The ’1’ at the input would make the PMOS device (M1) to be off and the NMOS device (M2) to be on. This would effectively make the output connected to ground (Vss) but not to the supply voltage (Vdd) thus the output node would
have the potential of Vss which is a ’0’.
2.3.3
The Transmission Gate
The switch is a central circuit in many designs. Following the discussion in Section 2.2.2 on how the transistors are biased it becomes obvious that using a simple pass-transistor is not a very robust implementation of the switch. because depending on whether it is a ’0’ or a ’1’ that should be conducted through the switch there would be a voltage drop over the switch.
Instead of only a pass-transistor a very common CMOS implementation of the switch is the transmission gate seen in Figure 2.4. The transmission gate is built upon the idea that the PMOS can charge the output all the way to the input voltage when this is “high” and NMOS can discharge the output to ground when the input is “low”.
in out ctrl
ctrl
Figure 2.4: A transmission gate implemented with one NMOS device and one PMOS device.
2.3.4
The D-Flip-Flop
The D-Flip-Flop (DFF) is a clocked storage element used to synchronize data to a clock signal. The DFF has the property of keeping the output Q (and the complementary output ¯Q) stable to whatever the input D is at a rising clock edge. In this case it is the positively edge clocked DFF that is illustrated in Figure 2.5.
12 Semiconductor Technology DFF Q ¯ Q D R clk in reset out out
Figure 2.5: The DFF as it appears in circuit diagrams.
2.3.5
The Adder
The Full Adder (FA) performs an addition between two single bit binary digits (a and b), it also takes a carry input signal (cin) as input and beside the sum output
(s) it has a carry signal output (cout). The boolean equations for the FA is seen
in Equation 2.2 and the corresponding truth table in Table 2.2.
s = a ⊕ b ⊕ cin (2.2a)
cout= ab + acin+ bcin (2.2b)
Table 2.2: FA Truth Table a b cin s cout Carry Status
0 0 0 0 0 Kill 0 0 1 1 0 Kill 0 1 0 1 0 Propagate 0 1 1 0 1 Propagate 1 0 0 1 0 Propagate 1 0 1 0 1 Propagate 1 1 0 0 1 Generate/Propagate 1 1 1 1 1 Generate/Propagate FA cin FA FA FA c3 a0 b0 s0 a1 b1 s1 a2 b2 s2 a3 b3 s3
Figure 2.6: A 4-bit RCA.
The carry signals make it possible to connect several FA’s in cascade allowing addition of binary numbers of multiple bits. In Figure 2.6 an example structure
2.3 Circuit Design 13
of this type is shown. This kind of adder is called the Ripple Carry Adder (RCA) and is the most straightforward and simple implementation. The RCA is slow because of the fact that the carry signal in each FA has to be computed depending on the input carry. This makes propagation of the carry signal the critical path of an RCA.
In Example 2.1 the worst case carry propagation for a 4-bit number is illus-trated mathematically, the carry signals are indicated with a bar under the digit.
Example 2.1 1 ¯ 1¯ 1¯ 1 1 1 1 + 0 0 0 1 1 ¯ 0 0 0 0
It is often useful to use the intermediate signals kill (K) propagate (P ) and generate (G) in circuit realizations of the FA, see Equation 2.3. These signals are named after how the input carry bit is handled.
G = ab (2.3a)
K = ¯a¯b (2.3b)
P = a ⊕ b (2.3c)
The sum and carry signals can then be written as functions of G and P (or K and P ).
s = P ⊕ cin, (2.4a)
cout= G + P cin (2.4b)
There are a lot of ways to accelerate this carry propagation but this will not be addressed here, the interested reader is referred to Rabaey et al. [5].
Chapter 3
A/D-Conversion
In which the basic concepts of analog to digital conversion are explained and two commonly used architectures are briefly discussed. The emphasis is naturally on the Σ∆-modulator and throughout this chapter it becomes apparent why the deci-mation filter is a fundamental part of the Σ∆-ADC. Last the trade-offs concerning different ADC architectures are explained. This strives to shed some light on why the Σ∆-ADC is under investigation in this thesis.
3.1
The Basics of A/D-Conversion
What an ADC does is to convert a continuous time signal to a discrete time signal that is quantized into a number of well defined and finite values. As illustrated in Figure 3.1, this is generally done by using a comparator that compares the input signal with a known reference signal. The comparator gives the logic output ’1’ or ’0’ depending on whether the input is above or below the reference signal voltage.
Vin
Vref
b
(a) schematic symbol
Vref
b Vin
(b) input and output
Figure 3.1: A schematic symbol of a comparator, seen together with an input signal and the corresponding output signal.
The quantization of a signal introduces noise, this is often measured with the ratio between signal power and noise power. This measure is called Signal to Noise Ratio (SNR), and because it is derived from measured quantities it does not only
16 A/D-Conversion
measure the noise introduced by the quantizer but all possible noise sources. This is often referred to as Signal to Noise and Distortion Ratio (SNDR):
SNDR = 10 · log10 Psignal Pnoise
[dB] (3.1)
3.1.1
Direct A/D-Conversion
Given the idea of a comparator the straightforward realization of an ADC with a resolution of multiple bits is to use several comparators with different reference signals. This is called direct A/D-conversion or Flash A/D-conversion.
1 3· Vref Vin b0 2 3· Vref Vin b1 Vref Vin b2
(a) Flash ADC structure
1 3· Vref 2 3· Vref Vref b0 b1 b2 Vin
(b) input and output
Figure 3.2: (a) shows structure of a 2-bit Flash ADC and (b) illustrates the input and the corresponding output.
To implement a Flash-ADC with a resolution of 2 bits the structure seen in Figure 3.2 is suitable. The three comparators has a 3-bit output which can produce 4 digits since each comparator produces logic ’1’ in succeeding order as the signal voltage level increases: 000, 001, 011, 111 (b2 b1 b0). Since 2 bits can represent 4
digits: 00, 01, 10, 11, the resolution is 2 bits.
The Flash-ADC present a seemingly simple and efficient architecture for ADCs, but it must be noted that the number of comparators needed grows exponentially with the required resolution as ncomp. = 2Wreq. − 1. E.g. a Flash-ADC with
a 3 bit resolution requires 7 comparators and a 12 bit resolution requires 4095 comparators.
3.1 The Basics of A/D-Conversion 17
3.1.2
D/A Conversion
A common implementation of the Digital to Analog Converter (DAC), which is a very frequently used subcircuitry of many ADC’s, is the so called switched capacitor implementation. Shown in Figure 3.3 is an example 4-bit DAC. The
C 2C 4C 8C Vref.
Vout
b0 b1 b2 b3
Figure 3.3: Schematic of a 4-bit switched capacitor DAC.
digital input (b3 b2 b1 b0) controls switches that either connects a capacitor of
varying size to ground or to a reference voltage. Depending on the size of the capacitor, the bit controlling it will have a different significance on the output voltage (VDAC). Consequently the least significant bit is controlling the smallest
capacitor (C) and the most significant bit controls the largest capacitor (8C). More generally the largest capacitor would be 2W −1times larger than the smallest
capacitor, where W is the word length or resolution of the DAC.
Since the output voltage of the switched capacitor DAC is dependent on the difference in size between capacitors the precision, to a very large extent, is subject to process variations. If the DAC is to have a high accuracy the capacitors needs to be very closely matched in size, so that each bit has twice the significance of the previous bit, starting with the Least Significant Bit (LSB) at significance 1.
Another limitation of the possible resolution is the exponential growth of the capacitor size, e.g. a 16-bit DAC would need 16 capacitors where the largest one, representing the Most Significant Bit (MSB) would be 32,768 times larger than the smallest one, representing the LSB.
3.1.3
The SAR-ADC
The SAR-ADC is a widely used type of ADC and is advantageous in applications requiring low power consumption, reasonably low sample rates (A few MSa/s [17]) and moderate to high resolutions (up to 18-bits). The SAR-ADC does a number of calculations on each sample and converge on a binary representation and is thus inherently slow, but can be made very compact and efficient. As seen in Figure 3.4: only one comparator, a register with control circuitry (SAR), a DAC and a sample and hold (S/H) unit is needed.
The conversion is done by by first setting the most significant bit (bn) of the
18 A/D-Conversion S/H SAR DAC b0 b1 bn .. . VDAC Vin Vref clk
EOC Digital Output . . .
Figure 3.4: Block diagram of an n-bit successive approximation A/D converter.
the DAC (VDAC) settle at half of the reference voltage (Vref/2). Depending on
whether the input (Vin) signal voltage is above or below Vref/2, the output of the
comparator either keeps bn at ’1’ or resets it to ’0’. Now the next conversion step
is taken and the SAR logic sets bn−1 to ’1’ and goes through the same procedure again. When all bits in the SAR has been set and then kept at ’1’ or reset to ’0’, the conversion is complete and the SAR commits the binary output by signaling End Of Conversion (EOC).
For a 4-bit SAR ADC the conversion of one sample held by the S/H-unit can be exemplified as shown below. Figure 3.5 illustrates how the VDACchanges with
each step, implicitly this also show the digital output.
Step 0
i) The SAR MSB, b3, is set to ’1’ while all other bits are reset to ’0’,
⇒ VDAC= Vref./2
ii) The comparator gives the output ’0’ because Vin< VDAC⇒ b3= ’0’
Step 1
i) The next bit, b2, is set to ’1’ ⇒ VDAC= Vref./4
ii) The comparator gives the output ’1’ because Vin> VDAC⇒ b2= ’1’
Step 2
i) The next bit, b1, is set to ’1’ ⇒ VDAC= Vref./4 + Vref./8
ii) The comparator gives the output ’0’ because Vin< VDAC⇒ b1= ’0’
Step 3
i) The next bit, b0, is set to ’1’ ⇒ VDAC= Vref./4 + Vref./16
3.2 The Σ∆-ADC 19
V
Vin
Vref
VDAC
Figure 3.5: Illustration of how the digital output of a SAR-ADC converges towards the input.
3.2
The Σ∆-ADC
The basic concept of the Σ∆-ADC is to use oversampling and a feedback loop that pushes the quantization noise out of the signal frequency band (fb) into higher
frequencies. This makes it possible to low pass filter the output which removes noise from the signal, thus increasing the resolution of the ADC. The Σ∆-ADC consequently consist of two basic blocks; a modulator that quantizes the signal and a digital filter that performs the filtering.
Σ∆-modulator Decimation Filter Analog input: f ≤ fb Digital output: Wq@ fs Digital output: Wreq.@ 2 · fb
Figure 3.6: High level system sketch of a Σ∆-ADC.
Because the modulator oversamples (fs≥ 2·fb) the signal at a high rate and as
mentioned pushes the quantization noise up in frequency it is possible to increase the resolution (Wreq.> Wq) of the digital signal and at the same time decrease the
data rate. This calls for a so called decimation filter which has the basic property of downsampling and filtering a signal. Since this thesis is aimed at the design of decimation filters the next chapter is dedicated to this and the next sections only address the Σ∆-modulator.
3.2.1
The Modulator
An oversampling ADC can perform better than one sampling at the Nyquist rate (see Equation 3.5). This is quite intuitive since one can imagine that doing a lot of measurements on approximately the same point in time should enable the output to be digitally processed and averaged to values between the levels available to the quantizer. The Σ∆-modulator however does more than just oversampling, it pushes the quantization noise into higher frequencies due to the feedback loop seen in Figure 3.7.
20 A/D-Conversion ADC DAC H(t) Σ x(t) y[n] − +
Figure 3.7: Block diagram of a 1:st order Σ∆-modulator with a n-bit ADC and DAC.
x(t) y[n]
Figure 3.8: A sine wave input and the corresponding output from a Σ∆-modulator with a 1-bit quantizer.
An illustration of how a first order Σ∆-modulator with a 1-bit quantizer per-forms on a sine input can be seen in Figure 3.8. From this it can intuitively be appreciated that if the Σ∆-output (y[n]) would be lowpass filtered it would be smoothed out and resemble the sine input more. These observations are not made plausible in a sentence as in the case of oversampling, it requires some system analysis and mathematical reasoning, this is done in the following two sections.
3.2.2
Linear Model
If one can assume that the quantization noise is linear and can be described by adding a noise signal (eq[z]), the model of a first order modulator can be made as
seen in Figure 3.9. That this and following assumptions are valid is discussed in Norsworthy et al. [23].
This linearizion gives us:
y[z]= eq[z]+ H[z](x[z]− y[z]) ⇒ y[z]= eq[z] 1
1 + H[z]+ x[z]
H[z]
3.2 The Σ∆-ADC 21 H[z] Σ Σ x[z] eq[z] y[z] − +
Figure 3.9: Linear model of a 1:st order Σ∆-modulator shown in the z-domain.
Assuming that the input signal (x[z]) and the quantization noise (eq[z]) is
uncor-related the noise and signal can be treated separately. From this a signal transfer function (STF = y[z]/x[z]) and a noise transfer function (NTF = y[z]/eq[z]) can
be derived:
STF = H[z]
1 + H[z] (3.2a)
NTF = 1
1 + H[z] (3.2b)
To achieve the wanted characteristics of the modulator the internal transfer func-tion H[z]must be something that makes the STF a low pass filter and the NTF a high pass filter. This would namely push the quantization error up in frequency but keep the signal spectrum unchanged, assuming that the signal is in the low frequencies, which is the whole idea of the oversampling Σ∆-ADC.
The literature [12], [23] states that H[z] should act as an integration which have the transfer function: z−1/(1 − z−1). For the STF and the NTF this would
yield:
STF = z−1 (3.3a)
NTF = 1 − z−1 (3.3b)
Since it is the frequency response that is of interest, z can be substituted with ej2πf /fs which results in:
STF = e−j2πf /fs (3.4a)
NTF = 1 − e−j2πf /fs (3.4b)
From Equation 3.4a and 3.4b it can be seen that if f → ∞ then STF → 0 and NTF → 1. The equations also show that if f → 0 then STF → 1 and NTF → 0. Hence: the STF and NTF has the characteristics of a low pass filter and a high pass filter respectively. This concludes that the Σ∆-modulator indeed pushes the quantization noise up in frequency out of the signal frequency band enabling a low pass filter to increase the resolution.
3.2.3
Noise Analysis
When any ADC is subject to noise analysis at an architectural level it is often done by disregarding thermal noise and similar distortion sources and concentrate
22 A/D-Conversion
on the effect of the quantization. This is done because choosing the number of quantization steps has a major impact on complexity and the system as a whole. It should however be stressed that the Signal to Quantization Noise Ratio (SQNR) is a theoretical maximum value assuming that all components are linear and ideal and that the quantization noise can be modeled using the linear model. For basic quantization (direct A/D-conversion) this SQNR can be derived as [27, pp. 12]:
SQNR = Wq· 6.02 + 1.76 [dB] (3.5a)
and for an oversampling ADC [27, pp. 15]:
SQNR = Wq· 6.02 − 1.25 + 10 · log10 fs 2 · fb [dB] (3.5b) where Wq is the resolution (word length) of the quantizer, fs is the sampling
frequency and fb is the bandwidth of the input signal. The quotient fs/(2 · fb) is
often referred to as Over Sampling Ratio (OSR). For the first order Σ∆-modulator [12] this noise analysis ends up in the similar equation:
SQNR = Wq· 6.02 + 1.76 − 5.17 + 30 · log10(OSR) [dB] (3.6a)
It is possible to suppress the quantization noise in the signal band even more using
Σ H[z] Σ H[z] Σ x(t) y[z] − + − + eq[z]
Figure 3.10: Linear model of a 2:nd order Σ∆-modulator.
higher order Σ∆-modulators. These modulators uses multiple feedback loops and integrators, in Figure 3.10 an example model of a second order Σ∆-modulator can be viewed. The same analysis as before can be made in this case and the end result is [12]:
SQNR = Wq· 6.02 + 1.76 − 12.9 + 50 · log10(OSR) [dB] (3.6b)
A common measure on how well an ADC performs is to compare it with the ideal SNR of direct A/D conversion. This measure is known as the Effective Number Of Bits (ENOB) and from Equation 3.5a it can be derived by substituting Wq with ENOB and SQNR with SNDR:
ENOB = (SNDR −1.76)
6.02 [no. bits] (3.7) In other words the ENOB is a measure of the effective resolution of an ADC. E.g. an ADC might have a large output wordlength but it nonetheless has a low actual resolution because of a poor SNDR, and thus has a low ENOB.
3.3 Trade-offs 23
3.3
Trade-offs
In a mixed signal circuit (e.g. a pacemaker) where analog signals (heart beats) are to be measured and where the circuit should react (correct the heart rhythm) to how these signals are constituted it is impossible to avoid devices in analog operation. To implement a lot of functionality at a low cost with the given resource (chip area, battery life) analog to digital converters (ADCs) are needed that allow digital signal processing. And the key to making a good ADC is to have an architecture that has the right trade-off between analog and digital components. The different techniques of A/D conversion all have their stronger and weaker sides, which makes them suitable for different applications.
3.3.1
Flash-ADC
With its exponential increase of complexity and the issues of process variations discussed in Chapter 2 it becomes apparent that the Flash-ADC is not a viable option for neither low power nor high resolution ADCs. However, Because of the high speed, it is a very important component within more advanced ADC-architectures, where the internal conversion speed than that of the output data rate.
3.3.2
SAR-ADC
The drawback of the SAR-ADC is that it relies on that capacitors are exactly matched relative to one another. Because of this, requirement of additional cal-ibration circuitry when resolutions higher than 12 bits are needed [17]. Another limitation is the exponential increase in size of capacitors in the DAC, these can not be infinitely large.
3.3.3
Σ∆-ADC
The Σ∆-ADC has the ability to use very few analog components making it tolerant to process variations. This ability comes from the fact that it is possible to use only one comparator and for the first order only one integrator (active or passive) is needed. The lack of analog components is compensated with the digital decimation filter. There are apparently three parameters that specify the architecture of the Σ∆-modulator and these are listed below:
• OSR: Increased OSR gives larger dynamic power consumption.
• Quantizer: Multiple bits in the quantizer means more analog components which gives linearity problems (DAC and ADC), due to process variations. • Order: Increased order of the modulator increases the power consumption
due to more operational amplifiers or linearity problems in the case of using passive integrators.
24 A/D-Conversion
Table 3.1: Maximum ENOB with Σ∆1
ENOB
OSR 1-bit Q 2-bit Q 3-bit Q 16 6.14 7.14 8.14 32 7.64 8.64 9.64 64 9.14 10.14 11.14 128 10.64 11.64 12.64 256 12.14 13.14 14.14 512 13.64 14.64 15.64 1024 15.14 16.14 17.14
In Table 3.1 a breakdown of maximum theoretical ENOB for 1st order Σ∆-modulators with 1-bit to 3-bit quantizers can be seen.
The limitations of this thesis restricts the choice to the first order modulator with a 1-bit quantizer. From Table 3.1 it can be seen that an OSR of 256 should be required to fulfill the demand on resolution (12-bits).
3.4
Summary
To summarize this chapter one can conclude that the subject of A/D-conversion is very complex. There is no set of rules that states what architecture to use in a certain situation, or even what specification to use if an architecture is chosen. Table 3.2 tries to show how the different discussed ADC’s are commonly used rather than showing a solid bound for the performance. As stated before one
Table 3.2: Breakdown of ADC Performance
Speed Resolution Power Consumption Σ∆-ADC High Very high Moderate
SAR-ADC Low High/Moderate Low/Very low Flash-ADC Very high Low High
goal of this thesis is to investigate if the Σ∆-modulator could use the ability of high resolution and high speed and trade this off for a low power consumption, this is why the Σ∆-ADC is of great interest. The next chapter will introduce the decimation filter and address how the specification of the Σ∆-modulator translates into specifications on the decimation filter and the associated trade-offs.
Chapter 4
Digital Decimation
In which the basic concept of the decimation filter is explained and different design and implementational issues are discussed. Last follows a discussion on trade-offs for the specific application of this thesis.
4.1
The Basic Concepts
The basic concept of a decimation filter is to reduce the data rate at which a stream of information is available by throwing away samples, as depicted in Figure 4.1. When doing this it is important to low pass filter the signal to prevent images of the signal to be aliased into the signal frequency band [28], this is why H(z) is required. As low pass filtering is exactly what is required in the case of the oversampled Σ∆-modulator a decimation filter is a natural part of the Σ∆-ADC.
H(z) ↓ M
fs fs/M
Figure 4.1: Conceptual view of a decimation filter.
Since the quantization noise has been pushed up in frequency, the high fre-quency and short word length (e.g. 1-bit) from the modulator can be decimated and at the same time the resolution can be increased. So the basic concept of the decimation filter in the case of the Σ∆-ADC is to trade off data rate for a much longer word length, i.e. extracting the intrinsic resolution of the Σ∆-modulator.
4.1.1
Multistage Decimation
When high OSR’s are used in the Σ∆-modulator the requirement on the filter before the decimation becomes very high. To relax these requirements the
26 Digital Decimation
mation can be made in several stages, this would relax the requirements on each sub-filter and reduce the overall complexity of the decimation filter.
H0(z) ↓ M0 H1(z) ↓ M1 . . . Hn(z) ↓ Mn
Figure 4.2: Block diagram n-stage decimation.
Norsworthy et al. [23, pp. 415] states that using a filter with more than two stages often result in implications that leads to the conclusion that two stages is optimal. Further a decimation ratio of 2 at the last stage is most advantageous, this is investigated in Chapter 5.
A common approach to this multistage decimation uses a simpler filter to perform a large first downsampling which is followed by a more advanced and sharp filter to compensate for the poor first stage. The idea is that the requirements on the last filter to a very large degree is relaxed because the filter performs a low ratio of decimation. A low decimation ratio before the final output implies that a relatively short frequency band needs to handled which means that fewer coefficients are required to describe a sharp filter. Another advantage is that the advanced last filter stage operates at a low clock frequency which can reduce power consumption.
For the first stage a so called sinc-filter is often used, which can be implemented using only adders and delay elements and no costly multipliers. This filter is a Cas-cade of Integrator and Comb (CIC) sections and was first introduced by Hogenauer in 1981 [10] and has become very popular. The CIC has many advantages and is devoted its own section in this chapter.
One recent publication [14] has shown that there is a lot to gain from co-optimizing the filter stages instead of individually designing each filter stage. The gain would be that each sub-filter requirements is relaxed but the sub-filters would compensate for each others lack in performance. E.g. would a pass band droop in one filter automatically be compensated by this co-optimization.
4.1.2
Polyphase Decomposition
To efficiently implement a filter it has been shown that the so called polyphase decomposition is efficient and reduce power consumption [15]. A conceptual view of the polyphase decomposition can be viewed in Figure 4.3
The idea behind the polyphase decomposition is that by doing the downsam-pling before the filtering the multipliers would operate at a lower speed and con-sume less power. Another reason is that only the samples required at the output is calculated.
Aboushady et al. [15] actually showed that the polyphase decomposition could be an efficient implementation of the sincN-filter. This is paradoxically because the polyphase decomposition require multiplications and the original idea
4.1 The Basic Concepts 27 ↓ M H0(z) Σ z−1 ↓ M H1(z) Σ z−1 ↓ M HN(z) .. . ... out in
Figure 4.3: The principle of polyphase decomposition of a decimation filter with decimation ratio M.
of Hogenauer was that it would be an economical filter in CIC-implementation, using no multiplier. The idea behind the polyphase decomposition of sincN-filters in many publications is that the transfer functions can be elaborated and the multiplications can be implemented in very specialized ways, this would however become very impractical for large decimation ratios.
The polyphase implementation could however be efficient at the first stage of the decimation where the input has a 1-bit word length. In this special case the input is either ’1’ or ’0’ and a multiplication only mean that a coefficient is added to a sum or not. And for the Σ∆-modulator the output often is only 1-bit.
Another angle of attack is to use more advanced multiply and accumulate architectures that could do all the multiplications and additions but be clocked at a higher speed. With todays deep sub-micron manufacturing processes the speed would most certainly be of no problem, at least not low for frequency applications, but high leakage currents are. Therefore a MAC-architecture clocked at a high speed but requiring less hardware could be advantageous.
2 8 D ig ita l D e c im a ti o n
4.2
Filter Design
When designing the decimation filter there are a lot of considerations to make, a good overview of these can be seen in Table 4.1, which is a slightly modified version of the table at page 409 from Norsworthy et al. [23].
Table 4.1: Design considerations
Algorithm Efficiency Architectural Efficiency Layout Efficiency Technology (Behavioral) (Structural) (Physical) (Physical)
Design choices and options • FIR vs. IIR • Single stage vs. multistage • Direct form vs. polyphase vs. transpose vs. parallel
• Coefficient word length
• Hardware vs. software
• Distributed vs. centralized arithmetic
• Bit parallel vs bit serial vs. digit serial
• Hard wired vs. reconfigurable vs. programmable
• Random vs. structured (e.g., PLA vs. ROM)
• Programmable logic • Gate array • Standard cell • Full custom • CMOS • BiCMOS • Bipolar • GaAs Associated trade-offs • Accuracy vs. speed vs. performance • Area vs. performance • Testability • Design time • Performance vs. area vs. power dissipation • Testability • Flexibility • Design Time • Design time and cost vs performance and area • Speed vs. power vs. complexity vs. cost
4.3 The Cascaded Integrator Comb Filter 29
4.2.1
Design Choices
Most often the design decisions that has to be made do not follow the top down approach as described from left to right in Table 4.1: First choosing a suitable algorithm which is the one that matches the application in mind, and then choos-ing an optimal architecture for this algorithm, and after this the best technique for physical implementation naturally follows and the perfect technology becomes apparent.
More often, as is the case in this thesis, there are restrictions inherent from the application and the availability of technology (e.g. manufacturing processes). In this case the power consumption is crucial and the filter must be able to be implemented and integrated on-chip with other components. This effectively limits the physical aspects to CMOS and this in turn limits the implementation to full custom or standard cell in contrast to gate array or programmable logic. With the focus on extremely low power consumption the full custom becomes an attractive choice with its ability to size the transistors in total freedom and use aggressive low power techniques like sub-threshold operation.
When implementational issues has to be considered the degrees of freedom on the choices of algorithm and architecture becomes quite narrow. And these issues must be kept in mind when designing a filter using some high level design tool.
4.2.2
Design Flow
When designing a filter the requirements are set by specifications for the wanted frequency and phase characteristics. The traditional input for the design of a decimation filter for a Σ∆-modulator is the modulator itself. The modulator has been specified and designed to be able to produce a certain resolution, in other terms it has a certain SNR. This means that the filter should match this SNR and manage to extract the maximum resolution that possibly can be extracted from the modulator.
This thesis approaches the design of a decimation filter with an alternative perspective. Instead of having a fixed modulator the specifications is kept flexible and different setups of OSR and order are used to see how this effect the filter.
4.3
The Cascaded Integrator Comb Filter
The Cascaded Integrator and Comb (CIC) filter was introduced as an economical class of filters for decimating or interpolating a signal by Hogenauer in 1981 [10]. This filter algorithm was aimed at decimation and interpolation in general and not at all at Σ∆-ADC‘s. With the Σ∆-ADC’s using high OSR’s the CIC-filter became a very popular filter, requiring no multipliers.
30 Digital Decimation Σ z−1 . . . fs Σ z−1 fs/M z−M Σ . . . z−M Σ fs/M − + +−
Figure 4.4: An N:th order CIC.
The CIC structure depicted in Figure 4.4 is conceptually the same as first con-ceived by Hogenauer in his famous article. The transfer function for one integrator section (denoted I) and one comb section (denoted C) can be described as:
HI[z]= 1
1 − z−1 (4.1a)
HC[z]= 1 − z−M (4.1b)
When N of these sections are cascaded as seen in Figure 4.4 the transfer function for the system as a whole becomes:
H[z]= H[z]NI · H[z]NC = (1 − z−M) N (1 − z−1)N = M −1 X k=0 z−k N (4.2)
Equation 4.2 shows that the N:th order CIC-filter (from now on denoted CICN) is in fact a low pass filter. One more interesting thing is that if the Σ∆-modulator NTF is recalled: NTF = 1 − z−1 (Equation 3.3b), it can be seen that
the CICN transfer function denominator exactly matches the NTF. This further strengthens the CICN as a candidate for decimating the Σ∆-modulator output, since the NTF would be canceled out by the denominator.
The limitation on the CIC that prevents it from being made infinitely large in terms of order and capability to managing high OSR’s is the integrators. The integrators are simple accumulators which add the incoming value to the previous one and thus accumulating the input. The issue is that the registers will overflow, although this can be handled with two’s complement representation and using modulo arithmetic a certain word length to be able to accommodate the comb sections.
Hogenauer found the register growth in the CIC filters to be [10]:
Bmax= N · log2(OSR) + Win (4.3)
Where Bmaxis the MSB for all sections, both the integrator sections and the comb
sections. This means that the minimum register word length of each integrator and comb is: Wreg.= Bmax. Even though it is possible to truncate for each section
the first accumulator require that Wreg.= Bmax. This means that the CIC cannot
4.4 Trade-offs 31
4.4
Trade-offs
Basically there is only one trade-off in the design of a decimation filter for a Σ∆-modulator: filtering capability for complexity. The performance of the filter can be measured in the resolution it manages to extract from the high frequency output of the modulator. And the performance is related to the complexity which directly relates to the power consumption.
Within this complexity versus performance trade-off there are three perfor-mance characteristics that defines the complexity:
• OSR: A high OSR, which generally indicates a high sampling frequency, will require larger filter orders. For the CIC-filter the OSR directly relates to the register word length and the sampling frequency to how high the clock frequency is.
• ENOB: The required effective resolution (SNR) of the ADC as a whole relates to the required stopband attenuation, and the allowed width the transition band.
• Distortion: The tolerable distortion of the converted signal relates to the passband ripple of the filter.
The next part of the thesis describes the implementation and evaluation of a set of CIC-filters, beginning with a chapter that gives a background to why the CIC was chosen.
Part II
Chapter 5
Design
In which the algorithm and architecture evaluation done in Matlab is described, this gives the background to why the CIC was chosen for implementation. The Matlab programming code can be found in Appendix A.
5.1
Filter Requirements
The requirements on the decimation filter is dependent on the required resolution of the Σ∆-ADC as a whole. But the filter design is also dependent on the character-istics of the signal and what can be tolerated in terms of distortion. As mentioned in the introduction this is not within the scope of this thesis and therefore pure sinusoidal signals are assumed. For many applications a linear phase response is required, this effectively limits the possible filters to FIR-filters.
A summary of the assumed requirements and what this means for the OSR of the modulator can be seen in Table 5.1.
Table 5.1: Σ∆-modulator specifications fb [Hz] ENOB Order Wq ⇒ OSR
500 12 1st 1 256
The table can seem somewhat contradictive. The requirement on resolution, given in effective number of bits (ENOB) is set to be 12, which given Equation 3.6a and 3.7, implies an oversampling ratio (OSR) of approximately 240, given a one bit quantizer (Wq) and a first order modulator. But it is more convenient with
an OSR that is an even power of two, hence 256 is appropriate.
As discussed in the previous chapter the decimation can be made in multiple stages. This will decrease the overall complexity of the filter, the question is how many stages and what filter is suitable for each stage. Matlab provides a powerful way to design and evaluate many filters and compare them, this section will provide an in-depth analysis of the decimation needed. The specifications for the
36 Design
modulator given in Table 5.1 translates into requirements on the decimation filter given in Table 5.2.
Table 5.2: Decimation filter specifications fb [Hz] fout[Hz] OSR Win Wreq. ⇒ As[dB]
500 1000 256 1 12 74
From Chapter 3 we know that the relation between ENOB and SNR can be described by Equation 3.7. Since the required resolution of the Σ∆-ADC as a whole is 12 bits this translates into the stopband attenuation (As) seen in Table
5.2.
5.2
Filter Evaluation
To perform an evaluation of any filter it is customary to see if the frequency re-sponse fulfills certain requirements, this can be done by deriving a specification from the NTF of the Σ∆-modulator at hand. Another way to evaluate the per-formance is to calculate how the filter in question can filter a set of data and compare this to how an ideal filter would perform. Now it becomes obvious that some kind of Σ∆-modulator is needed. To provide test data a HDL Σ∆-modulator was implemented, the details of this is discussed in the next chapter.
5.2.1
Specification
To derive a specification for the filter an NTF is needed, this can easily be done in Matlab. As derived in Chapter 3 the NTF of a first order Σ∆-modulator can be modeled as a simple zero at z = 1 and a pole at z = 0. This NTF can be seen in Figure 5.1 together with how it matches the frequency spectrum of an output signal from the mentioned Σ∆-modulator. By describing the signal spectral density (Rx)
and the noise spectral density (Ry) from the NTF a filter specification can be
derived [14]: Rx(ωT ) = Q2 12|NTF(ωT )| 2 ; Q = 2−Wq+1 (5.1) Ry(ωT ) = |H(ωT )|2Rx(ωT ) (5.2)
If the noise power spectral density is assumed to be lower that a constant σ, this leads to the noise power Pnoise being:
Pnoise= 1 π π Z 0 σdωT ⇒ Pnoise≥ σ ≥ Ry(ωT ) (5.3)
Now Equation 5.2 and 5.3 can be combined to: Pnoise≥ Rx(ωT )|H(ωT )|2⇒ |H(ωT )|=
s Pnoise
