Modelling and Analysis of Substrate Noise in Delta Sigma ADCs

SECOND CYCLE, 60 CREDITS STOCKHOLM, SWEDEN 2017

Modelling and Analysis of

Substrate Noise in Delta Sigma ADCs

ABU DARDA

KTH ROYAL INSTITUTE OF TECHNOLOGY

SCHOOL OF INFORMATION AND COMMUNICATION TECHNOLOGY

Modelling and Analysis of Substrate Noise in Delta Sigma ADCs

Author:

Abu D

Supervisor:

Nikola I

Examiner:

Prof. Dr. Ana R

This thesis work has been performed in fulfillment of the requirements for the Masters Programme in Embedded Systems

at the

School of Information and Communication Technology KTH Royal Institute of Technology

November 11, 2017

Stockholm

TRITA-ICT-EX-2017:193

Abstract

Modelling and Analysis of Substrate Noise in Delta Sigma ADCs

by Abu D

The rapid development in the semiconductors industry has enabled the placement of multiple chips on a single die. This has helped boost the functionality of modern- day application specific integrated circuits (ASICs). Thus, digital circuits are being increasingly placed along-side analog and RF circuits in what are known as mixed signal circuits. As a result, the noise couplings through the substrate now have an increased role in mixed-signal ASIC design. Therefore, there is a need to study the effects of substrate noise and include them in the traditional design methodology.

∆Σ analog-to-digital converters (ADCs) are a perfect example of digital integration in traditionally analog circuits. ADCs, used to interface digital circuits to an analog world, are indispensable in mixed-signal systems and therefore set an interesting case study. A ∆Σ ADC is used in this thesis to study the effects of substrate noise. A background study is presented in the thesis to better understand ∆Σ modulators and substrate couplings. An intensive theoretical background on generation, propagation and reception of substrate noise is presented in light of existing researches.

System and behavioural level models are proposed to include the effects of substrate noise in the design stages. A maximum decay of 10dB is seen due to injection of substrate noise system level simulations while a decay of 12dB is seen in behavioural simulations. A solution is proposed using controlled clock tree delays to overcome the effects of substrate noise. The solution is verified on both the system and behavioural levels. The noise models used to drive the studies can further be used in mixed-signal systems to design custom solutions.

Keywords: Analog Mixed Signal Design, Delta Sigma ADC, Substrate Noise,

,System Level Modelling, Behavioural Level Modelling

iii

Sammanfattning

Modelling and Analysis of Substrate Noise in Delta Sigma ADCs

by Abu D

Den snabba utvecklingen inom halvledarindustrin har möjliggjort placering av flera marker på en enda dö. Detta har hjälpt till att öka funktionaliteten hos moderna applikationsspecifika integrerade kretsar. Sålunda placeras digitala kretsar i allt högre grad parallella och RF-kretsar i de så kallade blandade signalkretsarna.

Som ett resultat har bullerkopplingarna genom substratet nu en ökad roll i ASIC- design med blandad signal. Därför finns det behov av att studera effekterna av substratbuller och inkludera dem i den traditionella designmetoden.

∆Σ analog-till-digital omvandlare är ett perfekt exempel på digital integration i traditionellt analoga kretsar. ADC, som används för att gränssnitta digitala kretsar till en analog värld, är oumbärliga i blandningssignalsystem och är därför en intressant fallstudie. A ∆Σ arkitektur används i denna avhandling för att studera effekterna av substratstörning. En bakgrundsstudie presenteras i avhandlingen för att bättre förstå ∆Σ modulatorer och substratkopplingar. En intensiv teoretisk bakgrund på generering, förökning och mottagande av substratbuller presenteras i ljuset av befintliga undersökningar.

System- och beteendemodellmodeller föreslås inkludera effekterna av substratbuller i konstruktionsstadiet. Ett maximalt förfall på 10dB ses på grund av injektion av substratbuller på systemnivå medan ett förfall av 12dB ses i beteende simuleringar.

En lösning föreslås med hjälp av kontrollerade klockträdfördröjningar för att övervinna effekterna av substratbuller. Lösningen är verifierad på både system och beteendenivåer.

De brusmodeller som används för att driva studierna kan vidare användas i blandningssignalsystem för att designa anpassade lösningar.

Nyckelord: Analog blandad signaldesign, Delta Sigma ADC, Substrate Noise,

Systemnivåmodellering, Behavioralnivåmodellering

Acknowledgements

First of all, I would like to thank my examiner Dr. Ana Rusu for giving me an opportunity to work on such an interesting and challenging project. As a newbie to the field, gaining experience under a talented research group is all one can hope for and you gave me just that. I highly appreciate the feedback I received throughout the thesis-work and am grateful for the patience you have shown.

Next I would like to extend a note of thanks to my supervisor Nikola Ivanisevic.

Without your constant guidance and supervision, it would have been a very difficult path for me. Thanks for making it easier. I would like to thank you once again for answering all my questions throughout and keeping up with my constant bugging!

I would like to thank the entire Integrated Circuits and Systems group for their help not only during the thesis but also for the courses I took with them.

A special thanks goes to my friends, Aditya Gahlaut, Prashant Sharma and Rohit Prasad, for giving me company during our stake-outs at the department. Also, I would like to thank Hassan Mahmood , Abhineet Singh Tomar for their help during these last few months.

And last but not the least, I would like to thank my family for their unconditional

love and support during my masters degree. A special token of appreciation for my

dad who pushed me to follow my dream and go for this career path.

v

Contents

Abstract ii

Sammanfattning iii

Acknowledgements iv

List of Figures vii

List of Tables viii

List of Acronyms ix

List of Symbols x

1 Introduction 1

1.1 Background . . . . 1

1.2 Research Problem . . . . 2

1.3 Objectives . . . . 2

1.4 Thesis Overview . . . . 2

2 Background Study 4

2.1 Basics of A/D Conversion: The Ideal ADC . . . . 4

2.1.1 Sampling . . . . 5

2.1.2 Quantization . . . . 5

2.2 ∆Σ modulation based Converters . . . . 6

2.2.1 Oversampling . . . . 6

2.2.2 Noise Shaping . . . . 7

2.2.3 Basic Architecture of a ∆Σ ADC . . . . 7

2.2.4 A Detailed look into ∆Σ Modulation . . . . 8

2.2.5 Design Issues . . . 10

2.3 Substrate Noise . . . 12

2.3.1 Effects of Substrate Noise on Mixed Signal ICs . . . 12

2.3.2 Substrate Noise Injection in a Mixed Signal IC . . . 13

2.3.3 Reception of Substrate Noise in a Mixed Signal IC . . . 14

2.3.4 Effects of Substrate Noise on a ∆Σ ADC . . . 15

2.3.5 Existing solutions to the substrate coupling problem . . . 15

3 System Level Modeling 18

3.1 Substrate Noise Modeling . . . 18

3.1.1 Design Process . . . 20

3.1.2 Noise Characterization . . . 27

3.2 System Level Study Results . . . 30

4 Behavioural Level Modelling 33

4.1 Substrate Noise Modelling . . . 33 4.2 Behavioural Level Study Results . . . 34

5 Conclusions 37

5.1 Summary . . . 37 5.2 Future Work . . . 38

A Appendix 39

A.1 Schematic of the OTA . . . 40

A.2 VerilogA code for Substrate noise generation . . . 41

A.3 VerilogA code for OTA with substrate sensitivity . . . 41

vii

List of Figures

2.1 Ideal ADC Operation . . . . 4

2.2 Principle of noise shaping . . . . 7

2.3 Delta Sigma ADC Operation . . . . 8

2.4 Basic scheme of a ∆Σ modulator . . . . 9

2.5 Simplified representation of IC parasitics . . . 13

2.6 Illustration of separate in-chip power lines . . . 16

3.1 Equivalent circuit for Substrate Coupling . . . 18

3.2 Substrate Noise waveform as per the parameters in [1] . . . 20

3.3 CT Implementation of Substrate Noise Injection . . . 21

3.4 Substrate Noise waveforms for different clock periods. . . 21

3.5 Parasitics report from Cadence Virtuoso . . . 22

3.6 Test-bench for PSRR estimation (Schematic for OTA is shown in Appendix A.1) . . . 23

3.7 Simulation set-up for the test-bench . . . 23

3.8 Transient Simulation result . . . 24

3.9 Variation in the differential output due to substrate noise . . . 24

3.10 Magnitude and phase response of the PSRR reported by circuit simulation in Virtuoso . . . 25

3.11 Magnitude and Phase response of DT function from eq.(3.9) . . . 26

3.12 System level model of substrate coupling noise . . . 26

3.13 Inclusion of substrate noise in the integrator model . . . 26

3.14 Substrate Noise Characteristics . . . 27

3.15 Noise characteristics for a leading digital clock . . . 28

3.16 Noise characteristics for a lagging digital clock . . . 29

3.17 Noise PSD of a single- bit second-order ∆Σ modulator at an OSR of 128 30 3.18 SNDR variation with the delay in the analog and digital clocks of the single-bit second-order modulator . . . 31

3.19 Noise PSD of the second-order single bit modulator for a delay of 30ns 31 3.20 SNDR variation with the delay in the analog and digital clocks of the 4-bit second-order modulator . . . 32

4.1 Behavioral model of Substrate noise coupling . . . 33

4.2 Transient simulation of the behavioral substrate noise block . . . 34

4.3 Transient simulation of the behavioural substrate noise block . . . 35

4.4 System performance parameters of the modulator . . . 36

A.1 Amplifier circuit used to implement integrators in the given ADC model 40

List of Tables

3.1 Loop filter coefficients . . . 30

3.2 Second-order modulator parameters . . . 30

4.1 Loop filter coefficients in the mixed-signal simulations . . . 34

4.2 Second-order modulator parameters . . . 35

4.3 Effect of delay between aggressor and sampling clock . . . 36

ix

List of Acronyms

∆Σ

ADC Analog-to-Digital Converter AMS Analog Mixed Signal

ASIC Application Specific Integrated Circuits CIFB Cascade-of- Integrator -FeedBack CT Continuous-Time

DAC Digital-to-Analog Converter DR Dynamic Range

DT Discrete-Time

ENOB Effective Number Of Bits FOM Figure Of Merit

IC Integrated Circuits LSI Large Scale Integration OSR OvertextbfSampling Ratio

OTA Operational Transconductance Amplifier PDF Probability Distribution Function

PSRR Power Suplly Rejection Ratio RF Radio Frequency

RSB Reduced Supply Bounce

SINAD Signal to Noise and Distortion Ratio SNDR Signal+Noise Distortion Ratio SoC System On Chip

VLSI Very Large Scale Integration

List of Symbols

 Quantization Noise N Number of Bits

P Power

DR Dynamic Range

EN OB Effective Number of bits OSR Oversampling Ratio N Number of bits f

Sampling frequency T

Sampling Period f

Bandwidth Y

Full-scale Value

ST F Signal Transfer Function N T F Noise Transfer Function L Order of modulator f

Corner frequency ω

Resonance Frequency β Frequency of oscillations

χ Damping Constant

G Gain

∆

Jitter

1

Chapter 1

Introduction

The idea of having multiple electronic systems on the same substrate was first conceived in 1950s. As Gordon Moore predicted in the late 60s, the number of transistors in a chip has doubled every one and a half year [2]. This was later referred to as the Moore Law and the developments in the semiconductor industry have since then been in compliance with the prediction. Thus, integrated circuits (ICs) have functionally replaced electronic systems that occupied multiple printed circuit boards (PCBs) with some ICs featuring several million gates. The miniaturization trend has led the technology from large scale integration (LSI) to very large scale integration (VLSI). The continued scaling has made the placement of various functional circuits together possible, thus giving rise to the system on chip (SoC) design methodology. High speed digital circuits are being integrated together with high performance analog circuits in a SoC to boost the overall system performance [3]. This has led to many design issues arising that were insignificant only a decade ago. Such trends demand that the design methodology be accompanied by an in- depth understanding of these issues. This thesis attempts to do so by studying the issue of substrate coupling between the analog and digital blocks of a delta sigma (∆Σ) analog to digital converter (ADC).

1.1 Background

Most functions on a modern SoC are implemented with digital circuitry but analog circuits are still crucial for interfacing with the real world signals. Analog circuitry is also integrated on the same die as the digital thus giving rise to the appropriately named analog mixed signal (AMS) systems or simply mixed signal systems. The reduction of cost, size and power dissipation has motivated the development of highly complex mixed signal systems. A typical mixed signal system consists of both noise sensitive analog blocks and noise injecting digital blocks. This leads to a very unique situation as noise coupling occurs between the aggressor (digital circuits) and the victim (analog circuits) within the system through the shared silicon substrate [4]. This phenomenon is termed as substrate coupling.

The coupling is generally weak but can still hamper the performance of low-noise circuits [5].

In mixed signal systems, the fast switching transients at the digital end propagate

to the analog circuits through the substrate coupling, thus limiting the achievable

analog precision. As the demands for high speed digital circuits and analog

precision increase for the next generation SoCs, the substrate noise will pose a

serious concern in the design methodology [6]. Previous researches in the topic

have been able to provide equivalent substrate impedance models using meshes and

green functions [7–9], experimental circuits for substrate noise generation [1,10,

time domain analysis of switching noise [12] and even experimental measurements

and analyses of substrate noise on ICs [13,

techniques have been proposed and studied in the literature, refer Chapter 2.

However, to actually implement any of these techniques one has to carefully study the target mixed signal system and design a custom solution according to the system requirements. The digital block of the system defines the characteristics of the noise being generated while the packaging, the underlying circuitry and the semiconductor technology provide for the coupling transfer function. The effect of this noise has to be studied on the analog circuitry before any suppression technology can be applied to the system. Therefore, there is a need for a more attentive approach to AMS design methodologies regarding substrate noise.

1.2 Research Problem

Despite the recent trend of replacing analog circuitry by its digital counterparts, there are some aspects that can only be implemented using analog circuits. Analog circuits are indispensable in electronic systems interacting with the environment and in every such system an ADC is required to establish a communication channel between the analog and digital blocks. Thus, a lot of effort has been put into the development of high resolution ADCs. As relatively large digital circuitry is being included to achieve even higher performance levels, there is a need of awareness of the effects of substrate noise on the ADC resolution.

In this thesis, the focus is on the effect of substrate noise on a high resolution ∆Σ ADC architecture. A ∆Σ ADC is most susceptible to the noise injected by digital transitions occurring during the analog sampling period [15]. In this work, the author seeks to model the impact of substrate noise on the resolution of a ∆Σ ADC and identify the critical conditions that degrade the performance.

1.3 Objectives

The goal of this project is to study the corelation between the substrate noise and the resolution of a ∆Σ ADC. During the thesis project, the effects and suppression techniques of substrate noises have been studied. A MATLAB model for the substrate noise source is provided alongside a study made on system level models of the ADC. The results of this study paved the way for a slightly more realistic study in the Cadence Design Environment. A Verilog-AMS model for the substrate noise generation and injection is developed and used to perform the study in Cadence Virtuoso. This approach has the advantage of making the study less complex as the behavioural model are used to validate a solution which was tested and verified at the system level beforehand. The results and models obtained in this thesis can be used for further researches into the topic and help develop a more substrate noise aware mixed-signal ASIC design methodology.

1.4 Thesis Overview

This thesis work aims to identify and analyse the critical conditions that degrade the performance of a ∆Σ ADC. The findings of the system level study will then be used to perform a Case-Study on a given ADC architecture model.

Chapter 2 provides a background study on the related topics. A brief introduction

to ADCs has been provided. Subsequently, ∆Σ are introduced and their operation

1.4. Thesis Overview 3

is explained. A short literature review on the substrate noise coupling has also been included in the chapter.

Chapter 3 presents a system level model for the substrate noise generation alongside its implementation in MATLAB. The MATLAB model for the ADC is also made available to the reader and a detailed look into the conducted study is also present.

Chapter 4 entails the circuit level modelling and study on the behavioural models. The results of the study are presented and verified on a given amplifier circuitry.

Chapter 5 presents the conclusion for the thesis and a discussion on future work.

Chapter 2

Background Study

ADCs act as bridges between the analog and digital domains of an electronic system. Conceptually, an ADC takes a continuous time and amplitude signal as input and outputs its discrete time and amplitude equivalent. However, the A/D conversion process is more complex than that and familiarity with the theoretical implications and limitations of the data conversion process is crucial to understand the working of an ADC. This chapter entails the basics of A/D Conversion and ∆Σ modulation. Modern ADC architectures consist of a number of digital blocks to meet the high resolution requirements while replacing the constraints on analog blocks.

This leads to noise coupling between the digital and analog circuits through the shared substrate. The effects of this noise, aptly named substrate noise, on a ∆Σ modulator architecture is the premise of this thesis and will be studied through the course of the thesis. Therefore, a background study on substrate noise, its effects on mixed-signal ICs and existing solutions is included in the last section of the chapter.

The sections pertaining to ADCs and ∆Σ modulation draw inspiration from [16–

18]and the readers are guided to these texts for a detailed insight into the topics.

2.1 Basics of A/D Conversion: The Ideal ADC

The operation of an ideal ADC can be depicted as a cascade of basic building blocks as shown in fig.2.1. First, the analog input x

(t) is passed through the anti- aliasing filter that protects the information content of the signal. It limits bandwidth of the signal and as a result prevents unwanted interference due to aliasing. The resulting filtered signal x

(t) is sampled at a sampling frequency f

, thus yielding a discrete time signal x

(n) = x

(nT

), where T

is the sampling interval (= 1/f

).

The N-bit quantizer maps the sampled input onto the closest discrete level out of the 2

. Finally, the encoder transforms the digital output Y

(n) of the quantizer to the required coding scheme.

FIGURE2.1: Ideal ADC Operation

As seen in fig.2.1, the two most fundamental operations involved in an ADC are

sampling and quantization. The sampling performs discretization in time whereas

quantization performs amplitude discretization. These two transformations lead to

2.1. Basics of A/D Conversion: The Ideal ADC 5

limitations in the ADC performance and thus the output is distorted compared to the input signal.

2.1.1 Sampling

A sampler transforms the continuous analog signals into its sampled data equivalent. Ideally, a sampler yields a sequence of delta functions each equalling the signal amplitude at the sampling instants. The sampling process imposes limitations on the bandwidth of the analog input. According to the Nyquist Criterion, sampling frequency (f

) at-least at twice the signal bandwidth f

to avoid information losses i.e. f

= 2f

. Based on the sampling rate ADCs can be broadly classified into Nyquist , oversampling and undersampling ADCs. ADCs operating in accordance with the Nyquist Criterion are known as Nyquist ADCs. Oversampling ADCs work at a sampling rate higher than the Nyquist frequency while under-sampling ADCs have a lower sampling rate. The different types of ADCs will be covered in detail in the subsequent sections.

2.1.2 Quantization

The quantizer assigns the sampled data-signal to a discrete level and the output value represents the quantization interval input amplitude resides in. This introduces a limitation on the ADC performance as the input signal is accompanied by an additive white noise, known as quantization noise (error).

Suppose an N-bit quantizer has an input signal varying between ±Y

/2 and the full scale output range is Y

. The quantization step (δ) for this system can be calculated as follows-

δ = Y

/(2

− 1) (2.1)

Thus, a linear model for the quantizer can be defined as - y = g

x + e(x). The quantizer’s intrinsic gain g

and error e(x) can lead to the quantizer having different full-scale values at the input and outputs i.e. X

6= Y

. The error, e(x) is a non-linear function of the input x and is bounded by ±δ/2. The input range of [−X

/2,X

/2] is known as the non-overload range and inputs outside this range lead to quantizer overload. s

The degradation resulting due to quantization noise is expressed through the in-band quantization power, P

, which can be written as-

P

=

−f_b

S

(f )df =

−f_b

S

(f )df = δ

/12 (2.2) The dynamic range (DR) of the ideal ADC can be determined as the ratio of the output power at the frequency of an input sinusoid with a maximum amplitude to the in-band quantization error power.

P

f s/2

∼ = (Y

/2)

/2 ∼ = (2

δ/2)

/2 ∼ = 2

δ

(2.3) The DR of the ideal ADC can thus be calculated as-

DR = P

f s/2

/P

= 1.5(2

) (2.4)

DR

= 6.02N + 1.76 (2.5)

Therefore, the dynamic range of an ideal ADC is limited by quantization noise.

It is also worth noting that each additional bit in the ideal quantizer results in an increase of approximately 6dB in the ADC DR.

The aforementioned ideal ADC is also referred to as Nyquist rate ADCs. These ADCs have a one-to-one correspondence between the input and output samples.

Each sample is processed separately without regard to any previous samples and so it is a memory-less converter. As the name implies Nyquist-rate ADCs can have a sampling rate as low as the Nyquist criterion i.e. they can be sampled at a rate of twice the signal bandwidth. In most cases, the linearity and accuracy of Nyquist- rate ADCs is determined by the matching accuracy of the analog components and the practical conditions restrict the effective number of bits (ENOB).

2.2 ∆Σ modulation based Converters

Most Nyquist-rate ADCs are not suitable to meet high resolution and linearity requirements. Dual Slope ADCs have the capacity to provide the resolution but have been deemed too slow for modern signal processing applications. On the other hand, oversampling ADCs have the capability to achieve higher resolutions at the expense of high latencies. Oversampling ADCs employ higher sampling rates than the Nyquist rate, typically by a factor between 8 and 512. This factor is known as Oversampling Ratio (OSR). The converter makes use of memory elements in its structure and each of its output is generated by utilizing all the preceding inputs. The implementation of oversampling ADCs requires a considerable amount of digital circuitry in addition to the already present analog circuits. The accuracy requirements on the analog circuits is a bit relaxed and thus the high accuracy comes at the price of faster clocks and inclusion of digital circuits. This has led to widespread use of oversampling ADCs in many applications previously dominated by the Nyquist-rate ADCs. The ∆Σ modulation technique has been recognized to be one of the most suitable oversampling analog-digital conversion technique for designing high resolution ADCs [19].

2.2.1 Oversampling

The key advantage of this technique is that the signal band occupies a small portion in the Nyquist bandwidth. This makes it possible to perform digital filtering on the signal, as a large fraction of noise lies outside the band of interest. Thus oversampling is used to spread the noise power in a wider spectrum and a filter is employed to reject the out of band noise, The use of an ideal digital filter after an oversampling ADC effectively reduces the quantization noise power by a factor of OSR,thus resulting in the following relation -

P

= (δ

/12) · (1/OSR) (2.6)

The dynamic range (DR) of an oversampled ADC can be written as

DR = P

/P

= 1.5 · OSR · (2

) (2.7)

DR

= 6.02N + 1.76 + 10 log(OSR) (2.8)

2.2. ∆Σ modulation based Converters 7

This implies that oversampling results in an overall increase in the dynamic range. Another effect of oversampling is on the resolution of the ADC, characterized by the effective number of bits (ENOB) of the ADC.

EN OB = n + 0.5 log

(OSR) (2.9)

Thus, the quadrupling the OSR has the potential to increase the ADC resolution by 1-bit. Thus, the use of oversampling to directly increase the resolution is not practical. However, oversampling relaxes the design constraints of the anti-aliasing filter.

2.2.2 Noise Shaping

The real effectiveness of the oversampling technique is achieved by reducing the noise power in the signal band at the expense of an increase in out of band noise.

The out of band noise is not an issue since it is removed by a digital filter.

FIGURE2.2: Principle of noise shaping

Using a quantizer in a feedback loop, as shown in fig.2.2, can have the required effect of noise shaping on a signal.

(X − Y · G(z)) · H(z) + ε = Y (2.10) The solution of the above equation results yields

Y = X · H(z)

1 + H(z)G(z) + ε

1 + H(z)G(z) (2.11)

It can be seen in eq.(2.10) that the signal and quantization noise pass through two different functions-

Y = X · ST F (z) + ε · N T F (z) (2.12) Here, STF represents the signal transfer function while NTF represents the noise transfer function. Thus, for achieving good noise shaping the signal transfer function must be a low pass filter while the noise transfer function must be a high pass filter to achieve noise shaping effect.

2.2.3 Basic Architecture of a ∆Σ ADC

The basic architecture of a ∆Σ ADC is shown in fig.2.3. As can be seen, a ∆Σ

ADC consists of a ∆Σ modulator and a digital decimation filter. The scheme consists

of four basic blocks namely the anti-aliasing filter, ∆Σ modulator, digital filter , and

the decimator.

• Anti-Aliasing Filter

The anti-aliasing filter performs the same function as in a Nyquist rate ADC i.e. attenuation of the out-of-band signal elements to avoid aliasing. However, the use of oversampling relaxes the requirements on this block.

• ∆Σ Modulator

The modulator over-samples the input signal and performs a very coarse analog to digital conversion at the resulting narrow-band signal. A coarse digital to analog conversion is used as feedback to shape the quantization error introduced in the analog to digital conversion i.e. most of the noise is shifted outside the signal band.

• Decimation Filter

The decimation filter performs the dual task of filtering and decimation. It removes the out-of-band noise provided by the ∆Σ operation.

The decimator brings the sampling rate back to the Nyquist rate. Down- sampling on digital signals is often required as it helps reduce the power requirements in digital circuits as it is mostly dependent on clocks. This process of oversampling coupled with quantization noise shaping and decimating the output results in a high precision ADC.

FIGURE2.3: Delta Sigma ADC Operation

∆Σ ADCs offer many advantages such as their inherent linearity and robust analog implementations among various others.The main advantage is the relaxation on the analog filter (anti-aliasing filter). This is achieved at the expense of increased requirements on the digital filter, which are relatively easier to fulfill. However, the introduction of digital circuitry alongside the ∆Σ modulator makes the ∆Σ ADC a mixed signal system in itself. This not only increases the complexity in the design methodology but also presents new challenges to the designer. The substrate coupling noise is one such factor that is increasingly becoming a concern in high resolution ADCs. A detailed description of ∆Σ modulators and the effects of substrate coupling are present in the subsequent sub-sections.

2.2.4 A Detailed look into ∆Σ Modulation

The ∆Σ modulator block has the largest influence on the ADC accuracy. The basic scheme of the modulator is shown in fig.2.4. It consists of a loop filter H(z), an n-bit quantizer and a negative feedback through a digital to analog converter (DAC).

The following section provides an insight into ∆Σ modulation and the reader is

guided to [16] for a complete understanding of the topic.

2.2. ∆Σ modulation based Converters 9

FIGURE2.4: Basic scheme of a ∆Σ modulator

Assuming the gain of the loop filter, H(z), is large in the signal band and small outside of it. Consequently, the error signal i.e. x − y will be insignificant within the signal band. Discrepancies in x and y are thus pushed to the out-of-band spectrum.

As seen previously, the signal passes through two different transfer functions namely the signal transfer function STF and the noise transfer function NTF.

Y (z) = X(z) · ST F (z) + ε(z) · N T F (z) (2.13) where X(z) and ε(z) give the z-transforms of the input signal and the quantization noise while STF and NTF are given by-

ST F (z) = g

· H(z)

1 + g

· H(z) (2.14)

N T F (z) = 1

1 + g

· H(z) (2.15)

Since the noise and signal are affected by different transfer function, H(z) can be modelled so as to avoid signal degradation. Assuming a unity gain in the quantizer and a high loop filter gain within the signal band, the transfer functions can be approximated as-

ST F (z) = g

· H(z)

1 + g

· H(z) ∼ = 1 (2.16)

N T F (z) = 1

1 + g

· H(z) ∼ = 1

g

· H(z) << 1 (2.17) H(z) is selected so as to achieve the L

order NTF. The easiest way to do this is to model the loop filter to be an integrator-

H(z) = z

1 − z

(2.18)

In this case, the modulator output is as follows-

Y (z) = X(z).z

+ ε(z).(1 − z

) (2.19)

This modulator is called a first order modulator, in reference to its noise-shaping

function. Subsequently, the output of an L

order modulator is-

Y (z) = X(z).z

+ ε(z).(1 − z

) (2.20) Involving the n-bit quantizer in the calculations, we can derive the following equation for the dynamic range-

DR

= 20 log(2

−1)+1.76+(2L+1)10 log(OSR)+(2L+1)10 log( (2L + 1)

π

) (2.21) We can see from the equation that the dynamic range of a ∆Σ modulator depends on the modulator order L, oversampling ratio OSR, and number of bits in the quantizer N . Thus, it is crucial to study the effects of each of these quantities on the ideal performance of a ∆Σ modulator.

• Effect of modulator order, L

Since noise shaping is crucial to a ∆Σ modulator, an increase in L can significantly increase the modulator performance. The increase in the dynamic range due to the modulator order, while keeping OSR and n constant, is calculated in [16] as-

∆DR

= 10 log ( 2L + 3

2L + 1 ) · ( OSR

π )

(2.22)

Thus, high order modulators naturally have better noise shaping capabilities.

But stability problems arise with the inclusion of higher order modulators.

• Effect of Oversampling ratio, OSR

The effects of oversampling are same on a ∆Σ modulator as any other oversampled ADC. Increasing the OSR has the potential to increase the dynamic range as-

∆DR

= 10(2L + 1) log(1 + ∆OSR

OSR ) (2.23)

For a given signal band, increasing OSR corresponds to faster circuit operation and hence increased power requirements.

• Effect of number of bits in quantizer, n

Increasing the number of bits in the quantizer leads to better performance of a ∆Σ modulator. An inverse proportionality is present between the number of bits in the quantizer and the power associated to the quantization error. In practice, it is assumed an additional bit in the quantizer leads to a 6dB increase in the modulator DR [16].

However, multi-bit modulators make use of a multi-bit DAC in the feedback.

Thus, the linearity of the modulators suffers on account of the DAC’s non- linear behavior, and is in fact limited by it.

2.2.5 Design Issues

A number of circuit and architectural design issues limit the performance of a

∆Σ ADC. It is important to have an understanding of the limits and solutions to

2.2. ∆Σ modulation based Converters 11

using these real basic blocks. Some of the issues that affect the performance of an ADC are discussed in this section. The reader is recommended to read [18] for the complete text on design issues in ∆Σ ADCs.

• Offset of the op-amp (or OTA)

The loop filter in a ∆Σ modulator can be implemented as a cascade of op-amp or OTA based integrators. Any offset present at the first integrator’s op-amp can is directly digitized. The second integrator’s offset when referred to the modulator input is dc and hence gets canceled by the high pass action of the modulator’s NTF .

• Finite op-amp gain

The finite gain of an op-amp limits the in-band aggressiveness of the NTF.

A detailed analysis on the effects of finite op-amp gain on the modulator performance indicate that the finite gain has effect on the shape of the NTF magnitude response below a certain frequency known as corner frequency, f

[18], where-

f

∼ = f

2π(A

+ 2) (2.24)

The finite gain does not have any effect on the SN R unless f

>> f

, which leads to the constraint on the op-amp gain for modulators with a medium OSR.

π(A

+ 2) >> OSR (2.25)

• Finite op-amp Bandwidth

Poles of the transfer function determine the bandwidth and the phase margin of the op-amp. The finite bandwidth of the op-amp leads to a gain error similar to that of the passive elements and has a slight effect on the modulator response [18]. The gain error is given by the following equation, where β is the feedback factor and τ

is the RC constant of the passive network.



= V

· e

(2.26) This can lead to parasitic poles in both the NTF and STF at high frequency.

However, since the parasitic poles are generally at higher frequencies, they do not affect the modulator action.

• Finite op-amp slew rate

Finite slew-rate combined with a finite bandwidth poses a significant limit.

Since slewing results in a non-linear transient response, its estimation in the z- domain is not possible, and time-domain simulations must be done. The slew rate error must be shaped by the NTF and then added to the output. Thus, in a second order ∆Σ modulator, the error in the second integrator is less critical than the first one.

• Non-Ideal ADC operation

The output of the ADC is a digital equivalent of the input plus the quantization

(

) and ADC errors 

. Thus, if 

> 

, the modulator performance is

not affected or negligible affected by non-ideal ADC operation.

• Noise

The performance of an ADC is affected by a number of noise signals arising from intrinsic as well as extrinsic sources. Intrinsic noise, mainly comprised of flicker, thermal and shot noises, is introduced by the active and passive devices in the circuit. These random device noises are a fundamental limitation in analog circuits and can be minimized by proper process, device, circuit and topology selections, and optimum bandwidth designs [4]. Digital switching noise and crosstalk are the major extrinsic noise sources. In practice, digital switching noise is the dominant source of deterministic noise in mixed-signal ICs [20]. Switching noise leads to induction of high frequency analog noise signals at the substrate, called substrate noise. Substrate noise is highly deterministic and deleterious as it can get coupled over long distances through the substrate to analog circuits.

2.3 Substrate Noise

With the aim of meeting the increased demands for less area and more functionality, the semiconductor industry has been pushing the analog-digital integration in SoC designs to new heights. This has the advantage of getting the best signal processioning from both the analog and digital domains and thus a large amount of analog circuitry is being designed alongside the digital circuits. Some of the most prevalent problems due to mixed-signal integration are chip/package capacitive and inductive coupling, ringing on the RLC tuned circuits that form the chip/package power supply rails and off-chip drivers and receivers, coupling between circuits through the chip substrate bulk, and radiated emissions from the chip/package interconnects. Over the years, substrate coupling effect has attracted the interest of mixed signal designers and a lot of research has been carried out. An overview of some of these researches has been provided in [4]. The problem has further been aggravated in mixed signal circuits with the inclusion of digital blocks in traditionally analog blocks to achieve better performance. Thus, it is necessary for today’s mixed signal designers to have an insight into substrate coupling, its effects, simulation techniques, and design methods adopted to counter the effects.

The following subsections attempt to acquaint the reader with the issue of substrate coupling and it is advised to look into [21,

2.3.1 Effects of Substrate Noise on Mixed Signal ICs

A typical mixed-signal IC has random and deterministic noise sources. Thermal, shot and flicker noises are the general contributors to the random noise levels while crosstalk, digital switching etc. are the primary deterministic noise sources. Digital switching noise is highly probabilistic and is, therefore, quantifiable in both the time and frequency domains. In reality, it is one of the dominant source of deterministic noise in mixed-signal chips [20]. This noise gets coupled to the sensitive analog circuits through the substrate and modulates their threshold voltages, gains, among other characteristics.

The significant degradation in the system performances due to parasitics occurring

in mixed signal systems is proof to the increasing influence of parasitics in today’s

mixed signal designs. More often than not, substrate has been credited to providing

a medium of parasitic coupling. A negative influence has been seen on integrated

circuits due to substrate parasitics [13–15,

2.3. Substrate Noise 13

current flowing to the bulk which in turn affects the device operation. The wire capacitances between the substrate delays signal transmission to the various locations of an IC, giving rise to a parasitic behaviour. In addition, perfect isolation between is not the substrate does not provide a perfect isolation between devices is not achieved due to undesirable crosstalk through the substrate.

Substrate Int e rconne ct s

Bonding Wire

A D

Analog Digital

Package

On-chip

Off- chip

FIGURE2.5: Simplified representation of IC parasitics

A very simplistic representation of IC parasitics is provided in the fig.2.5. The substrate block shown in the figure is , in practice, a RC network [27] and thus adds up to the existing parasitic capacitances due to the interconnects. Thus, the first effect of the substrate parasitics on an IC is the addition of its equivalent RC network to the existing IC parasitics.

Secondly, the substrate also acts as a noise propagating medium between various areas in an integrated circuit. A considerable amount of noise is present in the digital interconnects carrying switching signals as well as the digital power supply lines.

This digital noise reaches the sensitive analog cells through the interconnects and the substrate. With the constant scaling of the feature size, substrate noise coupling is becoming a critical issue in high-end IC design.

There are two distinct aspects to substrate noise. On one hand, substrate is used as a parasitic return path for signals carrying relevant information. Crosstalk happens in case a sensitive cell is present along this parasitic path is perturbed by the signal. On the other hand, the bulk conducts AC noise to ground. In this case, the least resistive path is followed and the noise flow is determined by the distribution of substrate contacts to AC ground.

The occurrence of one or the other type of parasitic effect, together with the techniques available to reduce the parasitic impact, relates significantly to the kind of wafer and process used for the IC fabrication.

2.3.2 Substrate Noise Injection in a Mixed Signal IC

Any current injected into the substrate causes fluctuations in the substrate voltage. This variation in substrate voltages is called substrate noise and is caused by coupling of switching or noisy signals to the substrate.

In digital CMOS circuits, the noise is caused by three mechanisms:

• Coupling to the digital power supply

The resistive voltage drops due to the parasitic couplings in the power-supply

connections to the chip and di/dt noise leads to the induction of noise at the

digital power supply. Ringing takes place due to inductance in the power-

supply connection and the on-chip capacitance between power and ground.

These effects are also called ground bounce or simultaneous switching noise [24,

CMOS gate, which results in a very low resistance path between the two, thus the noise is also present at the substrate. This noise coupling mechanism is often the dominant cause of substrate noise.

• Coupling from switching or noisy signals

The switching source and drain nodes of the MOSFETs in the digital circuits are the second most dominant source of substrate noise. The resulting noise has the same characteristics as the switching signals on these nodes [21]. This is not the case in the digital power supply noise where the switching causes an increase of the ground voltage inducing a positive noise peak at the substrate.

• Impact ionization in the MOSFET channel

The third source of substrate noise is impact ionization [7,

of impact ionization as a source of substrate noise depends on the technology, especially on the combination of the supply voltage and channel length.

2.3.3 Reception of Substrate Noise in a Mixed Signal IC

A typical mixed signal IC consists of both analog and digital signal processing blocks. The chip typically contains a silicon substrate in which the circuits are realized. Thus, different areas on the IC are coupled through the substrate. As mentioned earlier, the excessive switching activity at the digital end induces a noise signal in the substrate. This noise at the substrate is called substrate noise and gets coupled to the circuits and noise is reflected to each of the circuit present in the system. The analog circuits are the most sensitive to such noises and suffer a significant degradation in their performance.

The propagation of switching noise through the substrate is a three-dimensional phenomenon and the type of substrate plays a significant role in crosstalk effects.

Previous research on the topic has revealed that switching noise at heavily doped substrates gets evenly distributed throughout the chip [1]. Substrate noise effects are also heavily dependent on the layout geometry. It has been observed that the separation between analog and digital sub-systems suppresses substrate noise up- to a certain limit. This limit is found to be four times the thickness the epitaxial layer thickness. Further increases in the separation have no effect in reducing the substrate noise. An effective way to minimize the substrate noise, proposed in [1], is to reduce the substrate inductance.

In an analog circuit, the substrate is biased via the substrate contact. Thus, any noise at the substrate gets reflected into the analog circuits through coupling to the contact. Further if the analog ground is used to bias the substrate, noise can couple directly to the ground thus entering the analog circuitry via the power supply rejection ratio (PSRR). In addition to this, substrate noise is received in the analog circuits via couplings at interconnects, MOS body effect, and passive components.

The disturbances due to the interconnects and MOS body effect can be minimized by making the circuit differential and matched while that to the passive components can be suppressed by using parasitic insensitive architectures.

Using differential circuits is naturally a good solution to minimizing the substrate

noise effects in an analog circuit. The differential noise is then mostly provided by

the mismatches in the circuits. Again, making a highly symmetric circuit helps to

minimize mismatches.

2.3. Substrate Noise 15

2.3.4 Effects of Substrate Noise on a ∆Σ ADC

The effects of switching noise on a ∆Σ ADC have been previously studied in [15]. The paper presents an experimental study of the effects of switching noise on a second order ∆Σ modulator. It follows that the substrate noise can significantly limit the achievable performance in analog circuits. The effects of substrate noise is maximum when the noise appears in the vicinity of the analog sampling clock. The effect persists outside this time-frame due to ringing effect at the inductances.

The capacitive coupling between the noise source and the receptor nodes has a huge role to play. The peak signal-to-noise-plus-distortion ratio (SNDR) decreases non-linearly with an increase in the coupling strength. In the critical timing region preceding the sampling interval even a small coupling can lead to drastic drop in the ADC performance.

The research put forward in the afore-mentioned paper concludes that the decrease in performance is due to the harmonic distortion, thus implying signal dependent disturbances.

2.3.5 Existing solutions to the substrate coupling problem

The ever-growing demand for smaller feature size high performance mixed- signal SoCs combined with degradation of analog performance due to substrate noise has pushed researchers to come-up with methods to mitigate the problem.

There are three basic approaches to counter the issue at hand- reduction of noise at the source i.e. digital blocks, reduction in the coupling between the analog and digital sub-domains in a mixed signal system, and lowering the sensitivity of analog circuits to substrate noise. Each of these approaches will be discussed in detail in the subsequent sub-sections.

• Suppressing Digital Switching Noise

As mentioned earlier, parasitic couplings in the digital power supply lead to switching noise which in turn couples at the substrate. Several strategies have been introduced and used to effectively suppress the switching noise. A common solution is to lower the effective impedance on the power supply path, thereby reducing the voltage fluctuations. One way to do this is to have multiple power supply interconnects for the chip, so as to reduce the effective inductance [27]. However, just increasing the effective inductance is not enough to have better noise characteristics but it should also be kept in mind to have opposite currents in adjacent interconnects. Double-bonding (having two bond wires) the on-chip pad to off-chip interconnect is beneficial in reducing the parasitic resistance in the supply path [28]. On-chip decoupling capacitances have also been shown to have significant effect on decreasing the supply path impedance [27]. The resonance frequency of the on-chip power supply lines depends on the effective impedance which can be lowered using a simple RLC circuit [29]. The RLC values are chosen to place the impedance in the vicinity of the peak and hence counter it. A reduced supply bounce (RSB) CMOS logic has also been proposed to suppress the switching noise in digital circuits [10].

The noise induced in the substrate is a direct consequence of the switching

activity in the digital circuits. As a result, another common approach for

suppressing the noise is to controlling the unwanted switching activity in

digital circuits. In synchronous digital circuits, clocks are the trigger for any

switching activity in the circuit. Division of the entire digital circuit into sub-circuits with a dedicated clock skew can be done for substrate noise suppression [30]. This technique is effective as each sub-circuit switches at different instants and thus, the net noise coupled at substrate at any given instant is lesser in magnitude. The principle of reducing the unwanted switching can also be applied to the timing of output buffers. This is yet another simple and effective way to suppress switching noise [27]. Buffers usually have a lot of switching activity and thus are major contributors to switching noise. Although the switching activity cannot be decreased, timing the buffers to avoid simultaneous switching is a good idea to reduce noise at the source.

• Reducing Coupling between Analog and Digital Sub-Domains

Since the digital and analog circuits are realized on the same substrate, it is impossible to isolate them but the major coupling paths can be modified so as to get a weak noise signal. Since power supply bounces are an important issue in this regard, it is the obvious target for research. Thus, to prevent switching noise getting coupled to analog circuits, separate power lines are used for the digital and analog sub-domains. Even having the same off-chip power source but having separate on-chip power lines effectively reduces the coupling strength [22]. The concept, as illustrated in fig.2.6, is effective as now the on- chip power and ground lines are coupled to a off-chip point which is weakly coupled to the power source at high frequencies. Here Z

− Z

represent the packaging inductances. Major contributors to this coupling are wire capacitances, bond inductances, and other stray capacitances/inductances.

However, implementing separate power lines leads to critical design issues which must be dealt with during the design process [27].

FIGURE2.6: Illustration of separate in-chip power lines

Another effective method to decouple analog and digital sub-domains is to pay special attention to floor-planning. A lot of substrate coupling can be avoided by having a substrate noise aware approach during floor-planning by placing the noisy circuits as far as possible from the sensitive circuits [31].

An interesting approach to this is presented in [32], System-C and behavioural

level description are used to make an early estimate of the noise generation

capacities of various blocks before the floor-planning.

2.3. Substrate Noise 17

Use of guard bands is another widely researched solution. Guard bands provide a low impedance path for substrate currents. Thus, placing the guard bands between the analog and digital circuits can lead to a reduction in substrate noises. It has been observed that guard bands are effective in lightly doped substrates but their effect is limited in heavily doped substrates [4].

Another interesting approach is presented in [33], where an amplifier is used as an active guard band to sense and suppress the substrate noise.

• Desensitizing the analog circuits to Substrate Noise

Analog circuits can be made less sensitive to substrate noises by employing differential architectures [34]. A symmetric circuit can have a high rejection to substrate noises. Ideally a differential architecture should be able to completely reject substrate noise as the substrate noise has the same effect on differential paths. However, upon fabrication the differential paths are not entirely equal due to component mismatches. Furthermore, the noise injection is not symmetrical due to asymmetries of the layout with respect to the noise path.

As a result, differential architectures can suppress the substrate noise effects but cannot eliminate them.

• Planning in the frequency and time domains

Instead of targeting the noise magnitude it is also possible to modify the substrate noise frequency domain characteristics. Proper frequency planning can be done to achieve a noise shaping action on the noise, thus moving the noise to higher or lower frequencies [27]. Critical frequency components can be placed outside of the signal band to minimize its effects. The analyses of substrate noise in the frequency domain can be used for frequency planning of analog/radio frequency (RF) circuits.

Time-domain analysis of substrate noise can also prove beneficial for mixed-

signal IC design. As seen in [15], the sampling instant of an ADC can be placed

in a window where the substrate noise is negligible. In a similar fashion,

output buffers can be timed to switch when the corresponding substrate noise

has minimal impact on the analog circuits.

Chapter 3

System Level Modeling

The primary aim of a system level model is to set the design goals and priorities for the later design stages. The system specifications are captured with MATLAB/Simulink to obtain a precise definition and verification of the specifications. A system level study also allows the exploration of various architectures and configurations to meet the system requirements.

In the context of this thesis, a system level block is implemented for the substrate noise injection into existing ∆Σ ADC models. The modeling of substrate noise block takes inspiration from [1] while the ADC model has been developed by using the design methods introduced in [19].

3.1 Substrate Noise Modeling

The study in [1] presents a simplified schematic, shown in fig.3.1, to analyse the effects of substrate noise in mixed signal systems. The noise source V

refers to the switching activity leading to noise injection into the substrate. The capacitor C

models the diffusion and interconnect capacitive couplings and switching noise sources such as logic gate outputs, buffer outputs, noisy power lines, etc. The substrate bias impedance is comprised of C

, R

, and L

. V

models the simultaneous switching noise injected by digital circuits while V

is the noise received at the substrate.

FIGURE3.1: Equivalent circuit for Substrate Coupling

3.1. Substrate Noise Modeling 19

Upon analysis of the circuit, the transfer function V

/V

can be easily deduced as-

V

(s)

V

(s) = C

C

+ C

. s(s +

s

) s

+ s.

s

+

s(Cc+Cs)

(3.1) A resonance is observed in the response at frequency ω

, where

ω

=

s

1

L

(C

+ C

) − R

L

(3.2)

If magnitude of the response is large, then special steps must be taken to insure that the switching frequencies and their low-order harmonics do not coincide with the substrate resonance frequency.

Modelling V

as a unit step, the substrate noise can be calculated in the time domain-

V

= C

C

+ C

· e

· [cosβt + α

β · sinβt] (3.3)

where the damping coefficient, α, is given by- α = R

2L

(3.4)

and the frequency of oscillations, β, is given by-

β =

s

1

L

(C

+ C

) − R

4L

(3.5)

The settling behaviour is governed by the damping factor, ζ, given by- ζ = α ·

q

L

(C

+ C

) (3.6)

The maximum amplitude of the response occurs at t = 0 and is given by- V

= C

C

+ C

(3.7)

Equations (3.3) − (3.7) provide an insight into how the relative values of R

, L

, C

, and C

can be chosen to minimize the substrate noise amplitude and settling time. These equations show that the substrate noise can be over-damped (ζ > 1) or under-damped (ζ < 1), as shown in fig.3.2.

Unfortunately, the components presented in the analysis are dependent on the

implementation and cannot be adjusted arbitrarily . C

is dependent on the process

technology, circuit performance and functionality considerations. R

is determined

by size and number of substrate contact diffusions, which are in turn governed by

the latch-up considerations. On-chip decoupling capacitors can be used to increase

the value of C

and hence decrease the noise magnitude. But this measure leads

to the lowering of the substrate resonance frequency, ω

, as per the relation in

equation(3.2). However, if the value of L

is reduced, both the amplitude and settling

time can be lowered. Therefore, substrate noise can be minimized by lowering the

parasitic inductance of the IC package. In case of a conventional package, L

can be

reduced by connecting multiple bond wires to the substrate contact.

FIGURE3.2: Substrate Noise waveform as per the parameters in [1]

Although simple rules of thumb can be helpful in minimizing substrate noise effects, circuit and system simulations that can quantitatively predict substrate crosstalk effects are imperative in mixed-signal design methodology. Thus, a system level block for substrate noise waveform is designed to be included in system- level implementations of ∆Σ ADC architectures. This helps in establishing the various factors affecting the substrate coupling and quantifying its effect on ∆Σ architectures.

3.1.1 Design Process

The first step in the design procedure is to have a functional substrate noise block that can be integrated with the existing MATLAB/Simulink models of the ADC architectures. Building up on the study presented in [1], a continuous time (CT) block is implemented in Simulink, as shown in fig.3.3a, to capture the noisy switching activity and produce the resulting noise signal. For the purpose of simplicity, the digital noise aggressor has been modeled as an ideal clock having a 50% duty cycle.

Running CT blocks on SimuLink can be time-consuming if high frequency (HF) signals are present. The simulator decides the time-step depending on the highest frequency element in the model. The model, shown in fig.3.3b, generates a HF signal of the order of GHz. Therefore, an enable signal is included in the model to control the simulation time. The block has is only enabled for 50ns around the clock peaks.

The reason behind choosing 50ns can be seen in fig.3.4, where the noise waveform disappears less than 50ns after the noisy digital peak irrespective of the clock period!

However as the clock period approaches 50ns the subsequent stages of the signal start interfering with each other and lead to ringing. Therefore, the implemented CT block accurately provides the substrate noise signal corresponding to the digital signal at its input.

The next step is to define the coupling path of the noise signal into the ∆Σ ADC.

The parasitic extraction feature of Cadence Virtuoso is used for this purpose. The

schematic of the OTA , provided in Appendix A.1, used to implement integrators in

a second-order ∆Σ modulator is studied. For the given OTA model, the main entry

points for the substrate noise, as shown in fig.3.5, were found to be through the

power supply lines, the input and outputs nets, and the common-mode feedback

net. The coupling effects at the input and outputs nets (reported as nets A and B

3.1. Substrate Noise Modeling 21

(a) Substrate Noise Block

(b) Block Implementation

FIGURE3.3: CT Implementation of Substrate Noise Injection

(a) Tclk=180

ns

(b) Tclk=90

ns

(c) Tclk=45

ns

(d) Tclk=22

ns

FIGURE3.4: Substrate Noise waveforms for different clock periods.

in fig.3.5) is not considered for the course of the study as the circuit is differential and highly symmetric in nature. Therefore, the effects of these coupling paths are expected lead to negligible effects. The common-mode feedback is an important coupling path as it connects to off-chip components. However, the scope of the investigations has been limited to the layout of the amplifier and thus the effect of this path has not been extensively studied.

FIGURE3.5: Parasitics report from Cadence Virtuoso

The power supply net (reported as VDDA and VSSA in fig.3.5) is treated as the

exclusive source of substrate noise. Thus, any noise appearing at the substrate gets

coupled to the power/ground lines through a coupling capacitance. The effect of

this noise at the output can be modelled as a noise signal at the amplifier’s power

lines. Therefore, the substrate noise waveform multiplied by the amplifier PSRR can

be directly added to the integrator output in the Simulink models.

3.1. Substrate Noise Modeling 23

FIGURE3.6: Test-bench for PSRR estimation (Schematic for OTA is shown in Appendix A.1)

The natural next step is then to estimate the PSRR of the amplifier for inclusion in the system level model. A test-bench, shown in fig.3.6, is implemented to get an insight into the effects of the substrate coupling through the power supply lines.

The OTA inputs are set to get it into the operating point and a substrate noise signal is applied to the V DDA input through a coupling capacitance, as per the report in fig.3.5. Here again for the sake of simplicity, the digital noise is modeled as a simple 50% duty cycle clock signal. The digital noise is translated to its equivalent substrate noise by the sub2blk block, implemented in verilog-A (see Appendix A.2).

FIGURE3.7: Simulation set-up for the test-bench

The test-bench simulations are set-up as shown in fig.3.7. The DC analysis is

done to verify the DC operating point while the transient analysis is to see the

substrate noise waveform generated by the verilog code. The AC analysis provides