Linearization of Resistive Digital-to-Analog Converter for RF-Applications Using Compensator and Digital Predistortion

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Master of Science Thesis in Electrical Engineering

Department of Electrical Engineering, Linköping University, 2021

Linearization of resistive

digital-to-analog Converter

for RF-applications using

Compensator and Digital

Predistortion

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Linearization of resistive digital-to-analog Converter for RF-applications using Compensator and Digital Predistortion

Henrik Eklund LiTH-ISY-EX--21/5392--SE Supervisor: Yonatan Kifle

isy_{, Linköpings universitet}

Examiner: Jacob Wikner

isy_{, Linköpings universitet}

Division of Integrated Circuits and Systems Department of Electrical Engineering

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Abstract

High-speed digital-to-analog converters are critical components in many radiofre-quency (RF) applications. The resistive DAC (RDAC) architecture is suitable for high-speed implementation in extremely scaled digital circuit nodes. An RDAC core can be implemented as a resistance network and a digital block, consisting of inverters as drivers to the resistive network. One disadvantage of the architecture is the input code-dependent supply current. Combined with a non-zero supply net-work impedance, the code-dependent current will introduce non-linearity in the output voltage. One way to circumvent the problem is to use a high-performance voltage regulator, which counteracts the voltage variation in the impedance in the RDAC supply network.

In this thesis work, two alternative solutions are investigated; Compensation with another signal-dependent impedance in parallel with the RDAC core to reduce the impedance variations and a digital predistorter (DPD) which corrects the non-linearities of RDAC output voltage. The investigated techniques can be used for improving the linearity of an RDAC in certain cases. The current compensation technique works best at low frequencies, while the DPD can be used for all frequencies to relax requirements on routing resistance or voltage regulation design.

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Acknowledgments

I want to thank Assoc. Prof. Jacob Wikner, the examiner of this thesis, for all help during the master thesis, and Ph.D. student Yonatan Kifle, the supervisor of this thesis, for proofreading the report.

I would also like to thank all of you how contributed to this thesis in one way or another.

Henrik Eklund, Linköping, 2020-06-17

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List of Figures

2.1 The two major transmitter architectures described. . . 7

2.2 An ideal model of an RDAC. Dinis the input code to the drivers, and the drivers are assumed to connect the inputs of the resistive network to VDDor ground. . . 10

2.3 A spectrum with the harmonic tones marked. HD3magnitude is marked in the figure. . . 11

2.4 The response from a two-tone test. IM3magnitude is marked in the figure. . . 12

2.5 A spectrum with SFDR magnitude marked. . . 13

2.6 The conductance model of the parallel resistance DAC. . . 15

2.7 The restive network of a segmented RDAC. . . 17

2.8 The static current drawn from the reference voltage by the RDAC and the static resistance of the RDAC seen from the reference volt-age node plotted against the input code. . . 18

2.9 A simplified model with the RDAC and the supply network, which is used to characterize the non-linearity of the RDAC. . . 19

4.1 Resistance compensation, an additional parallel resistance, R0(Din), is added in parallel to the RDAC resistance, R(Din), which makes the total resistance, Rtot, constant. . . 26

4.2 Current compensation with an element which draws a variable current, I(Xin), which together with current drawn by the RDAC, I(Din), sum to a constant current. . . 27

4.3 The input code mapping between the input code and the code to the parallel RDAC for ideal drivers and DriverY. . . 28

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4.4 The current drawn from the supply network by the RDAC and the parallel RDAC in a static simulation is plotted. . . 30 5.1 Block diagram of the signal path in an RDAC with DPD, x[n] is the

input signal, xDP D[n] is the digital predistorted signal, and y(t) is

the output signal. . . 35 5.2 A model of indirect learning. A post-inverse of the RDAC is

esti-mated and copied to the DPD. . . 37 5.3 A model of a driver with routing resistance, RDD, and RSS, included. 39

A.1 Transient simulation showing the reference voltage for a 50 MHz single tone. . . 54 A.2 Transient simulation showing the reference voltage for a 1.5 GHz

single tone. . . 54 A.3 Transient simulation showing the reference voltage for a 5.5 GHz

single tone. . . 55 B.1 Frequency spectrum plots for the 5 GHz signal on an ideal model

of the RDAC. The DPD model used is a third-order polynomial. . 58 B.2 Frequency spectrum plots for the 2 GHz signal on a model with

low decoupling capacitance. The DPD model used is a GMP model with twelve taps. . . 59 B.3 Frequency spectrum plots for the 5 GHz signal on a model with

low decoupling capacitance. The DPD model used is a GMP model with twelve taps. . . 60 B.4 Frequency spectrum plots for the 2 GHz signal on a model with

routing resistance to the waveform generators. The DPD model used is a third-order polynomial. . . 61 B.5 Frequency spectrum plots for the 5 GHz signal on a model with

routing resistance to the waveform generators included. The DPD model used is a third-order polynomial. . . 62

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List of Tables

4.1 SFDR values in dBc for the RDAC for different drivers. . . 31

4.2 HD3values in dBc for the RDAC for different drivers. . . 32

4.3 IM3-values in dBc for the RDAC with different drivers. . . 32

4.4 ACPR-values in dBc for the RDAC with different drivers. . . 33

5.1 The results from the simulation with a 10 Ω resistance as supply network resistance model, the RDAC-model, and a DPD-model of polynomial type. The center frequency of the input signal is 5 GHz. 39 5.2 Simulation results from the DPD simulation with low decoupling capacitance in the LDO. . . 40

5.3 Simulation results from the DPD simulation with modeled resis-tance in the drivers to the inverter. . . 40

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Notation

Abbreviations

Abbreviation Meaning

ACPR Adjacent channel power ratio CFR Crest factor reduction DAC Digital-to-analog converter DPD Digital Predistortion

EDA Electronics design automation EVM Error vector magnitude

GMP Generalized memory polynomial

HD Harmonic distortion

IC Integrated circuit IM Intermodulation product LDO Low-dropout regulator

NMSE Normalized mean square error

OFDM Orthogonal frequency division multiplexing

PA Power amplifier

PAPR Peak to average power ratio

RDAC Resistive digital-to-analog converter

RF Radiofrequency

SFDR Spurious free dynamic range VLSI Very large scale integration

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Nomenclature

Symbol Meaning

V Voltage or electrical potential

I Current R Resistance Z Impedance g Conductance X Matrix x Vector {_.}H _{Hermitian transpose} {_.}−1 _{Inverse matrix}

||_.|| _{The norm of a vector}

x[n] Time discrete function

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1

Introduction

Resistive digital-to-analog converters (RDAC) are suitable for implementation in modern integrated circuit (IC) processes. However, the linearity performance is limited since the digital input code of the DAC is coupled to the reference voltage node of the DAC. This coupling degrades the linearity of the DAC. The supply network coupling can be remedied by compensation techniques. One technique includes a parallel RDAC supplied with another input code [1]. Another technique for improving linearity is digital predistortion (DPD). This thesis will focus on those compensation techniques applied to an RF-sampling RDAC and especially the DAC core and LDO developed in another thesis [2] running in parallel with this thesis in a joint project.

1.1 Motivation

The RDAC has been shown to be power efficient in literature and easy to scale to modern IC processes [1]. However, the linearity of an RDAC can be degraded since the impedance seen from the reference node of the RDAC is input code-dependent. This dependency is inherent in the architecture of the RDAC since the input code controls the resistances connected between the supply node and the ground node of the RDAC. Hence, the resistance between the reference and ground node will vary and causes the current through the RDAC to vary accordingly.

If the reference voltage of the RDAC is kept constant, the output voltage is linear with respect to the input code. However, an implementation with a constant supply voltage is challenging to design, very costly, and impractical. Since the supply network is not ideal and will present a series impedance, the reference

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voltage will vary with the input code. The output voltage of the RDAC is dependent on the reference voltage; therefore, the input code-dependent loading of the reference node will result in a non-linear behavior of the RDAC.

The suggested compensation techniques can potentially improve the non-linearity of RDACs when supply network resistances are present. Hence, they can be used to relax the requirements on layout routing and the LDO design. The relaxation can reduce silicon area and power consumption for reaching the same linearity or linearity improvement without extra silicon area, and power consumption added.

1.2 Aim

The project’s purpose, including this thesis, is to investigate if an RDAC could be used for high-speed implementations in wireless communications. More specifi-cally, this thesis concerns the implementation and functionality of compensation techniques for an RDAC, either with DPD or an impedance compensation net-work. These methods should compensate for non-linearities that are continuous in amplitude and phase. The compensation techniques should be tested on the DAC, including the LDO developed in a parallel thesis [2] with realistic test signals for wireless communication.

The targeted techniques are found in the literature [1, 3, 4]. In [1, 3] is an auxiliary RDAC connected in parallel proposed, supplied with an input code different from that supplied to the main DAC. The input code of the parallel RDAC is selected such that the currents from both RDACs are added up to a constant current, which ideally will eliminate the voltage variation in the common reference node [1]. Another method is to use a DPD, which is applied to the input signal to the DAC. The DPD distorts the signal such that the resulting output signal is linear with respect to the input code. DPD is commonly used for correcting the non-linearity in power amplifiers (PA) [5], although it is applied to a capacitive DAC in [4].

1.3 Research questions

The research questions studied in this thesis are:

1. Is it possible to use digital predistortion or a compensation network to compensate for non-linearities, continuous in amplitude and phase in a resistive digital-to-analog converter?

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1.4 Delimitations 3

1.4 Delimitations

This thesis has the following limitations:

• The amount of work hours is restricted to 800 hours.

• The design level will mainly be restricted to schematic level and critical so-called layout parasitics, which arise in the physical implementation. • The compensation techniques should focus on the non-linearities from

parasitics in the RDAC-network and compensate for non-linearities that are continuous in amplitude and phase.

• The power supply of the waveform generators, i.e., the supply of the switches and resistance network in the RDAC, is isolated from the rest of the supply network.

• The compensation techniques should be either a compensation network or DPD.

• The non-linearity models studied will be limited to memoryless polynomial and generalized memory polynomial (GMP).

1.5 Report outline

This thesis report consists of seven chapters and three appendices. They are structured in the following way:

• Chapter 1, Introduction, contains the motivation and the aim of the thesis. The research question used in the study and the delimitations of the thesis is defined in this chapter. Lastly, the outline of the report is outlined. • Chapter 2, Theory, servers as a basis, and the further chapter relies on

it. Modern mobile telecommunication systems and RF-sampling DAC are described briefly. The performance metric used to evaluate the results and the models used in the later chapters are presented.

• Chapter 3, Method, describes how the study is conducted and describes how the DPD is simulated.

• Chapter 4, Compensation, starts with a description of the used impedance compensation structure and it is implemented. Next, the input code map-ping is derived, and a distributed approach is discussed and dismissed. Finally, the results from the simulations are presented.

• In chapter 5, Digital predistortion introduces the second linearization tech-nique in the two first parts. Then an additional metric is presented for performance comparison of DPD. In the last part of the chapter, the results from the DPD simulations are presented.

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• In chapter 6, Discussion, is the discussion of the thesis presented, which is di-vided into three parts: Resultdiscussion, Methoddiscussion, and a discussion about the work in a wider context.

• Finally, in chapter 7, Conclusion, the thesis is closed by a conclusion of the study and some suggestions on future topics to research.

• Appendix A, Reference voltage plots, contains figures with the reference voltage from a transient simulation plotted.

• Appendix B, Digital predistorion simulation figures, contains figures from the DPD simulations.

• Appendix C, MATLAB script, contains the script used to derive the current from the RDAC model symbolically.

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2

Theory

This chapter introduces the fundamental theory and starts with a brief overview of a transceiver structure, focusing on the transmitter part, where the DAC is an essen-tial component. After the background of the transmitter chain, a brief description is given of orthogonal frequency division multiplexing (OFDM), commonly used in modern mobile communication. These two parts outline the need for high lin-earity in the DAC. Thereafter, the most common RF-sampling DAC architectures are described, which bridges the gap toward the more implementation-specific background about a non-linearity source in the RDAC.

2.1 Modern mobile telecommunication systems

For an increasing number of persons, mobile telecommunication is an essential part of everyday life. Mobile data is dominating the traffic in modern telecommuni-cation systems. Streaming movies and playing online video games on smartphones are made available to many of the world’s population with increased data rates provided by 4G. Today, the fifth generation of mobile communication system (5G) is deployed in most countries around the globe. It should provide a large amount of data at high data rates, serve a large number of users and be reliable with low latency.

The fulfillment of these needs puts additional requirements on the transceivers in the system since the fundamental resource used in telecommunication systems is the heavily occupied electromagnetic spectrum. It has forced the systems to implement new techniques like massive MIMO and move the radio frequency for transmitting the data partly to higher frequency bands [6]. It is, therefore,

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desirable to investigate new architectures for high-speed DAC implementation, which is an essential part of the transmitter chain in mobile telecommunication systems.

2.1.1 Transmitter

Transmitters are the telecommunication system part that emits the signal into the free space where electromagnetic waves propagate. Put simple transmitters can be assumed to consist of two parts: A digital signal generation part and a filtering and amplification part. The data generation part is commonly implemented as a digital signal processing unit, in implementations called a baseband processor. After the digital signal is generated, it must be converted to an analog signal before filtering and amplification, and being transmitted out in free space. The conversion from digital to analog signal is where the DAC serves its purpose in the transmitter chain. The analog part, which follows the DAC, consists of at least a power amplifier (PA). However, depending on the transmitter architecture used, the analog part could consist of more analog blocks, like filters and mixers. Transmitter architectures may be divided into two categories: Architecture with mixers and RF-direct. Simplified models of the two architectures are presented in Figure 2.1, where Figure 2.1a and Figure 2.1b depict a transmitter with a mixer and an RF-direct transmitter, respectively. A baseband processor is used in architectures with mixers, which operate up to the signal’s bandwidth and generates a digital baseband signal. The digital baseband signal is converted to an analog signal which is up-converted via an intermediate frequency where filtering and amplification of the signal are done or directly to the RF. The RF-signal is then fed through filters and a PA before the antenna. In the RF-direct architecture, a digital RF signal is generated in a signal processor, and then is a DAC used to generate the analog RF-signal. The RF-direct architecture is especially desirable1 in modern telecommunication systems since it moves the up-conversion of the signal into the digital domain and minimizing the analog part of the transmitter. In the RF-direct architecture, the requirements on the DAC are much more de-manding since it should output a signal in the RF frequency range, typically above 1 GHz. They should also support different frequency bands and preferably convert wideband signals, which nowadays is used to provide high data rates to many users. The wideband signal transmitted will by itself put challenging require-ments on the linearity of the RDAC to avoid generating distortion in channels

1_{The advantage of the RF-direct architecture is firstly the control of the noise in the modulation of}

the signal. In a digital signal processor, the signal’s noise will be the same independent of process, voltage, and temperature variation as long as the digital block works. If this signal processing is done with analog electronics, there can be noise from the mixing-frequency sources and process, voltage, and temperature variations. Secondly, a complete radio transmitter is much easier to implement in an IC if it does not need oscillators. Lastly, multiband communication standards support are simplified with RF-sampling DACs, which can generate RF signals in different frequency bands without mixers and oscillators, compare with software-defined radio.

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2.1 Modern mobile telecommunication systems 7

DSP DAC Mixer BPF PA

(a)A simplified model of a transmitter with a mixer. In this type of architecture is the RF signal generated after the up-conversions

DSP RF DAC BPF PA

(b)A simplified model of an RF-direct transmitter. The RF signal is generated directly by an RF-sampling DAC.

Figure 2.1:The two major transmitter architectures described.

adjacent to the allocated bandwidths. A commonly used modulation scheme in high data rate and multi-users implementation is OFDM, elaborated on in the following section.

2.1.2 Orthogonal Frequency Division Multiplexing

One common problem in high-data rate wireless systems is multi-path propaga-tion. The effect arises since the transmitted radio signals propagate both straight from the transmitter to the receiver and through reflections in buildings or other objects. The multi-path propagation makes the same signal arrive at the receiver with slightly different time delays and potentially destroying the data. Multi-path propagation and intersymbol interference, which multi-path propagation leads to, are critical when the transmitted signal has short symbol periods.2 One commonly used method to circumvent this problem is to split the data into several data streams where narrow-band signals transmit each data stream. In this case, the signal will be less affected by the multi-path propagation since each data stream, and narrow-band signals have slower variations than the wideband signals with the same data rate [7].

This modulation technique is called Orthogonal Frequency Division Multiplexing (OFDM) and is widely used in modern communication standards: LTE (4G), NR (5G), and WiFi (IEEE802.11) [7]. One disadvantage of OFDM is that it requires a

2_{A high data rate requires more symbols and, therefore, a short symbol period. The symbol period}

is inversely proportional to the bandwidth. Hence, a wideband signal is required for transmitting a large amount of data [7].

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highly linear transmitter chain. The linearity requirement is higher because of the large envelope variation in the OFDM signals caused by sub-carriers constructively or destructively interfering with each other [7].

PAPR

An issue with OFDM signals is the peak to average power ratio (PAPR), which is larger compared to other modulated signals. Unlike other modulation schemes, the calculation of PAPR is complex for OFDM signals since they consist of a number of active sub-carriers, N , which can either be interfering constructively or destructively. The theoretical value of an OFDM symbol can easily be derived to (2.1), where N is the number of the active sub-carriers, and K is the PAPR for the modulation of each sub-carrier [7]. For QPSK/4-QAM, K = 1.

PAPR = N · K (2.1)

In a practical implementation, the absolute peak value has an extremely low probability of appearing since it requires that all sub-carriers have the same phase. A more probable value of the PAPR is based on an asymptotic analysis of OFDM signals. Equation (2.2) states the approximation of the PAPR for OFDM symbols with a large number of sub-carriers, K is the PAPR for each sub-carrier, and N is the number of active sub-carriers [8].

PAPR ≈ 2 ln K N (2.2)

Crest factor reduction

One general method employed in telecommunications systems to address high PAPR is crest factor reduction (CFR). The crest factor measures the same thing as PAPR but is defined as the root-mean-square value instead of the power value, and therefore, the crest factor equals the square root of the PAPR value. CFR reduces the power difference between the peak power and the average power in some pre-determined way. A couple of different CFR methods exists and are presented in [9]. One is a hard-clipping of the signal like (2.3), where x(t) is the original signal, ˆx(t) is the hard-clipped signal, and Athis the clipping level of the signal [9].3

ˆ

x(t) = min(|x(t)|, Ath)earg(x(t)) (2.3)

Other methods use more sophisticated techniques which reduce the detrimental impact on the spectral purity typical at the expense of increased error vector magnitude (EVM). For example, one technique is the insertion of pulses where

3_{Hard clipping can raise the HD}

3and IM3values of the signal before the DAC, hence destroying

the linearity of the signal before the DAC. When hard clipping is used, the clipping value for OFDM signals should be chosen to be larger than the approximated PAPR value in (2.2).

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2.2 RF-sampling digital-to-analog converter 9

the peak is too high but with the opposite sign and a bandwidth lower than the signal’s bandwidth to reduce the peaks to the desired level without destroying the in-band signal [9].

2.2 RF-sampling digital-to-analog converter

A digital-to-analog converter converts a digital input signal to an analog output signal. The translation between digital to analog is not trivial since a digital signal is discrete in time and amplitude, and the analog signal is continuous in time and amplitude. The digital signal consists of input bits that control an analog quantity according to its weight.

There are a few commonly used DAC architectures; those are using either current, charge, or voltage as the analog quantity. For example, one of the most used techniques in high-speed design is the current steering DAC, where the input bits control current sources connected to the output. Another architecture is the capacitive DAC [10, 11]. In this thesis, the voltage mode resistive architecture is studied, where the output voltage is generated by the resistive division of a reference voltage in a resistive network [1].

A voltage mode RDAC can consist of digital blocks and a resistor network; hence it is simple to implement in process nodes tailored for digital circuits. Each bit controls a driver, which is a properly sized inverter. The inverter connects an input to the resistive network to the high reference voltage or the low reference voltage. How the network is designed depends on the segmentation of the RDAC, but one possible segmentation of the resistive network is depicted in Figure 2.2. The input bits can be converted to an input-code, Din. As seen in Figure 2.2, a

certain number of unit resistors are connected in parallel to the high reference voltage, VDD, or the low reference voltage, ground. Thus, the output voltage, VOut,

is changed, which is the voltage over the load resistance, RL.

The problem with the RDAC is, and which will be further discussed and derived in the last two sections of this chapter, that the current drawn from the supply node is input code dependent. Therefore, a non-zero supply impedance in series with the RDAC will cause the output voltage to be non-linear. One method to reduce the non-linearity is to use an on-chip voltage regulation at the reference node,

VDD, to stabilize the reference voltage. Other techniques to reduce the non-linear

behavior are to compensate for the input impedance variation or use predistortion to correct the non-linearity digitally. These two techniques will be presented in chapter 4 and chapter 5.

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RU 2N_−1−D_in RU Din RU 2N_−1−D_in RU Din RL + − VOut VDD VDD

Figure 2.2:An ideal model of an RDAC. Dinis the input code to the drivers,

and the drivers are assumed to connect the inputs of the resistive network to

VDD or ground.

2.3 Digital-to-analog converter performance

In this section, the performance metrics used to evaluate the performance of the compensation and DPD techniques are described. The quantities are com-monly used for characterizing the severity of the non-linearities of the transmitter components.

2.3.1 Harmonic distortion

Harmonic distortion arises in a non-linear system if the input signal is a harmonic tone, i.e., a sinusoidal. If the system is entirely linear, the output will consist of only one frequency, the input frequency. A non-linear memoryless system can be described as (2.4), where y(t) is the output signal, x(t) is the input signal, and ai

is the coefficients used to describe the gain of each term.

y(t) =

∞ X

i=0

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2.3 Digital-to-analog converter performance 11 f[Hz] POut[dBm] 1 st harmonic 2 nd h . 3 rd h . 4 th h . 5 th h . 6 th h . HD3[dBc]

Figure 2.3:A spectrum with the harmonic tones marked. HD3magnitude is marked in the figure.

With sinusoidal stimuli to the system, i.e., x(t) = A cos ωt, y(t) will be given like (2.5) where overtones are present.

y(t) = a0+ a1A cos ωt + a2A2cos2ωt + a3A3cos3ωt + . . .

= a0+ a2A2 2 + a1A + 3a3A3 4 ! cos ωt + a2A 2 2 cos 2ωt + a3A3 4 cos 3ωt + . . . (2.5)

If a2, a3, . . . are none-zero, i.e., a non-linear system, the output will have other frequencies in addition to the fundamental frequency. These other frequencies or tones are called harmonic distortions (HD). HD is measured as in (2.6), where PS

is the output power of the fundamental frequency and PH Di is the output power

of the ithharmonic [12]. For reference to the spectrum, see Figure 2.3. HDi = 10 log10

PS

PH Di

(2.6)

2.3.2 Intermodulation product

Intermodulation products (IM) are another effect of non-linearity in a system. They arise when the input signal has two or more frequencies. Let x(t) = A1cos ω1t +

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f[Hz] POut[dBm] f2− f1 2f1− f2 f1 f2 2f2− f1 f1+ f2 IM3[dBc]

Figure 2.4:The response from a two-tone test. IM3magnitude is marked in the figure.

the system will have tones at frequencies being linear combinations of integer weighted frequencies, so-called IM [12, 7]. E. g. in case of a non-linearity of order three or higher, there will be two output tones close to the fundamental tones at frequencies 2ω1−ω2and 2ω2−ω1. Since they are close to the fundamental tones, they are of certain interest to keep low4. IM is also a common way to measure the non-linearity of a system. IM3is calculated as in (2.7), where PS is the output

power of one fundamental tone and PI M3 is the power of one of the third-order

IM of interest [13]. See Figure 2.4 for reference to the frequency spectrum from a two-tone test.

IM3= 10 log₁₀ PS

PI M₃ (2.7)

2.3.3 Spurious-free dynamic range

In DACs and transceiver chains, the dynamic range is an important metric and especially the spurious-free dynamic range, SFDR. It is often defined as the range between the maximum output power and the largest spur [12]. A spur can be a harmonic tone, an IM, other distortion, or noise. The SFDR value shows how large or small signal-powers that are possible to transmit without destroying the

4_{In a multi-channel system large IM would potentially destroy the neighbor channels and also leak}

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2.3 Digital-to-analog converter performance 13

f[Hz] POut[dBm]

Signal

SFDR[dBc]

Figure 2.5:A spectrum with SFDR magnitude marked.

signal. SFDR is calculated as in (2.8), where PS is the output power of the signal

and PSpur is the output power of the largest spur [12], see Figure 2.5.

SFDR = 10 log₁₀ PS

PSpur (2.8)

2.3.4 Adjacent channel power ratio

In transmitters, which a DAC can be a part of, the adjacent channel power ratio (ACPR) is an important metric since communication standards often require the transmitters not to leak into adjacent frequency bands or channels [13]. If the leakage is too large, it will be seen as in-band interference to the signal transmitted in other telecommunication systems. Therfore, a wideband input signal according to the targeted specification must be used to measure the ACPR. The ACPR value is defined as in (2.9), where PS is the output power of the signal and PAdjacentis

the output power in an adjacent channel [13].

ACPR = 10 log₁₀ PS

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2.4 Models of the resistive digital-to-analog converter

This section describes voltage-mode RDAC models and starts with a simple model, which is assumed to be amplitude continuous. In the second part of this section, the behavior of a more realistic model, a segmented RDAC, is studied. The theory from this second part will be used to propose a compensation method of the segmented RDAC. In each part, the output voltage and input impedance of the model are derived. These properties are used to determine the cause of the non-linearity in the RDAC. The cause will be presented at the end of this section.

2.4.1 Amplitude continuous model of resistive digital-to-analog

converter

The starting point will be an RDAC model based on a parallel resistance DAC, of which the resistance network is depicted in Figure 2.2. The first step of the analysis is to transform the network into conductances to facilitate the analysis. (2.10) -(2.12) are used for transforming the structure in Figure 2.2 to Figure 2.6a. In the figure and equations, N is the number of input bits, RU is the unit resistance,

and RLis the load resistance. It can be shown that if the load conductance, gL,

is split into two equally sized conductances, the middle point of the parallel resistance structure will then have a constant potential, VDD/2, which is marked

in Figure 2.6b. gs= 2N−₁ RU (2.10) gL= 2 RL (2.11) a = Din 2N−₁ (2.12)

From the half-equivalent conductance model of the RDAC, it is possible to derive an expression for VOut/2; VOutis expressed in (2.13). It is also possible to derive the current drawn by the RDAC from the reference voltage, VDD, which can be

used to calculate the resistance of the RDAC, RRDAC. The current and resistance

are given in (2.14) and (2.15), respectively.

VOut= 2VDDgs( 1 2−a) gs+ gL (2.13) IDD = VDDgs gs+ gL (2(1 − a)ags+ gL 2) (2.14) RRDAC = gs+ gL gs(2(1 − a)agS+ g2L) (2.15)

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2.4 Models of the resistive digital-to-analog converter 15 (1− a)gs ags (1− a)gs ags gL/2 + − VOut VDD VDD RRDAC

(a)The conductance model of the RDAC with conductance values annotated. a represents the input code, which is a continuous variable between 0 and 1, RRDAC is the input

resistance seen from the reference node, VDD.

(1− a)gs ags (1− a)gs ags gL + − VOut 2 gL + − VOut 2 VDD VDD VDD 2

(b)The load conductance is split into two conductances to clarify that the middle point will have a constant voltage independently of the input code, which is half of the reference voltage.

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2.4.2 Segmented model of the resistive digital-to-analog

converter

In subsection 2.4.1, a parallel resistance DAC is analyzed. There is at least one issue with the unsegmented parallel resistance DAC. The number of resistances scales exponentially with the DAC resolution5, and the resistance network in a 12-bit DAC of this type will consist of 8190 unit resistances. The large number of resistances can potentially be hard to handle in a layout design as they consume a large silicon area.

The actual implementation of the RDAC designed in the parallel thesis work [2] is segmented into: A 6-bit binary-coded LSB part built as an R-2R-ladder and a 6-bit unary-coded MSB part built as a parallel resistance network. The parallel resistance part is controlled by thermometer-coded inputs6and has 63 inputs. The resistance network of the segmented RDAC is depicted in Figure 2.7 and contains 166 unit resistances.

The first steps to derive the output voltage and the input impedance of RDAC are the same for the simplified conductance model. It is possible to split the circuit into a half equivalent and find the VOut/2 for this circuit. The output voltage is

stated in (2.16), where VDDis the reference voltage, RLis the load resistance, R is

the unit-resistance, t is the number of bits in the parallel resistance network, b is the number of bits in the R-2R ladder, biare the input bits to the R-2R ladder, and thinis the input code to the parallel resistance network.

VOut= VDDRL RL 2 + 2R2t        1 2t        b X i=1 bi2 −_i + thin        −1 2 2t+b−₁ 2t+b        (2.16) The complexity of the segmented network makes the derivation of the total current drawn from the reference node, and thus the derivation of the input impedance cumbersome to derive analytically. Instead, a symbol handler was used to derive an expression for the current drawn by the segmented RDAC model. The MATLAB-script used to derive and verify the total current drawn by the RDAC is attached in Listing C.1. The current drawn from the reference node in the segmented RDAC model is given in (2.21) derived from (2.17) - (2.20). Since all expressions include the reference voltage, VDD, the impedance seen from the reference node can be

derived, but the need for a closed expression is less important. The static current and the impedance seen from the reference node are plotted in Figure 2.8.

5_{In a parallel resistance network, the number of resistances equals 2 · 2}N_{, where N is the number}

of bits, i.e., the resolution

6_{A thermometer code is reducing the glitches when switching between input codes. It takes the}

value represented by the input bits and translates it to a code-word with exactly that number of high inputs. The straightforward way to connect the waveform generators without thermometer code is to dedicate each input bit to a weighted number of waveform generators. The disadvantage of this method is that the switching activity will be higher than with thermometer-code.

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2.4 Models of the resistive digital-to-analog converter 17 2R 2R b1 R 2R b2 R 2R b3 R 2R b4 R 2R b5 R 2R b6 R thin R 2t_−1−th_in R₂L RL 2 R 2t_−1−th_in b1 2R 2R b2 2R R b3 2R R b4 2R R b5 2R R b6 2R R R thin + − VOut VDD VDD VDD 2 2 t+b −1 2t+b

Figure 2.7:The restive network of a segmented RDAC.

IMSB(thin) = VDDRL R(R + 32RL)thin 26− 1 26 −thin (2.17) II N T(thin, b) = − VDDRL R(R + 32RL) thin b X i=1 bi2−(6−i) (2.18) ILSB(b) = − VDD 219_{R(R + 32RL}₎      2 8_{(R + 32R} L) b−1 X i=1 b−1 X j=i+1         bibj2i+j b−1−j X k=0 4k         + 26RL b X i=1 b X j=i+1 bibj2i+j + 27(R + 32RL) b−1 X i=1        b2_i22i b−1−i X k=0 4k        + 25RL b X i=1 b2_i22i−₂8_R b−1 X i=1        2ibi b−1−i X k=0 25+k−₄k        −₂6_R_L b−1 X i=1 bi        218−₂i        1 + 27 b−i X k=0 4k               −₂12_b₆_R_L₂12−₁       (2.19) C = VDD 219_{R(R + 32R} L) (5595072RL+ 16943871R) (2.20) IRDAC= IMSB(thin) + II N T(thin, b) + ILSB(b) + C (2.21)

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0 512 1024 1536 2048 2560 3072 3584 Input code[D _in] 3.5 4 4.5 5 5.5 6 6.5 7 7.5 8 Current[mA] 80 100 120 140 160 180 200 Resistance[ ]

Figure 2.8:The static current drawn from the reference voltage by the RDAC and the static resistance of the RDAC seen from the reference voltage node plotted against the input code.

2.4.3 Characterization of the resistive digital-to-analog converter

model

Both models of the RDAC have shown an input code-dependent input impedance and an output voltage dependent on the reference voltage. Combining these two properties will degrade the linearity if any resistance is present in the supply network. The resistance in the supply network will, together with the RDAC, which can be seen as a variable resistance, form a voltage divider so the voltage at the reference node, VRef, can be described as (2.22). A model of the voltage

divider is depicted in Figure 2.9.

VRef(Din) =

VSupplyRRDAC(Din)

RSupply+ RRDAC(Din)

(2.22) If the simplified RDAC model is used as RRDAC(Din) in Figure 2.9 together with

the output voltage given by (2.13) and input impedance given by (2.15), a first-order approximation of the reference voltage of the RDAC can be derived, see (2.23). With the approximation of the reference voltage, it is also possible to derive the output voltage with the supply network present. VRef is the reference voltage

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2.5 Summary 19

R

RDAC

(D

in

)

R

Supply

+

−

V

Supply

+

−

V

Ref

Figure 2.9: A simplified model with the RDAC and the supply network, which is used to characterize the non-linearity of the RDAC.

(2.24) is obtained, an approximation of the output voltage with a supply resistance present. (2.24) has a first-order term of the input code, a, and a third-order term7, and thus the output voltage will become non-linear.

VRef = VSupply 1 − RSupply

gs gs+ gL 2a(1 − a)gs+ gL 2 ! (2.23) Vout= (1 − 2a)gs gs+ gL VSupply 1 − RSupply gs gs+ gL 2a(1 − a)gs+ gL 2 ! (2.24)

2.5 Summary

This chapter has described some of the basic concepts within modern telecommu-nication systems like 4G and 5G. It includes a brief description of the transmitter, why RF-sampling DACs are desirable, and why OFDM is used as a modulation technique when the system supports high data rates. After that, the performance measures for DACs used in this thesis were presented. Lastly, the two RDAC models used are described and how a non-linearity arises in the output voltage if the power supply has a non-zero impedance.

7_{The variable substitution a = 1/2 + b will show an expression with a first-order, and a third-order}

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3

Method

The method chapter describes how the thesis is conducted and how the results are achieved. In general, the same method is used for the two different linearization techniques. How the performance is simulated with the different techniques is described in the following sections.

The compensation structure and the digital predistortion are built on understand-ing why the RDAC structure has an input code-dependent resistance and supply current. The code-dependent impedance is well described in [1], the starting point of this thesis. Other literature is searched for in IEEE Xplore and through the search services provided by the library at LiU. Keywords used in the initial phase of the literature study are Resistive DAC, Digital Predistortion. The dissertation and papers found have been used to find more related work.

Based on the findings from the literature survey, the model in subsection 2.4.1 is created, and the model is analyzed further to understand the challenges with the compensation. A mathematical model based on functional simulation in MATLAB is implemented, and essential characteristics are derived from the model. The simplified RDAC model is also tested together with the proposed compensation structure. In addition, the simplified model is simulated in an EDA-tool allowing for more accurate simulations.

After the simplified model is developed and studied, experience gained from the model will be applied to a more realistic model of the RDAC implementation. The model is described in more depth in subsection 2.4.2. The method is similar to the one used with the simple model: First script simulations and then EDA-simulations.

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The DPD part has been researched in parallel with the compensation part. From the literature, the fundamental models and calculations are implemented in scripts. The technique is known to work for PAs [5], so initially, the scripts were adopted to work for DAC models. When the scripts were verified to work, they were used to simulate and find a good set of coefficients for the polynomial model and the GMP model.

3.1 Compensation performance simulation

The performance is simulated in EDA-software, and the quantities mentioned in section 2.3 are compiled. The performance is measured with and without compensation on a segmented RDAC model and an LDO model.

Single-tone simulations are simulated with an input harmonic frequency swept from 0.5 GHz to 5.5 GHz in 1 GHz steps. From the single-tone simulation, SFDR and HD3values are collected. The IM3 value is simulated with a two-tone test with a spacing of 46.875 MHz. The ACPR value for the RDAC model with and without compensation is simulated as well. In ACPR simulations, the input signals are generated as the test signals for estimation of the DPD-model, described in section 3.2.

3.2 Simulation of digital predistortion estimation

The estimation and simulation procedure of the DPD will be described in this section. The procedure consists of five steps:

1. A MATLAB script generates a wideband modulated signal to serve as a test signal, mimicking an OFDM signal.

2. An EDA-software simulation of the RDAC model to which the test signal is fed. The EDA-software simulation generates an output voltage waveform. 3. A MATLAB script for estimating the coefficients in the DPD model based

on the test signal and output voltage waveform. This step generates a predistorted signal according to the DPD model used.

4. An EDA-software simulation with the RDAC model where the predistorted signal is applied. The EDA-software simulation generates an output voltage waveform.

5. A MATLAB script calculating the NMSE value and the ACPR value of the output signal compared to the input signal and the test signal.

The test model in the DPD estimation is initially an ideal RDAC model without dynamic effects. After the scripts are verified to work for the ideal RDAC model, the test model is changed to a more realistic RDAC model.

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3.3 Summary 23 A problem with the GMP model is the ample space of possible coefficient combi-nations. An ordinary polynomial has an order which can be modified. In the GMP model, each term and order can have multiple taps representing different delays of the input signal samples. In addition, terms dependent on products of signal samples with different delays, so-called cross-terms, can be introduced. They have a polynomial order as well. Hence, the task of finding a good coefficient set for the GMP model is complex.

In the literature, some optimization methods have been used to find an optimal solution [14, 15, 16, 17]. However, the time restriction on the thesis limited the possibility of using these methods to find an optimal set of coefficients. Instead, an ad-hoc method is used where a new term is added to the GMP model, and then swept to find the best delay value. After the optimal tap position is found for a term, a new term is introduced and the sweep is repeated. This procedure is continued until new terms do not improve the result or the performance reaches a threshold limit.

3.3 Summary

This chapter describes the method used in the thesis for studying the proposed compensation structure and the DPD-model. The method for researching and sim-ulating compensation and DPD is presented with a description of the estimation simulation of DPD model coefficients.

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4

Compensation

The compensation chapter is divided into the following parts: First, the two different ways to look at the problem are presented, resistance and current. In connection to the problem description, two equations are presented, which math-ematically describe the solution. After that, the implementation-specific input code mapping is presented. It is followed by a discussion about a layout aspect of the compensator; Is it possible to design a distributed compensator structure to avoid degradation caused by routing resistance. Finally, the results from the schematic simulation are presented, using both static and dynamic simulation of the RDAC.

An RDAC suffers from a non-linear output if the supply to the reference node has a non-zero output impedance because of the code-dependent input impedance of the RDAC. This thesis aim is to show that there exist techniques to compensate for these properties. A structure is needed, which together with the RDAC forms a constant parallel resistance between the reference node and ground or makes the current drawn from the supply network constant.

4.1 Resistance approach

Since the RDAC has a varying input impedance, the resistance approach idea is to add resistance in parallel to the RDAC, which together with the RDAC forms a parallel resistance with a constant value between the reference nodes of the RDAC. A model of this idea is depicted in Figure 4.1, and it is mathematically described in (4.1), where R(Din) is the input resistance of the RDAC and R

0 (Din)

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R(Din) R0(Din) Rtot

Figure 4.1: Resistance compensation, an additional parallel resistance,

R0(Din), is added in parallel to the RDAC resistance, R(Din), which makes the

total resistance, Rtot, constant.

is the input resistance of the compensator. The value of the parallel resistance can be calculated as (4.2). Rtot must be smaller or equal to the minimum resistance of

the RDAC.1 Rtot = R(Din)R0(Din) R(Din) + R0 (Din) (4.1) R0(Din) = R(Din)Rtot R(Din) − Rtot (4.2)

4.2 Current approach

The other way to look at this problem is the variation in the supply current. The origin of the variation is the resistance variation, but looking at the current provides another view of the problem. It is known from the previous part that the reference voltage variation comes from the current drawn through the supply network impedance. If it is possible to counteract the variation, the reference voltage would be constant, as desired. Hence, a current source designed to draw a current from the reference node would stabilize the reference voltage variations. To achieve this, the total current drawn from the supply network must add up to a constant current. The current compensation is the method suggested in [1, 3]. Mathematically it can be described as (4.3), and a model of such a system is depicted in Figure 4.2. IRDAC(Din) is the current drawn by the RDAC, and

ICompensator(Xin) is the current drawn by the compensator.

Itot= IRDAC(Din) + ICompensator(Xin) = C (4.3)

1_{A parallel resistance can never be larger than the smallest resistance, which forms it unless negative}

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4.3 Input code mapping for the segmented RDAC 27

R(Din)

I(Xin)

I(Din)

Figure 4.2:Current compensation with an element which draws a variable current, I(Xin), which together with current drawn by the RDAC, I(Din), sum

to a constant current.

A full resolution RDAC is suggested in [1] to be used for the current or resistance compensation, while an RDAC with lower resolution is suggested in [3]. The full resolution RDAC solution will be the focus of this thesis. A solution with the simplified RDAC used in parallel yields the equation (4.4), where IRDAC(Din) is

the current drawn by the RDAC at input code Dinand Dinand Xinare the discrete

input codes for the RDAC and the parallel RDAC, respectively, while a and b are the continuous input codes used in subsection 2.4.1 for the simplified RDAC model. A solution to (4.4) is given in (4.5) for the continuous input code model.

IRDAC(Din) + IRDAC(Xin) = IRDAC(a) + IRDAC(b) = C ∈ R (4.4)

b = 1

2± √

a − a2 _(4.5)

Equation (4.5) can be translated to a discrete parallel resistance structure with the transformation equation (2.10)-(2.12), and the input code for that structure is obtained as in (4.6). The complexity of the segmented RDAC model makes it hard to find a closed expression for the input code mapping for that model.

Xin= 2N−₁ 2 ± q (2N−_1)D_in−_D2 in (4.6)

4.3 Input code mapping for the segmented RDAC

An expression for the current drawn by the RDAC is derived in subsection 2.4.2, and it can be used for deriving an expression for the input code to the parallel RDAC. The intention is to achieve a current close to constant. Thus, it can be expressed as (4.7), which provides the combination of input codes that is closest to the maximum and minimum current that a single RDAC draws.

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0 512 1024 1536 2048 2560 3072 3584 Input code, D _in 0 256 512 768 1024 1280 1536 1792

Parallel RDAC input code, X

in

Ideal drivers DriverY

Figure 4.3:The input code mapping between the input code and the code to the parallel RDAC for ideal drivers and DriverY.

Xin(Din) = argmin

Xin∈[0,2047]

|_I(D_in_{) + I(X}_in_{) − (max I + min I)|} _(4.7)

The motivation behind (4.7) and the input code mapping is that the constant current must be possible to achieve if one of the RDACs draws the minimum current or the maximum current. The current with this property is the total current drawn when one of the RDACs draws the minimum current, and the other RDAC draws the maximum current. If this condition is satisfied, all codes will have a matching code that minimizes the difference between the ideal current and the achieved current. Further on, only half of the input code space is used, either [0, 2047] or [2048, 4095], since the current drawn by an RDAC has a parabolic-like distribution around the middle point.2

Instead of solving (4.7) analytically, the mapping can be numerically calculated with a MATLAB script. One additional mapping is done based on a static simula-tion with one of the schematic level drivers designed in [2], in this thesis referred to as DriverY. The results of the static simulation can be seen in Figure 4.3.

2_{The current in the ideal model is symmetrical. The current in realistic RDAC model is not perfectly}

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4.4 Local compensation 29

4.4 Local compensation

In a physical implementation of a VLSI-IC, additional layout parasitics will be added, which are considered neither in the theory models nor in the simulation models. A parasitic type that potentially can destroy the compensator’s perfor-mance is the routing resistance3. When considering the routing resistance between the reference node and the drivers, a compensator distributed locally in the layout is desirable.

In the RDAC, a distributed compensator would need to compensate for the resis-tance variation or the current variation in small groups of the waveform generators close to each other in the layout. The current approach4is used to find out the requirements of such a structure. The current drawn by a small group of wave-form generators are studied. The smallest possible group is a single wavewave-form generator, and therefore, the current drawn by it is studied.

Let the high voltage of the inverter be Vref, and the low voltage be ground. The

input to the inverter is bi if the waveform generator is in the R-2R ladder or thiif

the waveform generator is in the parallel resistance network. Then the current drawn from the high input of the inverter by the waveform generator can be expressed as (4.8) if it is a binary-weighted waveform generator or (4.9) if it is a thermometer-code waveform generator. Vp|n,binary,i(Din) is the voltage in the ith

node in the R-2R ladder, and Vp|n(Din) is the voltage at the positive or negative

output of the RDAC5.

Iwf g,binary= bi Vref −Vp|n,binary,i(Din) R (4.8) Iwf g,thermomter = thi Vref −Vp|n(Din) R (4.9)

The equations show that the current drawn from the reference node of every driver in the RDAC will be dependent on the full input code. Hence, all local compensators would need to have the same resolution as the RDAC itself. Some

3_{The routing in a VLSI-IC is done with metal stripes, which are not resistance-less and will have a}

length-dependent resistance. All the resistances and drivers used in the RDAC have an area. Hence, there will be a difference in the length of the metal stripes connecting all drivers. If the length difference is large, a significant resistance difference will be present. Such differences will lead to variations in the resistance between the common node to the resistance net.

4_{Studying the resistance is not as straightforward, but it will lead to the same results. The resistance}

seen from the reference node will contain the resistance of all other nodes, even if the input impedance of only one waveform generator is studied

5_{The output voltage of the RDAC must be dependent on the full input code, D}

in; otherwise, the

RDAC would be a non-functioning DAC. The dependency of the full input code in the R-2R ladder nodes is harder to see, but the resistances between the ground to the right and the output voltage node to the left form a voltage divider for all nodes. Hence the voltages in between the resistances must depend on the full input code, Din.

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0 512 1024 1536 2048 2560 3072 3584 Input code[D _in] 3 4 5 6 7 8 9 10 11 12 Static current[mA] I_RDAC I_Comp I_RDAC + I_Comp

Figure 4.4:The current drawn from the supply network by the RDAC and the parallel RDAC in a static simulation is plotted.

problems with such a solution are the number of control signals needed, layout area, and generation of the control signals. In conclusion, local compensation is not practical to implement.

4.5 Results

The results from simulations with the RDAC and the parallel RDAC are presented in section 4.5. The section is split into a short introduction showing the current drawn by the RDAC and the parallel RDAC from a static simulation. In the remaining part of the section, results from dynamic simulation with single-tone, two-tone and wideband signal tests are presented.

4.5.1 Static simulation

A static simulation is presented to show the functionality of the RDAC and the compensating parallel RDAC together. The testbench in the EDA-simulator con-sists of one resistive network for each RDAC and the last stage drivers connected to the power supply network. The power supply consists of an ideal voltage source. The simulated static current from the RDAC and the parallel RDAC are plotted in Figure 4.4. Summing up, the two simulated currents gives an average current of 11.02 mA over all input codes. The difference between the maximum and minimum total current is 0.045 mA or 0.41 % of the average current.

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4.5 Results 31 Table 4.1:SFDR values in dBc for the RDAC for different drivers.

Frequency[GHz] 0.5 1.5 2.5 3.5 4.5 5.5 X with comp. 75.45 72.58 71.39 61.91 68.12 66.09 X without comp. 69.14 69.25 69.52 66.07 64.98 64.74 Y with comp. 73.94 72.48 64.28 68.35 63.78 66.10 Y with comp.6 73.19 72.83 66.25 69.33 65.82 65.49 Y without comp. 70.54 70.80 63.80 69.41 66.15 65.32 Z with comp. 72.49 71.19 66.77 69.78 62.24 61.76 Z without comp. 72.42 71.25 68.39 70.44 62.90 63.07

4.5.2 Dynamic simulation

Different RDAC candidates are designed in the parallel thesis [2] with different drivers in the waveform generators. Some of the drivers are DriverX, DriverY, DriverZ. They are sized to have equal rise and fall time, but the speed of the drivers differs. The speed difference influences the parallel RDAC performance. SFDR, HD3, IM3, and ACPR are presented for the different drivers. The metrics are presented with and without the parallel RDAC connected to the main RDAC; in addition, a simulation is done with DriverY with the input mapping based on the static simulation of DriverY. All the simulations are run with a sampling frequency of 16 GHz.

Spurious free dynamic range

The SFDR values are presented in Table 4.1. Common for all drivers is the reduced SFDR value for an increased frequency of the test tone. In the simulation with DriverX and DriverY, the SFDR value is increased when the parallel RDAC is connected. For DriverZ, no such enhancement of the SDFR can be seen; instead, degradation of the results can be seen.

Harmonic distortion

The HD3values are presented in Table 4.2, and they are in line with the SFDR results. An enhancement from the compensation is present by all drivers for a low input frequency. For DriverX the performance enhancement is present over all frequencies, but it is relatively small.

Third-order intermodulation product

The IM3results are presented in Table 4.3, and they show a similar pattern as the HD3and the SFDR values. However, the performance degradation at higher frequencies is more substantial compared to the single-tone test metrics.

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Table 4.2:HD3values in dBc for the RDAC for different drivers. Frequency[GHz] 0.5 1.5 2.5 3.5 4.5 5.5 X with comp. 78.44 72.58 71.39 61.22 62.75 65.56 X without comp. 69.14 69.25 69.52 60.59 61.07 63.11 Y with comp. 79.90 72.72 64.27 60.97 60.33 62.35 Y with comp.6 80.48 72.98 66.25 61.65 61.30 60.80 Y without comp. 70.53 70.80 63.80 61.85 61.87 63.10 Z with comp. 78.06 72.41 66.77 60.94 56.92 64.41 Z without comp. 72.47 71.24 68.39 60.91 66.29 68.17

Table 4.3:IM3-values in dBc for the RDAC with different drivers.

Frequency[GHz] 0.5 1.5 2.5 3.5 4.5 5.5 X with comp.-1 87.04 74.33 70.55 65.70 56.64 52.41 X with comp.+1 87.05 71.08 71.94 66.56 57.49 52.75 X without comp.-1 75.96 91.89 70.56 65.71 56.65 52.42 X without comp.+1 77.63 79.44 83.53 66.96 52.97 50.91 Y with comp.-1 89.28 77.30 74.17 57.33 52.72 50.30 Y with comp.+1 99.45 72.49 78.40 58.44 53.00 50.12 Y with comp.-16 93.52 79.04 71.21 60.95 53.79 50.80 Y with comp.+16 90.47 72.90 81.04 61.11 54.12 51.83 Y without comp.-1 75.27 83.63 78.08 55.69 51.53 49.12 Y without comp.+1 76.29 82.44 87.90 54.46 51.61 49.34 Z with comp.-1 83.74 78.42 71.54 65.42 53.99 53.30 Z with comp.+1 98.73 73.55 76.96 67.86 56.30 52.08 Z with comp.-1 73.13 85.01 73.62 68.60 53.31 51.36 Z with comp.+1 76.90 86.17 79.94 68.32 54.82 50.77

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4.5 Results 33 Table 4.4:ACPR-values in dBc for the RDAC with different drivers.

Center frequency[GHz] 1.0 2.0 3.0 4.0 5.0 6.0 X with comp.-1 76.71 72.38 69.83 71.85 70.90 71.29 X with comp.+1 74.92 72.55 69.21 70.20 70.77 70.76 X without comp.-1 76.81 75.33 73.48 74.18 73.00 72.62 X without comp.+1 75.59 74.67 74.18 72.50 73.06 72.79 Y with comp.-1 75.82 72.88 71.23 73.05 71.93 72.28 Y with comp.+1 74.77 73.05 70.41 71.31 72.01 72.28 Y with comp.-16 75.81 72.88 71.24 73.06 71.95 72.29 Y with comp.+16 74.78 73.06 70.43 71.32 72.03 72.30 Y wihtout comp.-1 75.74 74.91 74.41 75.15 73.80 73.52 Y without comp.+1 74.94 74.63 74.58 73.46 73.92 74.36 Z with comp.-1 73.08 71.69 71.95 73.23 71.59 72.04 Z with comp.+1 72.89 72.16 70.42 71.48 72.28 72.68 Z without comp.-1 72.66 72.57 73.76 74.51 72.57 72.79 Z without comp.+1 72.65 72.95 72.84 72.90 73.48 73.95

Adjacent channel power ratio

The ACPR values are presented in Table 4.4, and they are not showing any en-hancement of the results similar to SFDR, Hd3, IM3simulations. The main issue is that the results are close to the achievable noise limit without the parallel RDAC connected.

Reference node voltage

The SFDR and HD3results show a problem with the compensation structure at higher frequencies. Voltage data for the reference node from the single-tone test are added. An additional data point at 50 MHz is observed in the simulation. The voltage in the reference node during the first 10 ns for 50 MHz, 1.5 GHz, and 5.5 GHz input frequency can be seen in Figure A.1, Figure A.2, and Figure A.3. They show how well the compensator stabilizes the reference node voltage. In the low-frequency case, the variation without the compensator is significantly larger than with the compensator. The difference between the compensated and uncompensated case is smaller in the 1.5 GHz simulation, and in the high-frequency simulation, the variation is, in fact, larger for the compensated case than the uncompensated.

6_{An input code mapping base on a static simulation is used in these tests instead of the theoretical}

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4.6 Summary

In chapter 4, a compensation structure was introduced. It was also presented why it will be unfeasible to distribute the compensation structure. A parallel RDAC with the same resolution as the useful RDAC was chosen for the compensation in the simulations, and an input code mapping for the parallel RDAC was derived. At the end of the chapter, the results were presented. Firstly, a static simulation where the variation in the total current drawn by the RDAC is measured. Secondly, dynamic simulations where a limitation of the parallel RDAC solution can be seen both in stabilizing the reference voltage and enhancing DAC linearity.

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5

Digital predistortion

The second technique studied in this thesis that is used for reducing the non-linearity of an RDAC is digital predistortion. DPD is introduced in chapter 5, where the non-linearity models used in this thesis and the estimation of those models with least-square-error estimation are presented. Normalized square error is introduced as a metric on the performance of a DPD-model. At the end of the chapter, the results are presented.

DPD is common to used in transmitter chains for non-linear PAs. The concept behind DPD is to design a digital system that dynamically distorts the input to the non-linear device. With distortion from the DPD included, the cascaded transfer function of the pre-distorter and the non-linear unit should be linear. Figure 5.1 shows a block diagram of the concept. x[n] is the input signal, xDP D[n] is the

predistorted signal, and y(t) is the output from the RDAC, which should be linear with respect to x[n]. Previous studies [18, 19, 5] have targeted PAs, but lately, DPD has been used for compensating the non-linearities of a DAC [4].

DPD RDAC

x[n] xDP D[n] y(t)

Figure 5.1:Block diagram of the signal path in an RDAC with DPD, x[n] is the input signal, xDP D[n] is the digital predistorted signal, and y(t) is the

output signal.

Linearization of Resistive Digital-to-Analog Converter for RF-Applications Using Compensator and Digital Predistortion

Master of Science Thesis in Electrical Engineering

Department of Electrical Engineering, Linköping University, 2021