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Zigbee Data Packager

Project Team : -

Marwa Mekki & Seray Bundu

(2)

What is Zigbee?

 Wireless Personal Area Network

(WPAN) that is a ”superset” of IEEE 802.15.4 specification

 IEEE specifies the PHYsical and Media Access Control (MAC) layers

 Zigbee defines:- network, security and

application layers atop the PHY and

(3)

Zigbee application spheres

 Technology that ranges from

 sensor networks

 industrial monitoring and control

 home automation

 medical and automotive solutions etc.

With low data levels that can be transmitted

from ranges 10 – 70m are possible.

(4)

Zigbee & ieee 802.15.4 overview

 The standard specifies (for use by the PHY &

MAC layers) the freqs:

868, 915 MHz & 2.4 GHz for communication

 PHY layer includes

 Receiver energy detection (ED)

 Link quality indication (LQI) and

 Clear channel assessment (CCA)

 MAC layer handles

 Network association and disassociation

(5)

Zigbee & ieee 802.15.4 overview

 The technology handles

 Inter-operability

 Conformance testing specifications

 Device discovery

 Network configuration and

 Supports the star, mesh(peer-to-peer) and cluster-tree (hybrid tree/mesh).

 The data will be transfered as packets with

maximum size of 128 bytes, enabling a maximum

payload of 104 bytes.

(6)

Zigbee & ieee 802.15.4 overview

 Frame types used in data transmission are:

Data frame

MAC

Sublayer

PHY

layer

Frame Control

(2)

Sequence Number

(1)

Add fields (4 to 20)

Data payload

(104)

FCS (2)

MHR MSDU MFR

Preamble Seq.

(4)

Start of frame Delim.

(1)

Frame length

(1)

MPDU

SHR PHR PSDU

PPDU

(7)

Zigbee & ieee 802.15.4 overview

 MAC command frame

MAC sublayer

PHY layer

Frame Control

(2)

Seq.

# (1) Add fields (4 to 20)

Comm type

(1)

Comm payload

(103)

FCS (2)

MHR MSDU MFR

Preamble

seq. (4) Start of frame delim (1)

Frame length

(1)

MPDU

SHR PHR PSDU

PPDU

(8)

Zigbee & ieee 802.15.4 overview

 Beacon frame

MAC sublayer

PHY layer

Frame Control

(2)

Seq.

# (1) Add fields (4 to 10)

Superframe Specification

(2)

GTS fields (23)

Pending Add fields

(57)

Beacon payload

(32)

FCS (2)

MHR MSDU MFR

Preamble

seq. (4) Start of frame delim (1)

Frame length

(1)

PSDU

SHR PHR MPDU

PPDU

(9)

Zigbee & ieee 802.15.4 overview

 Acknowledge frame

MAC sublayer

PHY layer

Frame Control

(2)

Seq

# (1) FCS (2)

MHR MFR

Preamble sequence

(4)

Start of frame delim (1)

Frame length

(1)

MPDU

SHR PHR PSDU

PPDU

(10)

Module Design

 Interfaces

Clk Reset

W_E Request Addr Ack Data

Module µP

Base –

band

module

(11)

Module Design

 For the 4 data types written to the RAM by the µP,

D a T a T y p

S I z e of

a d d

S I z e of P a y

Si z e of G T S

fi el

Si z e of p e n d a d d

P re a m bl e s e q u e n

” ” ” St

ar t of

fr a m e d el i m

Fr a m e C o n t r

” Fr a m e

L e n g th

D a ta

s e q u e n c

C o m m a n d T y p

S u p er

fr a m e S p e

” G

T S

fi el

d s

P e n di n g

a d d

fi el

A d dr

e s s In fo

P a y L o a d

R e g I S T E r

(12)

Module Design

 Register

Clk

En_Reg qout Data

Reset

Ram

Reg µP

Add G

Control

CRC 3 2

Register

(13)

Module Design

 Address decoder

Clk

En En_Reg Addr

Ram

Reg µP

Add G

Control

CRC 3 2

Add

Dec

(14)

Module Design

 Controller

clk en_mux ack en_crc

Request sel, add

reset en_add_gen, init_add_gen start reset_crc

frame reset reg, add_gen

Ram

Reg µP

Add G

Control

CRC 3 2

Controller

(15)

Module Design

 Address generator

clk reset add en

init gen_ack frame_type gen_out

Ram

Reg µP

Add G

Control

CRC 3 2

Data Type

Size of Address Info

Size of payload

Size of GTS fileds

Size of Pending Add

(16)

Module Design

 Multiplexer

8-bit addr/data

8-bit o/p 8-bit addr/data

Control switch

Ram

Reg µP

Add G

Control

CRC 3 2

(17)

Module Design

 CRC

G(x) = x16 + x12 + x5 + 1 and parallel LFSR

clk

en o/p high Initialize o/p low data_in

CRC

computer

(18)

Module Design

Data flow

μP RAM

Reg Add

Dec

MUX 1

Add Gen

Controller

MUX 2

(19)

Results

From synthesis: -

Devices

Area

Max.

Freq (MHz)

# of slices

(768)

# of Slice FF

(1536)

# of 4 input LUT

(1536)

# of IO blocks

(124)

# of block RAMs (4)

RAM - - - 26 1 -

Add Decoder 2 1 3 10 - -

Register 9 16 8 18 - 657.46

MUX 1 - - 8 25 - -

Add Generator 225 120 418 22 - 117.85

MUX 2 - - 8 25 - -

CRC Generator 13 16 22 26 - 397.14

(20)

Questions ?

Questions???

References

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