Multi-Path Dierential Delay Line based Time-to-Digital Converter for ADPLL

Multi-Path Differential Delay Line based Time-to-Digital Converter for ADPLL

XIAOLONG CHEN

Master of Science Thesis Stockholm, Sweden 2013

KTH Information and

Communication Technology

Multi-Path Differential Delay Line based Time-to-Digital Converter for ADPLL

XIAOLONG CHEN

Stockholm 2013

School of Information and Communication Techbology Kungliga Tekniska H¨ ogskolan

TRITA-ICT-EX-2013:26

Abstract

All digital phase-locked loops (ADPLLs) play an important role in contem- porary applications such as Bluetooth, GSM, WCDAM and WiFi. A time- to-digital converter (TDC) is the critical part in the ADPLL, usually the dominant quantization noise contributor. The quantization noise is caused by the finite resolution of the TDC. Thus, a high resolution TDC with easy implementation (digital-friendly) feature is desired for the ADPLL.

After the investigation of different existing TDC topologies, an improved TDC based on a multi-path differential delay line is proposed and designed in 65-nm CMOS process. The proposed TDC utilizes the minimal-delay inverter as the delay element and a sense amplifier flip-flop as the compara- tor, which demonstrates high resolution and simple implementation.

The TDC contains 60 delay stages and was post-layout simulated with a

25-M Hz reference clock and a 4.06-GHz oscillator clock. The power con-

sumption is 1.215-mW from a 1.2-V supply with power saving enabled. The

DNL and INL are lower than 0.25 LSB. The typical resolution is around

9-ps, which meet the application spec. The TDC core layout has an area of

201.5 × 41.5 µm ² .

Acknowledgements

The M.Sc. study in Kungliga Tekniska H¨ ogskolan is a special time for me, mixed with pressure, enjoyment and happiness. It is also a memorable and colorful experience to study in Sweden. It would be hard for me to reach this stage without the support of others.

First and foremost, I would like to extend my sincere thanks to my M.Sc.

thesis supervisor, Dr. Jian Chen for guiding me for the overall research plan, sharing his great knowledge and experience in IC design, providing me with good suggestions for research and reviewing manuscripts.

Thanks are in order to Catena Wireless Electronics AB for providing this opportunity. I would like to thank Paul Stephansson for his valuable dis- cussions and suggestions. I would also like to express my gratitude to Jan Rapp, Mats Carlsson and many other people for their generous support during the my thesis work at Catena.

My thanks are also to the examiner and opponent of my M.Sc. defense committee for their insightful questions and invaluable time, Prof. Lirong Zheng and Xiaolin Zhao. My classmates in the System-on-Chip Design pro- gram also have provided wonderful ideas and friendship. I am also thankful to Sijia Hao for her patiently support.

Lastly, but not the least, my deep appreciation goes to my parents, who have given me the love, support and freedom to undertake many adventures.

There are too many others I want to thank as well. To my extended family

and friends who have supported me spiritually and emotionally, I want to

sincerely say thank you.

Contents

List of Figures vi

List of Tables xii

1 Introduction 1

1.1 Motivation . . . . 1

1.2 Objectives . . . . 2

1.3 Primary Contributions . . . . 2

1.4 Thesis Organization . . . . 3

2 ADPLL System and TDC Topology 4 2.1 ADPLL System . . . . 4

2.2 TDC in Phase Detection Block . . . . 5

2.3 TDC Performance for ADPLL . . . . 7

2.4 TDC Topology . . . . 7

2.4.1 Delay Chain Architecture . . . . 8

2.4.2 Delay Ring Architecture . . . . 8

2.4.3 Oscillator-Based Architecture . . . . 9

2.4.4 Gated Oscillator Architecture . . . . 10

2.4.5 Sub-Gate-Delay Spacing Delay Chain Architecture . . . . 11

2.4.6 Coarse-Fine Architecture . . . . 12

2.4.7 Vernier Delay Chain Architecture . . . . 13

2.4.8 Vernier Delay Ring Architecture . . . . 14

2.4.9 DCO-Based Vernier Architecture . . . . 15

2.4.10 Pulse Shrinking Ring Architecture . . . . 15

2.4.11 Comparison . . . . 16

CONTENTS

2.5 Summary . . . . 18

3 Vernier TDCs 19 3.1 General Description for Vernier Technology . . . . 19

3.2 DCO-Based Vernier TDC . . . . 21

3.2.1 Pre-Logic Block . . . . 21

3.2.2 DCOs and Calibration Block . . . . 21

3.2.3 Catching-up Detection Block . . . . 24

3.2.4 Counter . . . . 25

3.2.5 Output Logic and Control Block . . . . 25

3.2.6 Behavior Level Simulation . . . . 26

3.3 Vernier Delay Ring TDC . . . . 27

3.3.1 Vernier Delay Ring Block . . . . 27

3.3.2 Catch-up Detection Block . . . . 29

3.3.3 Behavior Level Simulation . . . . 29

3.4 Comparison of Two Architectures . . . . 30

3.5 Further Investigation of Vernier Delay Ring TDC . . . . 31

3.5.1 Delay Element . . . . 31

3.5.2 Edge Arbiter . . . . 33

3.5.3 Control Block for Delay Elements . . . . 38

3.5.4 Blocks Integration . . . . 40

3.6 Summary . . . . 41

4 Multi-Path Differential Delay Line TDC 43 4.1 Architecture . . . . 43

4.2 Schematic Design . . . . 45

4.2.1 Specification . . . . 45

4.2.2 Delay Element . . . . 45

4.2.2.1 Schematic Design of Delay Element . . . . 45

4.2.2.2 Sense-Amplifier-Based Flip-flop . . . . 52

4.2.2.3 Delay Stage . . . . 55

4.2.3 Edge Aligner . . . . 55

4.2.4 Power Saving Block . . . . 59

4.2.5 Small Delay Generation Block . . . . 63

CONTENTS

4.2.6 Read-out Block . . . . 66

4.2.7 Blocks Integration . . . . 69

4.2.8 Power Consumptions . . . . 70

4.2.9 TDC Linearity . . . . 74

4.3 Layout Design . . . . 75

4.3.1 Layout of Edge Aligner . . . . 75

4.3.2 Layout of Power Saving Block . . . . 81

4.3.3 Layout of Small Delay Generation Block . . . . 83

4.3.4 Layout of Delay Element . . . . 84

4.3.5 Layout of SAFF . . . . 91

4.3.6 Layout of Delay Stage . . . . 92

4.3.7 Layout of Differential Delay Line TDC . . . . 98

4.3.8 Power Consumptions . . . 102

4.3.9 TDC Linearity . . . 104

4.4 Summary . . . 107

5 Conclusion and Future Work 109

Bibliography 111

List of Figures

2.1 Block diagram of ADPLL (from (1)) . . . . 5

2.2 General block diagram of phase detection block (from (1)) . . . . 5

2.3 General operation principles of TDC (from (2)) . . . . 6

2.4 TDC fractional phase error estimation (from (3)) . . . . 6

2.5 Linear s-domain model with noise sources (from (3)) . . . . 7

2.6 Delay chain architecture . . . . 8

2.7 Delay ring architecture . . . . 9

2.8 Oscillator-based architecture . . . . 10

2.9 Gated oscillator architecture . . . . 11

2.10 Sub-gate-delay spacing delay chain architecture . . . . 12

2.11 Coarse-fine architecture . . . . 13

2.12 Vernier delay chain architecture . . . . 13

2.13 Vernier delay ring architecture . . . . 14

2.14 DCO-based vernier architecture . . . . 15

2.15 Pulse shrinking ring architecture . . . . 16

3.1 Sequence diagram of two signals with different frequencies . . . . 19

3.2 Block diagram of DCO-based Vernier TDC . . . . 21

3.3 Sequence diagrams of pre-logic block in DCO-based Vernier TDC . . . . 22

3.4 DCO topology of DCO-based Vernier TDC . . . . 22

3.5 Demonstration of connection wires after automatically PAR . . . . 22

3.6 DCO topology of DCO-based Vernier TDC with marked numbers . . . . 23

3.7 Demonstration of sorted periods for slow and fast DCOs . . . . 24

3.8 Schematic of a soft-edged flip-flop (from (4)) . . . . 25

LIST OF FIGURES

3.9 Sequence diagram of output logic and control block in DCO-based Vernier

TDC . . . . 25

3.10 ModelSim SE simulation results for DCO-based Vernier TDC . . . . 26

3.11 Block diagram of Vernier delay ring TDC . . . . 27

3.12 Topology of Vernier delay ring block . . . . 27

3.13 Working principle of Vernier delay ring block . . . . 28

3.14 Sequence diagram of Vernier delay ring block for demonstration . . . . . 28

3.15 ModelSim SE simulation results for Vernier delay ring TDC . . . . 29

3.16 Symbol and schematic of voltage-controlled NAND delay element . . . . 32

3.17 Demonstration of propagation delay, rising / falling delay of inverter and transition times . . . . 32

3.18 Comparison for different connections of voltage-controlled NAND delay element . . . . 33

3.19 Block diagram of rising and falling edge arbiters . . . . 34

3.20 Symbols, schematics and sequence diagrams of rising and falling edge detectors . . . . 34

3.21 Symbol and schematic of pulse arbiter . . . . 36

3.22 Definition of measurement time for arbiter . . . . 37

3.23 Measurement time in different conditions for edge arbiter . . . . 37

3.24 Measurement time of 1-ps interval using Monte-Carlo corner for process variation . . . . 38

3.25 Symbol and schematic of digital-controlled current mirror . . . . 39

3.26 Symbol and inter connection of Vernier delay stage . . . . 40

3.27 Block diagram of Vernier delay ring and catch-up detection blocks . . . 41

3.28 Transient simulation results of Vernier delay ring and catch-up detection blocks . . . . 42

4.1 Differential delay line TDC architecture . . . . 44

4.2 Sequence diagram of differential delay line TDC . . . . 44

4.3 Output of flip-flops from differential delay line TDC . . . . 45

4.4 Two different kinds of delay element topology . . . . 46

4.5 Connections among delay elements to form the delay line . . . . 46

LIST OF FIGURES

4.6 Transient outputs for a series of delay elements using separating input

topology . . . . 47

4.7 Transient outputs for a series of delay elements using two parallel invert- ers topology . . . . 48

4.8 Propagation delays by using different delay element topologies . . . . . 48

4.9 Symbol and schematic of a delay element for delay line . . . . 49

4.10 Connections of delay elements in differential delay line . . . . 49

4.11 Transient outputs from first five and fifteenth delay element couples . . 50

4.12 Propagation delays of differential delay line . . . . 51

4.13 Propagation delay of delay element with capacitor load from 0 to 10-f F 51 4.14 Propagation delay of delay element with supply voltage from 1.08-V to 1.32-V . . . . 52

4.15 Schematic of SAFF (from (5)) . . . . 53

4.16 Block diagram of a conventional SR latch for SAFF . . . . 53

4.17 Definitions for SAFF metastability measurement . . . . 54

4.18 Metastability curve of SAFF . . . . 55

4.19 Symbol and inter connections of a delay stage . . . . 56

4.20 Block diagram of edge aligner . . . . 56

4.21 Schematic of a custom NAND gate for edge aligner . . . . 56

4.22 Difference of two output edges as a function of two input edges difference for edge aligner . . . . 57

4.23 Transient simulation results of edge aligner . . . . 58

4.24 Edge difference, delay difference and half period difference of edge aligner using Monte-Carlo corner for process & mismatch variation (custom de- sign) . . . . 58

4.25 Edge difference, delay difference and half period difference of edge aligner using Monte-Carlo corner for process & mismatch variation (standard cell) 59 4.26 Symbol and block diagram of power saving block . . . . 60

4.27 Sequence diagram and some definitions for power saving block . . . . 61

4.28 Symbols and schematics of a delay buffer and a drive buffer for power saving block . . . . 61

4.29 Simulation of power saving block using Monte-Carlo corner for process

& mismatch variation . . . . 62

LIST OF FIGURES

4.30 Symbols and schematics of drive inverters for small delay generation block 64

4.31 Topology of small delay generation block . . . . 64

4.32 Propagation delays of differential delay line . . . . 65

4.33 Topology of small delay generation block (improved) . . . . 65

4.34 Symbols and schematics of a transit gate for small delay generation block 66 4.35 Sequence diagram and transient simulation results of small delay gener- ation block . . . . 66

4.36 Schematic of small delay generation block . . . . 67

4.37 Block diagram of input block for differential delay line TDC . . . . 69

4.38 Sequence diagram of input block for differential delay line TDC . . . . . 69

4.39 Block diagram of differential delay line for differential delay line TDC . 70 4.40 Transient simulation results of differential delay line TDC . . . . 70

4.41 Currents of different blocks for differential delay line TDC in power-save- on mode under typical conditions . . . . 71

4.42 Total currents of different supply voltages for differential delay line TDC in power-save-on mode under typical corner . . . . 72

4.43 Currents of different blocks for differential delay line TDC in power-save- off mode under typical conditions . . . . 73

4.44 Currents of different blocks for differential delay line TDC in shut-down mode under typical conditions . . . . 73

4.45 Mean and SD values of propagation delays for differential delay line TDC under Monte-Carlo corner for process & mismatch variation . . . . 74

4.46 Mean and SD values of typical rising and falling times for differential delay line TDC under Monte-Carlo corner for process & mismatch variation 74 4.47 TDC transfer function . . . . 75

4.48 Measurement results for one half period of 4.06-GHz (123.15-ps) . . . . 76

4.49 DNL and INL for schematic design . . . . 76

4.50 Layout of a costume NAND . . . . 77

4.51 Annotations for layers in the layout design . . . . 77

4.52 Layout of edge aligner . . . . 78

4.53 Post-layout transient simulation results of edge aligner . . . . 79 4.54 Difference of two output edges as a function of two input edges difference

for edge aligner in post-layout simulation after parasitic RC extraction . 80

LIST OF FIGURES

4.55 Edge difference, delay difference and half-period difference of edge aligner using Monte-Carlo corner for process & mismatch variation after para-

sitic RC extraction . . . . 81

4.56 Layout of delay buffer for power saving block . . . . 81

4.57 Layout of drive buffer for power saving block . . . . 82

4.58 Layout of power saving block . . . . 82

4.59 Post-layout simulation using Monte-Carlo corner for process & mismatch variation after parasitic RC extraction . . . . 83

4.60 Layout of switches with drive inverters for small delay generation block 85 4.61 Layout of small delay generation part for small delay generation block . 86 4.62 Layouts of two kinds of drive inverters for small delay generation block . 86 4.63 Transient post-layout simulation of small delay generation block after parasitic RC extraction . . . . 87

4.64 Layout of a single inverter for delay element . . . . 88

4.65 Block diagram of modeling the resistance from power line for differential delay line . . . . 89

4.66 Propagation delays with power line resistors and decoupling capacitors for differential delay line TDC . . . . 89

4.67 Layout of delay element . . . . 90

4.68 Layout of SA for SAFF . . . . 91

4.69 Layout of symmetric SR latch for SAFF . . . . 92

4.70 Layout of SAFF . . . . 93

4.71 Metastability curve of SAFF after parasitic RC extraction . . . . 94

4.72 Symbol and inter connections of a modified delay stage . . . . 94

4.73 Block diagram of modified differential delay line . . . . 95

4.74 Layout of one delay stage . . . . 96

4.75 Propagation delays from post-layout simulation for the delay stage . . . 98

4.76 Different kinds of drawing source and drain connections in an inverter for delay stage . . . . 99

4.77 Propagation delays from improved post-layout simulation for delay stage 99 4.78 Improved layout of one delay stage . . . 100

4.79 Layout of input block . . . 101

4.80 Layout of differential delay line TDC . . . 102

LIST OF FIGURES

4.81 Transient post-layout simulation results of differential delay line TDC after parasitic RC extraction . . . 102 4.82 Currents of different blocks for differential delay line TDC in power-save-

on mode under typical conditions after parasitic RC extraction . . . 103 4.83 Total currents of different supply voltages for differential delay line TDC

in power-save-on mode under typical corner after parasitic RC extraction 103 4.84 Currents of different blocks for differential delay line TDC in power-save-

off mode under typical conditions after parasitic RC extraction . . . 105 4.85 Currents of different blocks for differential delay line TDC in shut-down

mode under typical conditions after parasitic RC extraction . . . 105 4.86 Mean and SD values of propagation delays for differential delay line

TDC under Monte-Carlo corner for process & mismatch variation after parasitic RC extraction . . . 106 4.87 Mean and SD values of typical rising and falling times for differential

delay line TDC under Monte-Carlo corner for process & mismatch vari- ation after parasitic RC extraction . . . 106 4.88 TDC transfer function after parasitic RC extraction . . . 107 4.89 Measurement results for one half period of 4.06-GHz (123.15-ps) after

parasitic RC extraction . . . 108

4.90 DNL and INL after parasitic RC extraction . . . 108

List of Tables

3.1 Design parameters of voltage-controlled NAND delay element . . . . 31

3.2 Design parameters of standard cells in rising and falling edge detectors . 34 3.3 Design parameters of pulse arbiter . . . . 36

3.4 Design parameters of control block . . . . 39

3.5 The relationship between digital control code and propagation delay of NAND (Typical codes for delays between 60-ps and 70-ps) . . . . 40

4.1 Design parameters of delay element . . . . 50

4.2 Design parameters of SAFF . . . . 54

4.3 Design parameters of custom NAND for edge aligner . . . . 57

4.4 General performance of edge aligner under different corners, voltages and temperatures . . . . 59

4.5 Design parameters of standard cells for power saving block . . . . 60

4.6 Design parameters of delay buffer and drive buffer for power saving block 62 4.7 Simulation results of power saving block under different corners, tem- peratures and supply voltages . . . . 63

4.8 Design parameters of small delay generation block . . . . 67

4.9 Differential delay line TDC power consumptions and typical propagation delays in power-save-on mode under different corners, temperatures and supply voltages . . . . 72

4.10 General performance of edge aligner in post-layout simulation under dif-

ferent corners, voltages and temperatures after parasitic RC extraction . 80

4.11 Post-layout simulation results of power saving block under different cor-

ners, temperatures and supply voltages after parasitic RC extraction . . 84

LIST OF TABLES

4.12 Extracted capacitance values among different nodes of the inverter for a delay stage . . . . 97 4.13 Differential delay line TDC power consumptions and typical propagation

delays in power-save-on mode under different corners, temperatures and

supply voltages after parasitic RC extraction . . . 104

Chapter 1

Introduction

1.1 Motivation

In contemporary communication systems, one of the most challenging tasks is the frequency synthesizer design, which needs to meet a serial of strict requirements and keep the power and area consumptions low. Phase locked loop (PLL) is one of the most common methods of frequency synthesis for contemporary wireless transceivers.

Conventionally, analog-intensive charge-pump PLLs are mainly used in such systems, which consume much area and power. Analog-intensive design encounters difficulties when CMOS processes scale due to limited voltage headroom.

In contrast, all-digital PLLs (ADPLLs), which has been developed quickly in recent years (6)(7)(8), demonstrates many desired features such as performance improvements with process scaling, standard cell implementation for control blocks and making use of DSP techniques. As a result, there is a huge interest in the design of ADPLLs for contemporary communication systems. It has been successfully adopted in commercial products for GSM (9)(10), Bluetooth (11) and WCDMA (12).

In ADPLL systems, a phase detector is of great importance. It generates the phase

difference between a clean reference clock and a noisy oscillator clock. The phase

difference control the frequency of the oscillator until it is locked. As a phase detection

method, a time-to-digital converter (TDC) is one of the most critical blocks in terms of

phase noise contribution. In conclusion, during the ADPLL design process, much more

attention should be paid to the TDC design not only to reduce the noise contribution

to total noise, but also to be low area and power consumptions.

1.2 Objectives

1.2 Objectives

This thesis work is a sub-project of a low noise ADPLL design in Catena Wireless Elec- tronics AB. A high resolution TDC with a resolution at least less than 10-ps is required by the maximum phase noise tolerance of the ADPLL for the working frequency from 3.8-GHz to 4.05-GHz. The objective of this thesis is to design and implement the required TDC circuit and layout for the ADPLL design.

In order to reach the objectives, the background of ADPLLs and TDCs are studied.

Secondly, different kinds of TDC topologies are analyzed to check if they meet the requirements. After that, we can obtain some promising topologies for future inves- tigations. Thirdly, the chosen TDC will implemented using a 65-nm CMOS process.

The layout and post-layout simulation are also provided.

1.3 Primary Contributions

In regard to the high resolution time-to-digital converter, the primary contributions of this thesis are:

• General investigation of different kinds of TDC topologies

• Investigation of a differential delay line topology with multi-path delay elements cross connected in two lines

• Investigation of a small delay generation block for the differential delay line to reduce the number of propagated elements before propagation delay becomes stable

• Reduction of propagation delay with a custom layout design for the inverter in delay element by reducing parasitic capacitance between source and drain

• Realization of a 60-stage TDC with 9-ps resolution and around 201.5 × 41.5 µm ²

area cost

1.4 Thesis Organization

1.4 Thesis Organization

• Chapter 1. Introduction

The motivation, objective and primary contributions of this thesis are described in this chapter.

• Chapter 2. ADPLL System and TDC Topology

A general description of ADPLLs and different typical TDC topologies are intro- duced. In addition, a comparison of topologies is carried out.

• Chapter 3. Verner TDCs

This chapter introduces the behavior level simulations of two different Vernier technologies. After comparison, the Vernier delay ring technology is taken for a further investigation.

• Chapter 4. Multi-Path Differential Delay Line TDC

The schematic and layout designs of multi-path differential delay line TDC are developed. With improvements, post-layout simulations show that this design meets the requirements.

• Chapter 5. Conclusion and Future Work

This chapter summarizes the overall work and suggests some recommendations

for the future work.

Chapter 2

ADPLL System and TDC Topology

All digital phase-locked loop (ADPLL) system is widely used in modern communication systems like GSM, WIMAX (13), Bluetooth. One of the ADPLL sub-blocks, time- to-digital convertor (TDC), plays an important role in the noise contribution to the ADPLL system. In this chapter, we will investigate different kinds of TDC topologies and discuss suitable topologies for this project.

2.1 ADPLL System

All digital phase-locked loop is one variation of phase-locked loops (PLLs). In general, the PLL contains four basic elements, phase detector (PD), low-pass filter, variable frequency oscillator and feedback path. In ADPLL, all blocks are defined as digital at the input / output level. Although the digitally controlled oscillator (DCO) is analog in its internal, which nature does not propagate beyond its boundaries, its input and output are still digital. Thus, the control part of the DCO can be implemented as a fully digital circuit.

The block diagram of an ADPLL is illustrated in Figure 2.1. At the beginning, the

frequency command word (FCW) should be determined to obtain a certain frequency

of the ADPLL output. The PD block generates a signal representing the difference in

phase between reference phase and variable phase. The phase error (PHE) is processed

2.2 TDC in Phase Detection Block

DCO OTW FCW

FREF Phase and Frequency Control Logic

Variable Phase

Normalized DCO

f _R

K _DCO

∆f _v

Figure 2.1: Block diagram of ADPLL (from (1))

as the input of DCO, thereafter the DCO is used to perform digital-to-frequency con- version. Its output frequency is a function of the input oscillator tuning word (OTW).

2.2 TDC in Phase Detection Block

In PD block, there are three phase inputs, reference phase (R R [k]), variable phase (R V [k]) and fractional error correction ([k]). The PHE will be estimated from these inputs via following Equation (2.1)

φ ˆ _E [k] = R _R [k] − R _V [k] + [k]. (2.1)

+

- PR

+ FCW CKR

CKV FREF

CKV

CKR TDC&PF PHE

PV

Reference Phase

Fractional Error Correction

Variable Phase

Figure 2.2: General block diagram of phase detection block (from (1))

A general block diagram of phase detection block in Figure 2.2 illustrates the phase

detection mechanism mentioned above. There are three sub-blocks, phase reference

accumulator (PR), variable-phase accumulator (PV) and fractional error correction

(PF). The fractional delay difference () between the reference clock (FREF) and the

2.2 TDC in Phase Detection Block

next significant edge of the DCO clock (CKV) is measured by a time-to-digital converter (TDC).

T q

T out

T in

t _start t _stop

∆T start ∆T stop

Start Stop

t

t Reference

Signal

Figure 2.3: General operation principles of TDC (from (2))

Figure 2.3 describes the general operation principles of a TDC, as widely cited from Baron’s paper on the Vernier technique (2). In the figure, the input time interval,

T _in = t _stop − t _start , can be divided into a number of smaller time reference of T _q with a

quantization error, e _q . An estimate of T _in is then calculated by counting the number of T _q , T _out = N × T _q . ∆T _start and ∆T _stop are errors for the measurement in the beginning and at the end, such that e _q = ∆T _stop + ∆T _start . Then T _out = T _in − e _q .

∆t

∆t

ϕ

>0 ε=1−∆t

/T

FREF CKV

∆t

∆t

ϕ

<0 FREF

CKV

T

/2

(a) Positive phase error (b) Negative phase error

CKV FREF TDC ∆t

NORM

∆t

ε

Figure 2.4: TDC fractional phase error estimation (from (3))

Figure 2.4 depicts the detailed operation of PD. ∆t r is a quantized time between

the FREF sampling edge and the CKV rising edge while ∆t f is the one between the

FREF sampling edge and the CKV falling edge. Both CKV edges should be the nearest

one coming before FREF sampling edge. The raw digital output of the TDC should be

2.3 TDC Performance for ADPLL

normalized by the oscillator clock period (T _V ) as Equation (2.2) below.

[k] = 1 − ∆t _r /T _V (2.2)

It is also easy to get the half period of CKV by calculating the difference of ∆t r

and ∆t _f .

2.3 TDC Performance for ADPLL

Within the ADPLL system, the noise can be injected only in two places. The linear s-domain model with noise sources is illustrated in Figure 2.5. From the figure, we can see that one noise source is the TDC (φ n,T DC ) and the other is the oscillator (φ n,V ).

Due to the digital characteristics of ADPLL, the rest of the system does not contribute any noise.

Phase Detector Normalized DCO

K DCO

1 s Loop Filter

ϕ R'

ϕ n,TDC

ϕ E

ϕ n,V

ϕ V

∆ω V

K DCO

2π α *2π

N +

- 1

f /LSB R

Figure 2.5: Linear s-domain model with noise sources (from (3))

Noise from TDC and DCO should be maintained under a certain level to keep the noise of ADPLL within a reasonable range. The TDC noise is affected by its time resolution. In order to minimize the TDC phase noise, the improvement of the TDC time resolution is essential. Therefore, a target resolution is included as the TDC design requirement.

2.4 TDC Topology

In the following part, several kinds of state-of-the-art TDC topologies are briefly inves-

tigated and analyzed. The main method of measuring time in TDC is that comparing

the time interval with standard delays. For example, the interval can be compared

with a serial standard delays or a parallel different delays simultaneously. Based on

the compression result, evaluation circuit will generate an output for the interval. A

general description is summarized and Pros and Cons are also listed.

2.4 TDC Topology

2.4.1 Delay Chain Architecture

This is one of the basic architectures with delay elements by counting the number of sequential delays that occur within the testing period. In Figure 2.6, the period is the time between two rising-edges of start and stop signals. When the start signal comes, it propagates through delay elements. After the stop signal arrives, registers will sample values at each node to provide how many delay elements have been propagated through, which can be used to calculate the period between start and stop signals.

D Q D Q D

Q Start

Stop

Delay Elements

Out

Figure 2.6: Delay chain architecture

• Pros:

– It is easily implemented, e.g. by using buffer, FF / latch and simple read-out circuit.

– It can be low power.

• Cons:

– The resolution is limited by delay elements.

– A long delay chain is necessary for a wide dynamic range.

– Mismatch and accumulated jitter will create problems for a long delay chain.

(14)

2.4.2 Delay Ring Architecture

In order to solve the problem of limited dynamic range of the delay chain architecture,

2.4 TDC Topology

controlled by a logic part. In this architecture, the number of delay elements (inverters) should be odd to make sure that the logic values from counting nodes will change when the folded back signal passes through. The TDC output is generated by counting and summing the number of delay element transitions that occurred during the measuring period as shown in Figure 2.7.

Start

Stop Out

Delay

0 1

Counter Logic

Register Reset

Counter Counter

Mux Delay Delay

Figure 2.7: Delay ring architecture

• Pros:

– A short delay chain can provide a wide dynamic range by reusing of delay elements.

– The area consumption is much lower for a wide dynamic range.

– The integral non-linearity is better compared with delay chain architecture for a large input interval.

• Cons:

– Resolution is limited by delay elements.

– Counters work at a high frequency for a short ring.

– Mismatch and accumulated jitter will also create problems. (15) 2.4.3 Oscillator-Based Architecture

There is not much different between this architecture in Figure 2.8 and delay ring

architecture. The oscillator generates signals with different phases for counters all the

time. Among the testing window between the start and stop signals, the counters work

2.4 TDC Topology

like that in the delay ring architecture counting the number of phase changing. The number in total is summed and then sampled for output.

Start

Stop Out

Delay

Counter Logic

Register Enable

Counter Counter

Oscillator

Delay Delay

Figure 2.8: Oscillator-based architecture

• Pros:

– The dynamic range is wide.

– Mismatch error and quantization error can be improved by oversampling.

• Cons:

– Resolution is also limited by delay elements.

– The power consumption is high.

– Counters work at a high frequency (read-out circuit may be complicated).

(16)

2.4.4 Gated Oscillator Architecture

The main difference between the gated oscillator architecture and ring architecture is that the oscillator is gated with an enable signal, as shown in Figure 2.9, which will make the oscillator keep its state between two measurements.

• Pros:

– It introduces first-order noise-shaping by transferring the quantization error

to the next period.

2.4 TDC Topology

Start

Stop Out

Delay

Counter Logic

Register Enable

Counter Counter

Gated Oscillator

Delay Delay

Reset

Figure 2.9: Gated oscillator architecture

– The area consumption is lower for a wide dynamic range.

– Mismatch can be relaxed like a barrel shift.

– This architecture can be low power.

• Cons:

– Resolution is limited by delay elements (multi-path technique can be utilized to improve this).

– Counters work at a high frequency.

– To get a finer resolution, it may need a large number of delay stages and complicated ring-oscillators and read-out circuit. (17) (18)

2.4.5 Sub-Gate-Delay Spacing Delay Chain Architecture

Besides multi-path technique, another way to improve the resolution is to insert a gate- delay, such as a resistive divider, between the input and output of a delay element to create an intermediate signal within the range of the delay element, as illustrated in Figure 2.10. After the stop signal arrives, all registers will sample these values, which can be used to calculate the period between start and stop signals.

• Pros:

– The resolution can be improved.

2.4 TDC Topology

Start

Stop

Delay Elements

Out Figure 2.10: Sub-gate-delay spacing delay chain architecture

• Cons:

– This will increase the total size by adding additional elements (a ring archi- tecture can be utilized to reduce this problem).

– It will increase the complexity of the read-out circuits.

– Non-linear impedances of the delay elements will be introduced during the switching transients. (15)

2.4.6 Coarse-Fine Architecture

In general, the input time values can not be stored as its original forms or transformed to other formats without distortion or noise. In this architecture, time value is processed directly. As shown in Figure 2.11, firstly, a coarse TDC based circuits are used to get the time residue, which is the same as the quantization error of the coarse TDC. After amplified by a time amplifier (TA) and selected by the multiplexer, it is sent to the fine TDC for later measurement. The output is generated base on outputs from both coarse and fine TDCs.

• Pros:

– It can provide a high resolution.

• Cons:

– Complicated circuits consume a large area.

– A wide dynamic range will result in a large area.

2.4 TDC Topology

Start

Stop

Delay Elements

Out Arbiter Arbiter Arbiter Arbiter

Fine TDC

TA TA TA TA

Mux Coarse TDC

Figure 2.11: Coarse-fine architecture

– High power consumption due to a series of arbiters and TAs will work in parallel. (19)(20)

2.4.7 Vernier Delay Chain Architecture

The Vernier delay technique is used to improve the resolution by introducing the relative rate of transitions. The resolution is the slight difference between two standard delays as shown in Figure 2.12. After the stop signal catches up the start signal, the number of how many delay cells have been passed through will be used to calculate the interval between start and stop signals.

D Q D Q D

Q Start

Stop

Delay Elements

Delay2 Out Delay1

Figure 2.12: Vernier delay chain architecture

• Pros:

– This architecture has a high resolution.

2.4 TDC Topology

– Flip-flops can work in a low frequency.

• Cons:

– Long delay chain is needed for a wide dynamic range.

– Mismatch and accumulated jitter will create problems for a long delay chain.

(2)

2.4.8 Vernier Delay Ring Architecture

The principle of this architecture is nearly the same as that of delay ring architecture.

The end of each chain in the Vernier delay chain architecture is folded back to its beginning to increase the dynamic range without adding more delay elements like in Figure 2.13. The TDC output is generated by the evaluation logic.

Start

Stop

C o n tr ol & E va lu a tio n

Delay2 Delay1

Out

0 1

Counter

Arbiter Arbiter Arbiter

Counter

1 0

Figure 2.13: Vernier delay ring architecture

• Pros:

– This architecture has a high resolution.

– Flip-flop can work at a low frequency.

– Short delay chain can realize a wide dynamic range by reusing of delay elements.

– Mismatch can be relaxed like a barrel shift.

– The delay rings can work at a relative low frequency

• Cons:

– Complicated read-out and other logic circuits are necessary. (14)

2.4 TDC Topology

2.4.9 DCO-Based Vernier Architecture

The DCO-based Vernier architecture can be viewed as one-stage Vernier delay ring. The DCO consists of three inverting stages and its output frequency is controlled digitally.

As illustrated in Figure 2.14, the different frequencies from two DCOs are generated based on the systematic mismatch from automatic placed-and-routed. With the help of calibration circuit, it is possible to get a really low resolution (slightly different frequencies). Then the output is generated by coarse and fine counters. All these parts can be realized with digital standard cells without custom circuit or layout.

Start

Stop

C o n tr ol & E va lu a tio n

Fast DCO Slow DCO

Out Counter

Arbiter

Counter

Figure 2.14: DCO-based vernier architecture

• Pros:

– This architecture has a high resolution.

– It is synthesizable.

– The area consumption is low.

• Cons:

– Calibration circuit for DCOs is complicated.

– Counters work at a high frequency (read-out circuit may be complicated).

(4)

2.4.10 Pulse Shrinking Ring Architecture

Each pulse shrinking couple can shrink the input pulse with a fixed value, which is

realized by modifying the rising and falling times by using inverters with different drive

2.4 TDC Topology

strengths. In the multistage line, as shown in Figure 2.15, the counter counts the number of cycles that input pulse propagates through before the pulse width is zero.

The FFs measure the position where the width turns into zero. Later the time interval can be calculate by the number of shrinking coupes where the pulse passes through before it reduces into zero and the shrinking width.

Start

Stop

Logic Out

0 1

Counter

C on tr ol &E valu at ion

Figure 2.15: Pulse shrinking ring architecture

• Pros:

– This architecture has a high resolution.

• Cons:

– Pulse shrinking couple consumes much area.

– It needs digital correction circuits for output.

– There is a tradeoff among resolution, number of stages and quantization time.

– Noise will accumulate with the increase of input phase error. (21) 2.4.11 Comparison

According to the goal of this project, this design is s a target application in a low noise ADPLL system. The value of resolution is determined by the maximum phase noise tolerance of ADPLL, e.g. 20-ps for the worst case of wireless standards (22). We can also calculate the minimum measure range which should be lager than 131.6-ps from the minimum CKV frequency. In addition, this design should be easily implemented.

Frequency of CKV: 3.8-GHz − 4.05-GHz Resolution: < 10-ps

CMOS technology: 65-nm CMOS10LPe-RVT

2.4 TDC Topology

On high resolution and wide dynamic range sides, we will consider gated ring os- cillator TDC with multi-path, delay ring TDC with sub-gate-delay spacing technology, Vernier delay ring TDC, pulse shrinking TDC and DCO-based Vernier TDC.

Delay ring TDC with sub-gate-delay spacing technology consumes much area. Pulse shrinking TDC has a poor noise feature and a tradeoff among resolution, number of stages and quantization time. It can not be further improved such as by adding first- order noise-shaping feature or converting into gated topology.

Although DCO-based Vernier TDC is the only one that can be realized in the full digital domain, there is less fabrication supporting according to literatures. This topology should be carefully thought over.

The core block for multi-path gated ring oscillator TDC is complicated due to cascading the unrestricted connections of delay structures and introducing many delay stages, when a high resolution is necessary. The read out circuits is not so difficult, while the main problem for this part is that counters work at a high frequency. Additionally, it has good features like first-order noise-shaping.

Compared with gated ring oscillator TDC with multi-path, Vernier delay ring TDC has a much simpler core block. However, other logic circuits, such as evaluation logic, are a little bit more complicated. Although the first-order noise-shaping feature is not included, all its blocks can work at a relative low frequency. Attention should be paid on how to design two kinds of delay elements with slightly different delay for this topology.

For all ring topology, we have to fold its last output back to its beginning, which will introduce discontinuity between delay stages in layout design because the impossibility to draw the layout as a ring. It also will introduce un-symmetry in the layout. All of these topologies are complex.

In the view of short measurement time and easy implementation, if we can increase

the resolution of delay chain TDC, it will also be a good back-up topology. In addition,

since it is a line topology, we do not need to worry about discontinuity between delay

stages.

2.5 Summary

2.5 Summary

In this chapter, a general description of ADPLL is given. After mentioning the im- portance of TDC in ADPLLs, different typical TDC topologies are introduced and compared. In the following chapters, we will evaluate DCO-based Vernier TDC and Vernier delay ring TDC, mainly on their working principles and behaviors simulations.

Although these two topologies can archive a really high resolution (less than 5-ps) in cost of complexity, they will not benefit much from technology scaling process. Since easy implementation is also included in requirements, we will make some improvements in the delay chain topology, which also can benefit a lot from technology scaling process.

Due to its simple topology, it is more reliable than the other two.

Chapter 3

Vernier TDCs

In this chapter, a brief study of different kinds of Vernier technologies is carried out.

Among these general comparisons, information on detailed blocks and behavior level simulations, using Verilog HDL, is provided. Based on such information, a further investigation will be taken for one chosen Vernier architecture.

3.1 General Description for Vernier Technology

The example shown in Figure 3.1 gives a better understanding of Vernier technology.

There is a small interval between two rising edges from rectangle signals with different frequencies, Clock and Vernier. Assume the frequency of Clock is slightly lower than that of Vernier. As a result, if we let two signals continue being generated, the rising edge from Vernier will catch up the one from Clock. The time interval between them will become smaller and smaller while time passing.

T tot_CLK

Clock

Vernier

T tot_Vernier

Time Difference

Figure 3.1: Sequence diagram of two signals with different frequencies

After several cycles, the rising edge from signal Vernier will be firstly ahead of

the one from signal Clock (the time difference is not integral multiple of the time

3.1 General Description for Vernier Technology

difference between periods from two signals) or just overlap (the time difference is integral multiple of the time difference between periods from two signals), we are able to obtain the Equation 3.1

T _{dif f} = T _{tot CLK} − T tot V ernier + T _err , (3.1)

where T dif f is the small interval between two rising edges and T err is the small time interval between the first catching-up rising edge of Vernier and the one from Clock.

T _err is going to be equal to zero if overlapping happens. T _{tot CLK} and T tot V ernier are the total running times for the signal Clock and signal Vernier until catching-up or overlapping happening.

If the time difference is less than one period of signal Clock, it is sure that the numbers of periods passing for both signals are the same when the first catching-up or overlapping is happening. T err is neglectable when the time difference between Clock and Vernier periods, which can be also called resolution, is small enough. So we can use the Equation (3.2) to represent the T dif f in forms of periods and number of period.

T _{dif f} = N × T _Clock − N × T _{V ernier} + T err (3.2)

= N × (T _Clock − T _{V ernier} ) + T _err (3.3)

= N × Resolution + T err (3.4)

T _Clock and T _{V ernier} are period lengths for signal Clock and signal Vernier. N is the

number of cycles. In this way, we can measure the time difference by counting cycles.

The comparator for rising-edges is also important. It is not a good idea to use a con- ventional D-flip-flop here, because the set-up time and hold-on time for this D-flip-flop is much larger than the resolution of design requirement, and its metastability window is large too. If we use a conventional D-flip-flop and the interval is less than the hold-on time, the output might be a random value and it cannot detect the signal correctly.

For this reason, the comparator should be designed with the following features. The

set-up time should be smaller than required resolution. If the set-up or / and hold-on

time is / are not fulfilled, the output should be stable.

3.2 DCO-Based Vernier TDC

3.2 DCO-Based Vernier TDC

A brief description of the DCO-based Vernier architecture has been mentioned in prior Section 2.4.9. A detailed block diagram of DCO-based Vernier TDC is shown in Figure 3.2, which containing pre-logic, output logic and control, DCOs and calibration, counter and catch-up detection blocks. This architecture can be synthesized besides the pre- logic block. The DCO architecture here is the basic one like a ring of inverters. In the following sections, we will discuss each block individually.

Pre- Logic

Slow DCO

Fsat DCO Calibration

Counter

Catching-up Detection

Ou tpu t L ogi c &C o n tr ol

Out LEAD

LAG External Reset

First Signal

Last Signal

Sign

Reset Sign Out

Reset

Internal Reset Stop

First Signal

Figure 3.2: Block diagram of DCO-based Vernier TDC

3.2.1 Pre-Logic Block

Two control signals for DCOs and Sign-bit are generated from two input signals, LEAD and LAG. If LEAD signal comes first, then it will be transferred to the control signal for slow DCO while LAG signal will be transferred to the control signal for fast DCO and the Sign-bit is zero. By contrast, if LAG signal comes first, it will also be transferred to the control signal for slow DCO while LEAD signal will be transferred to the control signal for fast DCO and the Sign-bit is one. Sequence diagrams are shown in Figure 3.3. Additionally, the interval between two control signals will keep the same as that between two input signals.

3.2.2 DCOs and Calibration Block

The DCO topology is shown in Figure 3.4, containing several delay stages, while the

stage is made of several parallel tri-state inverters. Then we can control the output

frequency / period by turning on or off part of them.

3.2 DCO-Based Vernier TDC

RST LEAD LAG First Signal Last Signal SIGN_BIT

RST LEAD LAG First Signal Last Signal SIGN_BIT

(a)LEAD signal comes first (b)LAG signal comes first Figure 3.3: Sequence diagrams of pre-logic block in DCO-based Vernier TDC

Stage 1 Stage 2 Stage 3

Control Frequency Control

Out

Figure 3.4: DCO topology of DCO-based Vernier TDC

Architectures for both DCOs should be the same in order to get two DCOs with slight frequency difference. The mismatch from automatically placed and routed (PAR) is used to bring the delay difference between two DCOs. After the automatically PAR, the lengths of connection wires are different as shown in Figure 3.5, which will bring different parasitic for each delay stage. Then we can calibrate them to get different delays through calibration clock. (23)

Figure 3.5: Demonstration of connection wires after automatically PAR

3.2 DCO-Based Vernier TDC

Stage 1 Stage 2 Stage 3

Control Frequency Control

Out

1

2

8

9

15

16

17

23

Figure 3.6: DCO topology of DCO-based Vernier TDC with marked numbers

In order to show the calibration procedure clearly, each delay cell (tri-state inverter) is marked with a number as shown in Figure 3.6. Take the fast DCO for example.

Firstly, only one inverter is turned off at one time (e.g. Inverter 1). Secondly, we need to measure the output period for the fast DCO at this situation. Here, slow DCO with a constant statue (e.g. three fixed inverters are turn off to make sure its frequency is lower) is introduced. If we let two DCOs start simultaneously with rising-edges and count the number of cycles from slow DCO when rising-edge from fast DCO catches up the other one at the first time, we can calculate the period of fast DCO via Equation 3.5 (T _{F ast Bx} , Bx here means inverter x is turn off) in forms of period of slow DCO (T _Slow ) and the number of cycles (N ),

T _{F ast Bx} = (N/(N + 1)) × T _Slow . (3.5)

Thirdly, this inverter from fast DCO will be turned on and another inverter will be turned off (e.g. Inverter 2) to measure the new period of fast DCO. Such kind of measurement should be carried out on and on until all inverters have bent tested with the help of a fixed statue slow DCO as reference. In the end, a serial of T _{F ast Bx} (e.g.

T _{F ast B1} , T _{F ast B2} , ..., T _{F ast B23} ) is obtained.

Then the same kind of measurement will be generated for the slow DCO to obtain a serial of period values, T _{Slow Bx} (e.g. T _{Slow B1} , T _{Slow B2} , ..., T _{Slow B23} ), which is in forms of a constant period value of fast DCO (T _{F ast} ) and the number of cycles (N ).

It is possible to measure the exact relationship between T _Slow and T F ast , as illus-

trated in Equation 3.6,

3.2 DCO-Based Vernier TDC

T _Slow = (N/(N + 1)) × T _{F ast} , (3.6) to provide comparisons between periods of fast DCO (T _{F ast Bx} ) and periods of slow DCO (T _{Slow Bx} ).

Finally, T F ast Bx will be sorted ascending while T Slow Bx will be sorted descending like as demonstrated in Figure 3.7.

Cell Number t

t+∆t t+2∆t t+3∆t

t+4∆t ^{Slow DCO}

Fast DCO

22 7

15 2

3 9 16

6 8 12

17 21

7 8

9 14

3

1

21 18

11 15

19 1

Figure 3.7: Demonstration of sorted periods for slow and fast DCOs

Since the the exact relationships among T _{F ast Bx} and T _{Slow Bx} are already known, it is possible to know the exactly point in the figure where the period of fast DCO

(T F ast Bx ) is larger than the one of slow DCO (T _{Slow Bx} ). Then one inverter with

carefully chosen from each DCO will be turned off to get two DCOs with slightly different frequencies.

3.2.3 Catching-up Detection Block

As mentioned in the end of general description part, the set-up and hold-on time is the main considerations for this block. Hence a soft-edged flip-flop is put to use here as in Figure 3.8. The clock signal for the master stage is delayed (e.g. by some inverter or buffer delays) to increase the time for the signal passing onto the slave stage. If the delay time is created properly, the set-up time of the soft-edged flip-flop can be reduced to zero. It also can be constructed by the standard digital logic cells. (24)

However this kind of flip-flop has the same problem as a D-flip-flop does when the

rising edge of the clock comes after the falling edge of the data. Thus, the period of fast

3.2 DCO-Based Vernier TDC

D

RN

CK'

CK'

CK

CK

Q Q

Figure 3.8: Schematic of a soft-edged flip-flop (from (4))

that it can work correctly. The only function for this block is to compare the arriving sequence of two rising-edges. When the one from fast DCO catches up the one from slow DCO, a catching-up signal will be generated to stop the counter and trigger the output logic and control block to produce a measurement result. In the behavior level simulation, an ideal D-flip-flop model is used.

3.2.4 Counter

The counter counts the number of cycles from slow DCO before it is stopped by the catching-up signal. It works at low frequency compared with the DCO working fre- quency. Thus, there is no necessity to use any custom design here.

3.2.5 Output Logic and Control Block

The measurement result is produced according to the values of counter and sign-bit.

Thereafter a reset signal will reset the system for next measurement. The sequence diagram of this block is shown in Figure 3.9. If the LAG signal comes first, the output will be a negative value while a positive value for that LEAD signal comes first.

CATCHING_UP

OUTPUT RST SIGN_BIT

COUNTER ^{6 7 0 1 2 3}

7 -12

4 5 101112 0

Figure 3.9: Sequence diagram of output logic and control block in DCO-based Vernier

TDC

3.2 DCO-Based Vernier TDC

3.2.6 Behavior Level Simulation

The behavior level model is written by Verilog HDL and simulated through ModelSim SE. In order to simplify the coding, two fixed DCOs are introduced instead of DCOs with calibration block. Figure 3.10 below are sequence diagrams. The TDC works well with different kinds of inputs.

(a) LEAD signal comes first

(b) LAG signal comes first

Figure 3.10: ModelSim SE simulation results for DCO-based Vernier TDC

3.3 Vernier Delay Ring TDC

3.3 Vernier Delay Ring TDC

As mentioned in Section 2.4.8, the Vernier delay ring architecture also has many ad- vantages. The detailed block diagram of Vernier delay ring TDC is shown in Figure 3.11, which contains pre-logic, output logic and control, Vernier delay ring, catch-up detection and counter blocks. The pre-logic block, counter and output logic and control block are as the same as those in DCO-based Vernier TDC. Therefore Vernier delay ring and catch-up detection blocks are shown separately.

Pre- Logic

Vernier Delay Ring

Counter

Catching-up Detection

Ou tpu t L ogi c &C o n tr ol

Out LEAD

LAG External Reset

First Signal Last Signal

Sign

Sign

Reset Reset

Internal Reset Stop

First Signal

Arbiters Outputs

Figure 3.11: Block diagram of Vernier delay ring TDC

3.3.1 Vernier Delay Ring Block

The Vernier delay ring block is made of two delay rings as shown in Figure 3.12. All of these delay elements should have the same topology (e.g. NAND) in order to reduce mismatch. The propagation delay in fast ring should be a little shorter than that in the slow ring to get a good resolution (smaller NAND represents shorter propagation delay in the figure.).

Arbiter Arbiter Arbiter Arbiter Arbiter

Slow Ring

Fast Ring Control S

Control F

Figure 3.12: Topology of Vernier delay ring block

3.3 Vernier Delay Ring TDC

The control signal is injected into one input of the first delay element, while the other input is connected to the output of the last delay element. One input of the NAND in the following stages is connected to VDD to make these NANDs work as inverters for symmetry. Two outputs from the delay elements of slow and fast rings are compared by the arbiter, which will produce an output based on the arriving sequence of these two signals. Here, the number of arbiters is the same as that of delay stages in the ring, while there is only one arbiter in the DCO-based Vernier TCD.

Arbiter Arbiter Arbiter Arbiter Arbiter

Slow Ring

Fast Ring Control S

Control F 0

1 0 1 0 1

Figure 3.13: Working principle of Vernier delay ring block

Control Output 1 Output 2 Output 3 Output 4 Output 5

Cell Delay

Cell Delay

Cell Delay

Cell Delay

Cell Delay Cell Delay

Figure 3.14: Sequence diagram of Vernier delay ring block for demonstration

If the control signal is stuck at ‘0’, values from each output will be stuck at a fixed value, as shown in the slow ring of Figure 3.13. When the control signal changes into

‘1’, the output of the first delay element will change from ‘1’ to ‘0’. The signal will propagate through on and on. After the output of the last delay element has been changed, it will be transferred back to the first one. At this time, the output of the first delay element will change from ‘0’ to ‘1’ as shown in the fast ring of Figure 3.13.

The principles for both rings are the same. The sequence diagram is illustrated in

3.3 Vernier Delay Ring TDC

Figure 3.14. The arbiter that connects two outputs of each delay stage should be able to compare both rising-edges and falling-edges, while only rising-edge comparison is considered in the DCO-based Vernier TCD.

3.3.2 Catch-up Detection Block

All outputs from arbiters should be monitored to determine whether catching-up hap- pens or not. These arbiters work at a relevant low frequency if there are enough delay stages. In the behavior level simulation, the model is ideal. While in reality, some other problems should be corrected, e.g. mismatch problem, fake “01” transition, bub- ble problem and small phase error detection (14).

3.3.3 Behavior Level Simulation

The behavior level model is written by Verilog HDL and simulated through ModelSim SE. Figure 3.15 below is the sequence diagrams for Vernier delay ring block. It is easy to find that the interval between two edges from slow and fast rings turns smaller and smaller. The yellow vertical line indicates where the edge from faster ring catches up with the other. The outputs from arbiters also changes at that time for catch-up detection.

Figure 3.15: ModelSim SE simulation results for Vernier delay ring TDC

3.4 Comparison of Two Architectures

3.4 Comparison of Two Architectures

In general, there is not so much difference in working principle between these two architectures. Even we can say that the DCO-based Vernier TDC can be considered as the Vernier delay ring TDC with only one delay stage. Both architectures can provide a high resolution, wide dynamic range and low frequency working conditions for counters and arbiters. However, arbiter architectures should be designed carefully to make sure that it can work correctly. Additionally, catching-up detection should also be carefully thought over.

One main difference is whether it can be synthesizable or not. The advantage for Vernier delay ring TDC is that there is no calibration circuit, while it is a synthesizable design for DCO-based Vernier TDC. The disadvantages of Vernier ring TDC are the complicated read-out circuits and the necessity of custom designs for critical blocks, while the calibration block is really a complicated design for DCO-based Vernier TDC.

A simple example is introduced to show the measurement time comparison for two architectures. If the delay time for each stage is nearly the same and the architectures contain three stages each, the working frequency would be almost the same and it is also possible to get the same high resolution from both. However, the measurement time for DCO-based one is three times longer than the other under the same resolution, because edges comparison happens at outputs from each stage in Vernier delay ring TDC while only the DCO output is compared in DCO-based Vernier TDC.

Based on the design requirements, the reference frequency in ADPLL is less than 100-M Hz (e.g. 25-M Hz typically). If the measurement can be finished within one or a half clock cycle of the reference frequency, it will be much easier to design other blocks in ADPLL. For this reason, a short measurement time is necessary.

Another consideration is that whether the design work is reliable. In the Vernier

delay ring TDC, we can get detailed results after post-layout simulation since the

propagation delay for each ring is designed in advance. However, the delay in DCO-

based Vernier TDC is generated based on automatically placed and routed mismatch,

which is not under control. Additionally, a complicated calibration block is necessary

to keep it working properly. Although a custom design can be used for these two DCOs,

we will lose the attractive feature of being synthesizable.

3.5 Further Investigation of Vernier Delay Ring TDC

In conclusion, we will focus on Vernier delay ring architecture here to investigate its performance by using 65-nm CMOS technology. Some modifications might also be made to improve its functions.

3.5 Further Investigation of Vernier Delay Ring TDC

As mentioned before, Vernier technology is chosen for a small resolution. After a general case study of two kinds of Vernier TDC architecture, we decided to take a further investigation of Vernier delay ring TDC.Several blocks are realized in schematic and related simulations are made below.

3.5.1 Delay Element

The propagation delay of delay element is not critical for resolution, which only affects the measurement time. We need to build a ring with delay elements, where the output of the last stage should be fed back to the first one. Each delay element has one output. The first stage have two inputs, control signal and signal from the last stage, while others only need one input to connect to the output of prior stage. In order to have a good symmetry in the ring, the NAND gate is used as delay element. The other stages besides the first one, the additional input will be connected to VDD.

It is easy to notice that if we use a conventional NAND gate as the delay element here, the propagation delay is fixed. If the process and / or mismatch variation are large, it is possible that the propagation delay in the fast ring is larger than that in slow ring. Then, the TDC will not work properly. Thus a voltage-controlled NAND delay element is introduced. Additional control MOSFETs are added between the NAND and two power lines as shown in Figure 3.16 and design parameters of transistors are listed in Table 3.1.

Mosfet Width NF Length M1, M3 7.686µ 14 60n M2, M4 5.166µ 14 60n M5, M6 3.122µ 14 60n

M7 5.292µ 28 60n

Table 3.1: Design parameters of voltage-controlled NAND delay element