SRI MOHAN KRISHNA DAVID SANDEEP

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SRI MOHAN KRISHNA DAVID SANDEEP

Under the guidance of

Mr. MATTIAS O’NILS

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Introduction

 Noise filtering - The process of estimating the original image information from noisy data

 Vector median video filter is an Image restoration filter .

 Goal of image restoration- improve image in a predefined sense.

 Important aspect – having a prior knowledge of degradation phenomenon.

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Basic function of a filter:

Restoration filter f(x,y)

Ŋ(x,y)

g(x,y)

f(x,y)

 g(x,y) = f(x,y) + Ŋ(x,y)

Restoration of f(x,y) form g(x,y) with a knowledge of Ŋ(x,y)

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What is the need for a new filter?

 Problem with averaging filter(mean filters)

-

Blurs edges and details in image.

- Not effective for salt and pepper noise

.



Median filter:

- Taking the median value instead of average or weighted average of pixels.



sort all the pixel values in an increasing order,take the middle one

.

-

yeilds excellent results for images corrupted by salt and

pepper noise

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What is salt & pepper noise ?



a kind of impulsive noise

• Pa for z= a

• P(z) = P_b for z = b

• 0 for others

 If Pa nearly eqaul to Pb

and Pa,Pb ≠0

Then impulsive noise resembles salt and pepper noise

 Because of image digitization impulse noise tends to have extreme values i.e very large compared to strength of image signal

a b z

P_a P_b

P(z)

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Median filter: 3 x 3 square window

100 100 100 100 100 100 200 205 203 100 100 195 200 200 100 100 200 205 195 100 100 100 100 100 100

100 100 100 100 100

100 100

100 195

100 200 100 200 200 200

100 100 100 100 100 100 100 100 Window

shape

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Directional Vector Median Filter

S21 S22 S23 S11

S22

S33 S12

S22 S32 S22

S13

S31

Medians are calculated in four directions resulting in four values In the second stage the median of the four values is calculated

First Stage Median

filter

Second stage Median

filter

s22

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Block diagram

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Data flow

1. Address Generator

0 0 1 1 1 1 1 1 1 0 0 0

0 0 0 1 1 1 1

rsync rsync_o

Address 0 1 2 3 4 5 639 640 0 0 0

1 1 1 0 0

Genarates address where the input data is to be stored in block RAM’s

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Block RAM’s

254 1 1 1 1 1 1

639 640 0 0 0

0 1 2 3 4 5

100 1 1 1 1 1 1

254 20 Data_in = 20

Data_read1 254

Data_read2 100

address

Block RAM1

Block RAM2

When read_write signal is enabled the data in the location specifed by address is read first and after that data to be written is placed in the location

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Counter

• The counter counts the row and column values with reference to the frame synchronisation and row synchronisation pulses.

• Generates enable pulses for the edge detector block and dvmf evaluator block.

• If row synchronisation pulse turns high from low the column value is initialized 1.

• If row sync pulse is high the value of column is incremented for every clock pulse

• If frame synchronisation pulse changes high from low then row count is initialized to 1

• Row count is incremented at row synchronisation positive edge transition.

• The enable signal is generated when column count >0 and < 641

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Edge detector

• The edge detector detects the edges of the frame and informs to the DVMevaluator block

• If fsync is high ,it informs it as upper edge of the frame and initialises the row count value to 0.

• If rsync pulse changes from low to high it informs it as the left edge of frame and initialises the column count to 1 and increments row count.

• If rsync pulse changes from high to low it informs that it is the right edge of the frame

• If the row count = 480 then it informs that it is the bottom edge of the frame.

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DVM Evaluator

255 Pdata = 255 255

Data_read 1= 255 Data_read 2 = X

Pdata = 230

x

230

255

255 200

200

255

255 255 Data_read 1 = 200

0

200 170 180 255 200 180 255 200 180

corner

frame

Up/ Down

150

200 100 130 210 215 200

150 210

Left / right

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results

Noisy input image

Matlab output VHDL output

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Results

• The noise in the input image was removed successfully by the designed filter.

• Maximum Frequency: 51 MHz

• No of 641x8-bit dual-port block RAM’s used : 2

• Number of 4 input LUTs : 3288

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Conclusion

• The obtained results are compared with the MAT LAB output and the results are found to be absolutely comparable.

• The only deviation obtained was at the first row where in the logic of VHDL specifies the first row output to be the pixel values of the last row of the previous frame.

• The customer requirement of 30 MHz frequency has been met successfully.

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