Reconfigurable Analog to Digital Converters for Low Power Wireless Applications

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Reconfigurable Analog to Digital Converters for Low Power Wireless Applications

E. MARTIN I. GUSTAFSSON

Doctoral Dissertation

KTH - Royal Institute of Technology Stockholm, Sweden, 2008

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TRITA-ICT/ECS AVH 08:04 ISSN 1653-6363

ISRN KTH/ICT/ECS AVH-08/04–SE ISBN 978-91-7178-932-7

KTH School of Information and Communication Technology Isafjordsgatan 39 SE-164 40 Kista SWEDEN Akademisk avhandling som med tillstånd av Kungl Tekniska högskolan framlägges till offentlig granskning för avläggande av Teknologie Doktorsexamen i Elektronik och datorsystem måndagen den 2 juni 2008 klockan 15:00 i sal N1, Electrum 3, Kungl Tekniska högskolan, Isafjordsgatan 28, Kista.

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Abstract

The commercialization of Marconi’s radio transmission and reception, along with the development of integrated circuits in the 1960’s have facilitated many new consumer products for wireless communication, where the mobile phones or handsets are one. These handsets started out as a portable phone, mounted in cars, and have with time added additional services as Short Message Service, and have today become a media center with global positioning, and high-speed internet connection. This has been possible with the use of multistandard radios, that can receive and transmit information using many different wireless communication standards. Many of these handsets have one dedicated integrated radio chain for each communication standard used, which results in a large and expensive integrated circuit for these modern handsets. The challenge of today is to make modern handsets cheaper, smaller, and lower in power consumption. The power consumption is an issue of particular importance since the capacity of the available power sources do not increase with the demands of the handsets. One proposed method to do this is to move towards Software Defined Radio, where software of the handset control a single reconfigurable radio, and set which communication standard that the handset is to use. In this way, the handset can be reconfigured to communicate in the most power or data efficient way, depending on the choice of the user. The area of the Software Defined Radio receiver is also smaller than the parallel chains that are implemented today, which reduces the cost of production. The Software Defined Radio receiver is very challenging to design, since there is a large number of wireless communication standards, sometimes even within the same frequency bands. This make the reception of a weak desired signal difficult, when there may be a strong interferer in the same frequency band. A key component in the Software Defined Radio receiver is the Analog to Digital Converter. The development of new wireless communication standards requires higher performance of the Analog to Digital Converter in the receiver. This performance is hard to achieve, when the power consumption should be low, and the area should be small, especially in the modern integrated circuit technologies.

This thesis put the development of the communication industry into a historical perspective, and gives a review of the fundamental development of wireless communication applications. The fundamental concepts and implementations of Analog to Digital Con- verters for multistandard wireless receiver chains are also covered. Finally two case studies on the design of multistandard Analog to Digital Converters for Software Defined Radio applications are presented. These Analog to Digital Converters implement different meth- ods of reconfiguration in order to comply with the requirements of the standards. The first case study is to the knowledge of the author the first reported reconfigurable Analog to Digital Converter for Wireless Personal Area Networks, that can be reconfigured from Bluetooth to the UWB communication standard. This is done by changing the architecture of the Analog to Digital Converter from Sigma Delta type to flash type. This reconfigurable Analog to Digital Converter is implemented at transistor level. The second case study investigates the limits of circuit level reconfigurability in an algorithmic Ana- log to Digital Converter. It is found that the requirements of two wireless communication standards can be covered with the use of smart circuit design techniques. The performance of this Analog to Digital Converter has been validated with experimental measurements.

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List of Publications

[1] Liang Rong, Martin Gustafsson, Ana Rusu, Mohammed Ismail, “Systematic Design of a Flash ADC for UWB Applications”, in Proceedings of ISQED 2007, San Jose, USA, pp. 108 - 112, March, 2007.

[2] A. Rusu, Martin Gustafsson, Delia de Llera Rodriguez Gonzalez, Mohammed Ismail, “Flexible ADCs for Wireless Mobile Radios” in Proceedings of ECCTD 2007, Sevilla, Spain, pp. 172 - 175, August, 2007.

[3] Martin Gustafsson, Ana Rusu, Mohammed Ismail, “Behavioral Modeling of a Programmable UWB/Bluetooth ADC” in Proceedings of ICECS 2007, Mar- rakech, Morocco, pp. 1159 - 1162, December, 2007.

[4] Martin Gustafsson, Ana Rusu, Mohammed Ismail, “Systematic Design of a High-Speed Capacitive Interpolative Flash ADC”, Submitted to Analog Inte- grated Circuits and Signal Processing, Springer, 2007.

[5] Martin Gustafsson, Ana Rusu, Mohammed Ismail, “Design of a Reconfig- urable ADC for UWB/BT Radios”, Accepted for publication in proceedings of NEWCAS 2008, Montreal, Canada, June, 2008.

[6] Martin Gustafsson, Ana Rusu, Mohammed Ismail, Harald Neubauer, Johann Hauer, “A Flexible Algorithmic ADC for Wireless Sensor Nodes”, Submitted to ICECS 2008, Valetta, Malta, August, 2008.

[7] Martin Gustafsson, Ana Rusu, Mohammed Ismail, Harald Neubauer, Johann Hauer, “A Programmable Algorithmic ADC for Low-Power Wireless Ap- plications”, Submitted to Analog Integrated Circuits and Signal Processing, Springer, 2008.

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Publications not Included in this Thesis

[8] Martin Gustafsson, Jonny Johansson, Jerker Delsing, “A CMOS amplifier for Piezo-Electric Crystal Interfaces”, In proceedings of MIXDES, Stettin, Poland, pp. 125 - 129, June, 2004.

[9] Martin Gustafsson, Jonny Johansson, Jerker Delsing, “Relative Ultrasound Measurement Circuit“, in Proceedings of WISP, Faro, Portugal, pp. 322 - 327, September, 2005.

[10] Martin Gustafsson, “Integrated Low Power Ultrasound Sensor Interfaces“, Licentiate Thesis, Luleå University of Technology, November, 2005.

[11] Jonny Johansson, Martin Gustafsson, Jerker Delsing, “An autonomous low- power transmit/receive ASIC with on-chip high voltage generation for piezo- electric transducers“, Elsevier Sensors and Actuators A: Physical, Vol 125, pp. 317 - 328, January, 2006.

[12] Martin Gustafsson, Ana Rusu, Mohammed Ismail “A Survey of Reconfig- urable ADCs for Low-Power Wireless applications“, In proceedings of SSoCC, Kålmarden, Sweden, May 2006, (Non-reviewed).

[13] Martin Gustafsson, Ana Rusu, Mohammed Ismail, “A Reconfigurable ADC for UWB/Bluetooth”, In Proceedings of SSoCC, Fiskebäckskil, Sweden, May, 2007, (Non-reviewed).

[14] Kangqiao Zhao, Saifullah Amir, Xiaozhou Meng, Muhammad Ali, Martin Gustafsson, Ana Rusu, Mohammed Ismail, “Circuit implementation of a Re- configurable Successive Approximation ADC”, Submitted to ICECS 2008, Valetta, Malta, August, 2008.

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Acknowledgments

I would like to start this thesis by express my gratitude to Docent Ana Rusu, for the encouragement, support, and inspiration. I would also like to thank Professor Mohammed Ismail for accepting me as a student, for his triedless encouragements when things were at delicate states. Furthermore I would like to thank Saul Ro- driguez Duenas for all the good discussions during my two years at KTH. I would not have gotten this far without your help. I would like to thank Adam Strak, Delia de Llera Rodriguez Gonzalez, Fredrik Jonsson, and Jad Atallah for all the support and for making my time at KTH as pleasant as it has been.

Education is something that happens on the inside, it is when you change your way of thinking, and doing things. This process of change is slow, and usually progresses beyond ones normal perception, thus leaving you completely unaware of the change you have made, and the progress you currently is making. A moment of recollection, such as writing a summary of the work you have been doing for the last two years bring these things to your attention.

This process of change is something that your environment is aware of, as one is thrown between hope and despair. For helping me come this far I have devoted this thesis to my family, but I would like to mention a few of my friends: Michael and Anna, Jens, Hans, Alexander, Sus, Dennis, Niclas, Khashayar.

I would like to thank Per Larsson-Edefors, Daniel Eckerbert, Roger Malmberg and Lena Peterson for all the support and inspiration in the early stages of my work.

I also would like to thank Jerker Delsing, Per Lindgren, Jonny Johansson, Gustaf Stenberg, Jokke, Linus, Jonas Ekman, C, Magnus Berndtsson, Jerry, and Kalevi for the time at LTU.

I would like to thank Harald Neubauer, Hans Hauer, Jose-Angel Diaz Madrid, Joseph Sauerer and Andrés García-Alonso for making my stay in Germany fruitful.

Finally I would like to mention Allan Olson, Hans-Erik Backram, Marcus Movér, Mats Carlsson, and Jan Lindberg and thank them for the good cooperation during my final year.

Martin Gustafsson, March 2008

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Abbreviations and Acronyms

ADC Analog to Digital Converter AMPS Advanced Mobile Phone System BPSK Binary Phase Shift Keying

BT Bluetooth (Not a standard definition)

BW BandWidth

CDMA Code Division Multiple Access CCK Complementary Code Keying CI Capacitive Interpolation

CMOS Complementary Metal Oxide Semiconductor

CT Continuous Time

DAC Digital to Analog Converter DCM Dual Carrier Modulation

dB deciBel

dBc deciBel relative to carrier

dBm deciBel related to a 50 Ohm load

DC Direct Current

DLL Delay Locked Loop

DNL Differential Non-Linearity

DR Dynamic Range

DVB Digital Video Broadcasting

ECG Electro Cadio Gram

ENOB Effective Number of Bits

F Noise Factor

FDD Frequency Domain Duplexing FIR Finite Impulse Response FOM Figure of Merit

GBW Gain and 3-dB BandWidth product GFSK Gaussian Frequency Shift Keying GMSK Gaussian Minimum Shift Keying GPS Global Positioning System

GSM Global System for Mobile communication IF Intermediate Frequency

INL Integral Non-Linearity

I/Q In-phase and Quadrature-phase LNA Low Noise Amplifier

LO Local Oscillator

LSB Least Significant Bit MASH Multi stAge Noise sHaping MBPS Mega Bits Per Second MiM Metal Insulator Metal

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viii

Mote Sensor node

MSB Most Significant Bit MSPS Mega Samples Per Second

NF Noise Figure

NSD Noise Spectral Density NTF Noise Transfer Function

OFDM Orthogonal Frequency Domain Multiplexing

PA Power Amplifier

PCB Printed Circuit Board

PLL Phase Locked Loop

PSD Power Spectral Density Q Quantization interval

QAM Quadrature Amplitude Modulation QPSK Quadrature Phase Shift Keying

RF Radio Frequency

SAR Successive Approximation Register

SC Switched Capacitor

SDR Software Defined Radio SFDR Spurious Free Dynamic Range

Σ∆ Sigma Delta

Slice One of the ADCs in a parallel ADC structure SINAD SIgnal to Noise And Distortion Ratio

SMS Short Message Service

SQNR Signal to Quantization Noise Ratio

SR Software Radio

SNDR Signal to Noise and Distortion Ratio STF Signal Transfer Function

TDD Time Division Duplexing THD Total Harmonic Distortion

UWB Ultra WideBand

VCO Voltage Controlled Oscillator

WCDMA Wideband Code Division Multiple Access WiMAX Worldwide interoperability for Microwave Access WLAN Wireless Local Area Network

WPAN Wireless Personal Area Network

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List of Figures

1.1 The Puldhu transmitter station of Marconi’s experiment in 1902[29] . . 2

1.2 Kilby’s integrated circuit, from the American Institute of Physics: Emilio Segre Visual Archives . . . 3

1.3 Early cellular phone from Motorola, the DynaTAC 8000X portable cellular phone, 1984. . . 3

1.4 Wireless communication standards overview . . . 5

2.1 The single conversion super heterodyne receiver [59] . . . 12

2.2 The signals through a super heterodyne receiver . . . 14

2.3 The homodyne receiver . . . 15

2.4 The signals through a homodyne receiver . . . 16

2.5 The signals through a low-IF receiver . . . 18

2.6 The quadrature low-IF receiver . . . 19

2.7 Software Radio receiver . . . 20

2.8 SRD Zero IF receiver . . . 22

2.9 ADC specifications overview for a Zero-IF receiver . . . 24

2.10 ADC specifications overview for a Zero-IF receiver . . . 25

3.1 A continuous-time and continuous-amplitude ECG signal . . . 28

3.2 A discrete-time and continuous-amplitude ECG signal . . . 29

3.3 A continuous-time and discrete-amplitude ECG signal . . . 30

3.4 A discrete-time and discrete-amplitude ECG signal . . . 30

3.5 Static ADC errors . . . 32

3.6 A 3 bit flash ADC implemented with comparators and a resistive ladder reference . . . 36

3.7 A 3 bit folding flash ADC, with only 4 two-input comparators. . . 37

3.8 A 4-bit interpolating ADC with a 1-to-4 interpolation scheme . . . 39

3.9 An illustration of interpolation in a flash ADC. Three new responses are created with the use of this 1 to 4 interpolation, as shown in Fig. 3.8 . . 40

3.10 The concept of oversampling . . . 42

3.11 A first order Σ∆ modulator, shown with quantizer in a) and with quantizer as a noise representation in b) . . . 43

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List of Figures xiii

3.12 The noise shaping in different order of Σ∆ modulators . . . 44

3.13 The SQNR for different quantizer resolutions and loop order versus OSR 45 3.14 A second order feedback Σ∆ modulator block diagram . . . 46

3.15 A second order feedforward Σ∆ modulator block diagram . . . 47

3.16 Input signal histogram comparison for a feedforward modulator in a) and a feedback modulator in b) . . . 47

3.17 The 2-1 MASH architecture . . . 48

3.18 The steps in a discrete time SC delaying integrator . . . 50

3.19 A block diagram of a second order continuous time feedback modulator 50 3.20 A block diagram of a pipelined ADC . . . 52

3.21 A block diagram of a pipelined stage . . . 53

3.22 The processing of an input signal in a 4-stage, 1 bit per stage pipelined ADC . . . 53

3.23 A magnified image of the input from the 4-stage, 1-bit pipelined ADC, with the associated digital values for the 4-bit conversion . . . 54

3.24 A SC implementation of a 1-bit pipeline stage . . . 55

3.25 An algorithmic ADC block diagram . . . 58

3.26 A SC implementation of an algorithmic 1-bit ADC . . . 59

3.27 A SC implementation of the double capacitor technique in algorithmic ADCs . . . 60

3.28 Timing diagram of algorithmic ADC operating with time scaling . . . . 60

3.29 A SC implementation of the double capacitor and double sampling technique in algorithmic ADCs . . . 61

3.30 A simplified timing diagram for the sampling time maximization and time scaling scheme . . . 61

3.31 A block diagram of a DAC based SAR ADC. . . 62

3.32 A block diagram of a charge redistribution based SAR ADC. . . 63

3.33 A block diagram of time interleaved ADCs. . . 66

4.1 Block diagram of the MASH ADC [74] . . . 74

4.2 Block diagram of the reconfigurable pipeline [5] . . . 75

4.3 Bias current generation for different modes of operation to amplifiers in [74] . . . 78

4.4 Block diagram of reconfigurable flash ADC [99] . . . 79

4.5 Preamplifier schematic in reconfigurable flash ADC [99] . . . 80

5.1 Handset applications for a BT/UWB transceiver . . . 82

5.2 Block diagram of Reconfigurable BT/UWB ADC . . . 84

5.3 Block diagram of possible reconfigurability in a CI flash ADC . . . 86

5.4 Energy per quantization step for flash ADCs . . . 87

5.5 Block diagram of the 1-to-2 capacitive interpolation scheme . . . 88

5.6 Implemented amplifier for the BT Σ∆ ADC . . . 89

5.7 Root locus plot for coefficients k1=1.75, b1=1, and b2=0.8 . . . 90

5.8 Block diagram of Reconfigurable CI flash ADC . . . 91

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xiv List of Figures

5.9 Behavioral model of interpolating amplifier from Matlab/Simulink . . . 92

5.10 Input signal amplitude error caused by sampling clock jitter . . . 93

5.11 Behavioral model of signal generator including jitter a) as suggested by [64], and b) as suggested by [36] . . . 94

5.12 Implemented amplifier for the BT Σ∆ ADC . . . 95

5.13 Layout of CI flash ADC . . . 97

5.14 Normalized PSD plot from a two-tone test at behavioral level of ADC in BT mode . . . 98

5.15 Normalized PSD plot from a two-tone test at circuit level of ADC in BT mode . . . 99

5.16 Normalized PSD plot from a two-tone test at behavioral level of ADC in UWB mode . . . 99

5.17 Normalized PSD plot from a two-tone test at circuit level of ADC in UWB mode . . . 100

5.18 SINAD versus input signal voltage for both modes of operation from behavioral modeling . . . 101

5.19 SINAD versus input signal voltage for both modes of operation from circuit level simulations . . . 101

6.1 Sensor nodes in landslide early warning system . . . 104

6.2 Mote block diagram with transceiver . . . 105

6.3 Overview of the performance of Pipelined, Algorithmic, Σ∆ and SAR ADCs . . . 108

6.4 Overview of the performance of Pipelined, Algorithmic, Σ∆, and SAR ADCs . . . 108

6.5 Detailed block diagram of algorithmic ADC . . . 110

6.6 Amplifier step response depending on non-idealities . . . 111

6.7 2-pole amplifier response with different phase margins . . . 112

6.8 Telescopic amplifier with gain boosting . . . 114

6.9 Dynamic range simulation results from behavioral model for Bluetooth and CDMA2000-1X modes . . . 115

6.10 Power spectral density plot of a full scale input in CDMA2000-1X mode from behavioral simulation . . . 115

6.11 Power spectral density plot of a full scale input in CDMA2000-1X mode from schematics . . . 116

6.12 Die micrograph . . . 117

6.13 Photo of the test Printed Circuit Board for the characterization of the algorithmic ADC . . . 118

6.14 SINAD of ADC over range of reconfiguration . . . 119

6.15 Dynamic range measurement with 200 kHz input signal . . . 120

6.16 PSD plot of a 200 kHz input signal in CDMA2000-1X mode . . . 120

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Chapter 1 Introduction

1.1 Development of the Communications industry

Imagine one day an invention is created, making one or both of the distance com- munications controlled by the Swedish Bureau of Telegraphy, irrelevant. Today fu- turistic scenarios describe the wireless pocket telephone that is every man’s property.

Without paying too much attention to these fancies, it is however not unthinkable that our means of long distance communication can change. This change can be of such magnitude that the equipment owned by the Swedish Bureau of Telegraphy, is turned into a worthless pile of rubbish.

- Freely after H. Rydin in 1914 (Original publication in Swedish)

This is how Rydin described the futuristic fantasies, right at the end of the First World War. These lines were published in a book written as a tribute to the banker Marcus Wallenberg on his 50:th birthday.

If Rydin by the time of writing was aware of the wireless telegraph and the demon- strations that both Marconi and Popov already had made in the end of the nine- teenth century is unknown. Popov and Marconi started at about the same time to transmit text messages with the wireless telegraph, and both are known as the fathers of the wireless telegraph. Neither Popov nor Marconi really made a techno- logical invention with their communication as such, it was rather an implementation of the already established knowledge in the academia. Popov, who came from the Russian academia, developed a demonstrator that communicated the message

“Heinrich hertz” in 1896 [59]. Marconi on the other hand came from a rich Italian family, with no academic background in line with Popov. His dedicated interest, engineering skills and solid funding allowed him to build a wireless telegraph that with the help of his parents, attracted the attention of the British authorities [59].

This attention awarded him a patent, and the possibility to continue his experiments, now in a company based in Great Britain, which evidently lead to the first

1

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2 CHAPTER 1. INTRODUCTION

transatlantic communication in 1902 [29]. The Puldhu transmitter station used in this first communication is shown in Fig. 1.1.

Figure 1.1: The Puldhu transmitter station of Marconi’s experiment in 1902[29]

These systems were still in their cradle in 1914, and the development of the components for these wireless systems were large and extremely high in power. This strongly limited the deployment of electronics in many areas. How Rydin visioned the pocket size electronic system is very difficult to understand, until 33 years later, when the transistor was invented at Bell Labs in 1947 by Bardeen, Brattain, and Shockley. Several research companies were interested in this development, and in 1959 the integrated circuit (IC) was invented at both Texas Instruments by Kilby, and at Fairchild Semiconductor by Noyce. Both of them filed for patents, and both of them were also granted patents, Noyce in 1961, and Kilby in 1964. Kilby’s integrated circuit is shown in Fig. 1.2

In the 1960’s, ICs were in their cradle, and Rydin’s now almost 50-year old vision was still far away from becoming real. The electronic industry exploded in the late 1960’s and onwards, and this lead to smaller integrated circuits with more functionality to a lower cost, for each integrated circuit generation that was created.

This was described by Gordon Moore in 1965 as “Moore’s law” [48]. The wireless telephones were now based in cars, to support the weight of the electronics and to provide power for the device. Experiments were going on how to extend the range and provide services for a mass market, but the interest of the authorities was still lacking.

The first commercial cellular phone call was made 14 years later in Tokyo, in 1979, and one year later in the United States. By this time the cellular infrastructures

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1.1. DEVELOPMENT OF THE COMMUNICATIONS INDUSTRY 3

Figure 1.2: Kilby’s integrated circuit, from the American Institute of Physics:

Emilio Segre Visual Archives

had already been built in both countries. One early cellular phone, from 1984 is shown in Fig. 1.3.

Figure 1.3: Early cellular phone from Motorola, the DynaTAC 8000X portable cellular phone, 1984.

Today, the fancies told by Rydin back in 1914 are true since more than a decade.

The development of this wireless pocket phone, or handset is heading for new challenges. The handset was originally developed to provide telephone calls, but since the integration of the Short Message Service (SMS) into the Global Standard of Mobile communication (GSM) in the mid 1980’s, the additional services of handsets have been growing fast. Today a high-end handset can have features like music, FM radio, TV, high-speed Internet, Global positioning, etc. The communication of the handset can be of one or many standards, e.g. over one of the generations of mobile communication (2G, 2.5G, 3G a.s.o.), or directly over wireless high-speed Internet connections, provided by one of many network service providers. The applications of the wireless communication is not limited to only the handset, but many other

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small electronic devices use wireless communication to transmit and receive data, which was something that Rydin could not foresee in 1914.

The abundance of wireless communication standards is also problematic for the device. The available frequency spectrum for wireless communication is limited, and thus more standards are competing to provide services, sometimes even in the same frequency spectrum.

This means that small and sensitive signals need to be filtered and demodulated from the ether that used to be quiet (except from around Marconi’s transmitters), but is filled with strong wireless communication traffic today. In addition to these strong interferers, the high mobility of the handset can cause heavy fading of the signal. This makes the receiver the most interesting part in the multistandard device.

The industry implements a new receiver for each standard that is added to the multistandard device, and this new receiver is added next to the other ones on a single IC [69]. For a multistandard device as the high-end handsets are today, this IC becomes large, which is impractical from a cost-of fabrication perspective.

The large number of analog and digital blocks also increase the power consumption of the IC, if not proper care is taken to ensure that everything is powered down properly. An illustration of such a multistandard receiver is shown in Fig. 1.4.

This receiver is also impractical since many of the features needed in these parallel transceivers are similar, and could be reused between several standards.

The increase in power consumption is problematic, since the energy density of rechargeable power sources do not increase as fast as the power consumption of the electronics does. This implies that the devices become heavier and larger to accommodate the larger power sources, which decreases the portability. These are two factors why the reduction of power consumption in multistandard receivers is critical to allow high-end products to become cheaper, smaller and thus available to a broader potential market.

1.2 Motivation of this work

This thesis addresses the design of reconfigurable Analog to Digital Converters (ADCs) for low power multistandard wireless receivers. The multistandard wireless receivers that are implemented today are parallel, which makes them large in size [69], which increase the cost of fabrication, and the power consumption of the integrated circuit due to the leakage currents. The push for longer standby and operation times of these applications force the power consumption of the electronics to be reduced.

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1.2. MOTIVATION OF THIS WORK 5

LNA

VGA

ADC

ADC I

Q Multi-

Band Generator

90o Baseband

processing LNA

VGA

ADC

ADC I

Q Multi-

Band Generator

90o Baseband

processing

LNA

VGA

ADC

ADC I

Q Multi-

Band Generator

90o Baseband

processing

WLAN GSM

WCDMA

Data out Data out Data out

Data processing

Figure 1.4: Wireless communication standards overview

The ADC requirements for modern wireless communication standards are pushed upwards in sampling frequency and dynamic range. One example of this is when the 3G mobile standard was developed, the CDMA2000 was abandoned in most places, in privilege of the WCDMA communication, which requires more bandwidth of the ADC. The sampling frequency of the ADC for a zero-Intermediate Frequency (IF) receiver changed from 1.25 MHz up to 5 MHz, for an In-phase/Quadrature-phase (I/Q) receiver.

The ADC performance does not scale with process as the digital performance does, and new techniques are needed to improve the ADC performance. This is em- phasized by trends like Software Radio, where the receiver is an antenna, a Front End Module (FEM), and an ADC. In this application, the ADC needs to cover a very wide bandwidth at high resolution. In the Software Defined Radio (SDR), the receiver is built with reconfigurable blocks, and the ADCs have to be made recon-

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figurable in sampling rate and dynamic range. This without introducing significant overhead in either leakage currents or area, compared to a customized solution.

This thesis investigates ADC reconfigurability, with the focus on achieving the specifications set by Zero-IF multistandard SDR receivers, in two low-power wireless applications.

1.3 Systematic design approach

Reconfigurable ADCs are complex systems that can be difficult to design, since many architectures and parameters need to be evaluated to find an optimal solution, before the real design effort can start. The experienced ADC designers know how the design should start, simply because they have done it many times before, and with their experience they can quickly estimate the important circuit specifications. For the beginners, it is hard to know how to start. This is where behavioral modeling of ADCs comes in handy. This design methodology have been used for a long time for Sigma Delta ADCs, but it has not been used to the same extent for other ADC architectures.

The procedure starts with the design of a high-level model of the ADC, in an environment where circuit implementation issues, such as biasing can be disregarded.

This creates a rapid understanding of the functionality of the ADC, and allows an optimal solution to be found, along with circuit block specifications [37, 64, 89, 90].

The method with which the work in this thesis has been performed is:

1. Design high-level ideal ADC model

2. Gradually introduce circuit based non-idealities

3. Find circuit block specifications for the building blocks, and verify the im- plications of these non-idealities to the system level, e.g. through SINAD measurements

4. Implement VerilogA/AHDL models in Cadence, and validate the system level specifications, now with bias voltages

5. Implement the circuit blocks to the specifications, and gradually replace the VerilogA/AHDL models with circuit blocks

6. Validate the system level specifications by using co-simulations, where the critical blocks are represented as circuits, and the non-critical blocks as Ver- ilogA/AHDL models

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1.4. THESIS OUTLINE 7

7. Finally validate system specifications at circuit level 8. Freeze schematics and start layout

9. Validate layout with post-layout simulations 10. Tape-out, fabrication and measurements

This method will save time, since only the critical blocks of the ADC are represented by the complex circuit description, and the other blocks are represented as VerilogA/AHDL models.

1.4 Thesis outline

Chapter 1 is the introduction of the thesis, where the area of integrated circuits and wireless communication is put into a historical perspective. The motivation of the thesis is given, the method with which the work has been conducted, as well as a summary of the scientific contributions.

Chapter 2 describes radio receivers in more detail, and also reconfigurable radio receivers. With the base of these reconfigurable receivers, the ADC specifications for a number of wireless communication standards are also given. Based on these different specifications, an overview of multistandard ADC solutions are presented.

Chapter 3 discusses the fundamentals of analog to digital conversion, and gives a refresher of the basic concepts for a few ADC architectures that provide a high degree of flexibility. The Sigma Delta ADCs are discussed in particular, along with flash, pipeline, and algorithmic ADCs. The chapter is concluded with a discussion about multistandard ADCs, and design approaches for multistandard ADCs.

Chapter 4 is devoted to reconfigurability in ADCs. The concepts of architec- tural and circuit reconfiguration are explained, and two examples are presented in more detail on each level of reconfiguration. It introduces the case studies of Chapters 5 and 6.

Chapter 5 is a case study on an architectural reconfigurable ADC, where a novel ADC that can be reconfigured between Bluetooth and WiMedia OFDM Ultra Wide- Band (UWB) standards is proposed.

Chapter 6 is a case study of circuit level reconfigurability in ADCs, and shows how an algorithmic ADC can be configured for many applications, and among these to be used in a SDR receiver targeted for the Bluetooth and the CDMA2000-1X communication standards.

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Chapter 7 presents the conclusions of the thesis.

1.5 Author’s contributions

This thesis is based on the publications in the list of publications. The content and contribution of the publications are as follows:

In [1] the need of accurate behavioral modeling in the systematic design of a Ca- pacitive Interpolation (CI) flash ADC is demonstrated. Behavioral modeling had previously mainly been used for Sigma Delta ADCs, but this work illustrates the feasibility to implement this for flash ADCs as well. The author wrote and presented the paper, based on the work of Liang Rong.

In [2] the feasibility of a reconfigurable ADC that covers all the present wireless communication standards is presented. The technique to solve this is presented, along with simulation results from the behavioral model of the ADC for all modes of operation. The author proposed the solution on how to reconfigure the ADC array to include the UWB standard, and wrote two sections of the paper.

In [3] the behavioral modeling results of a reconfigurable ADC that covers Blue- tooth and UWB communication standards are demonstrated. It is illustrated how the reconfiguration between these standards can be achieved, and simulation results from the behavioral model in both modes of operation are shown. The author proposed the solutions and wrote the paper.

In [4] a new amplifier model for high-speed ADCs, a more accurate jitter model for flash ADCs, and the implementation results of the full systematic design flow of a CI flash ADC for UWB applications are presented. The author implemented the models, the circuits, and wrote the paper.

In [5] the circuit implementation of the reconfigurable Bluetooth/UWB ADC is demonstrated. It is shown that the concept from [3] is feasible, and that it can be implemented at circuit level. The author implemented the models, the circuits and wrote the paper.

In [6] the behavioral modeling is extended to algorithmic ADCs, and it is shown that an accurate model can be build. The circuit implementation is done based on the behavioral level simulation results. Secondly, reconfigurability is investigated for algorithmic ADCs. The author wrote the paper, and implemented models and circuits.

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1.5. AUTHOR’S CONTRIBUTIONS 9

In [7] the measurement results of the flexible algorithmic ADC presented in [6]

are shown. The measurement setup is presented, along with measurements of the range of reconfigurability for a given sampling rate. The author wrote the paper, and performed the measurements.

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Chapter 2 Multistandard radio receivers

2.1 Radio Receiver Architectures

One of the central steps in making Rydin’s vision for the handset come true, was to drastically reduce the size and power consumption of the radio that Marconi used. The pulses sent by the transmitter stations quickly faded with distance, and were easily drowned in the noise generated in the receiver. This called for more advanced receivers, and a new way to receive signals was discovered by Armstrong during his service in France during 1918 [2]. It was named the super heterodyne receiver.

2.1.1 The super heterodyne receiver

The earliest reports on the super heterodyne receiver dates back to 1918, where the full details of the system were not made public until late 1919 [6]. In those days, some recent improvements to the super heterodyne receiver were presented, along with enhancements that made this type of receiver a success [6]. The name heterodyne comes from super hetero- which means very different, and -dyne which means tone. A block diagram of a super heterodyne receiver for audio applications is shown in Fig. 2.1. This receiver is a dual conversion receiver, which means that there are two frequency conversion steps that takes place. The frequency conversion is changing the Radio Frequency (RF) input, to two Intermediate Frequency (IF) signals, IF1 and IF2.

There are several components involved to transform the input RF signal into the desired audio signal at the end of the receiver, shown in Fig. 2.1. The blocks in the receiver from left to right are:

Antenna it receives the signal. The antenna is adjusted to receive the desired frequency band.

11

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12 CHAPTER 2. MULTISTANDARD RADIO RECEIVERS

LNA IF-A

Local Oscillator1

Demod. Audio processing

Tuning

1 2 3

5

6 7 8 12 Audio

out 4

Band select Image reject Channel select

Local Oscillator2

9 10

Channel select

11

Tuning

Figure 2.1: The single conversion super heterodyne receiver [59]

Band select filter of the Front End Module (FEM). This filter makes the first selection of the input signal, and may also be used in the duplexing process, if there is a transmitter that is using the same antenna.

Low Noise Amplifier (LNA) provides the first gain in the chain. This is usually implemented as a narrow band block, that should add very little noise to the signal.

Image reject bandstop filter rejects the image band, in order to reduce the effect of interferers and noise coming from the image band.

Mixer 1 performs the first frequency down-conversion. The image reject filter makes sure that the signal is kept clean from noise and interferers. The mixer is usually a wide-band block.

Frequency generator (LO1) generates the first reference signal for the frequency down conversion. This Local Oscillator (LO) could be trimmed by external components and gauges, in order to fine tune the receiver to the right frequency.

Channel select bandpass filter 1 removes the cross products created in the mixer, and the RF and LO leakage that is coupled across the terminals of the mixer. It also attenuates the in-band interferers before the amplification.

IF1 amplifier is the second stage of amplification. Low noise levels are impor- tant in this amplifier, since the signal levels can still be low.

Mixer 2 creates the final frequency down conversion. Now the signal is converted into the region where it can be detected by the demodulator.

Frequency generator (LO2) performs the second frequency down conversion.

The frequency of this second LO can be tuned, in order to compensate for drift and other undesired effects.

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2.1. RADIO RECEIVER ARCHITECTURES 13

Channel select bandpass filter 2 removes the cross products created in the second mixer, and performs further attenuation of in-band interferers.

Demodulator finally converts the received signal to the desired information.

Audio processing amplifies and filters the audio signal to provide the desirable frequency content (Equalization).

The signals through the receiver chain are shown in Fig. 2.2, where it can be seen how the frequency and amplitude in the spectrum changes at each node in Fig. 2.1.

The signals shown in the figure are simplified, and e.g. the effects of the mixer 2 on the LO1 is neglected. Proper care have to be taken in the selection of the LO frequencies, so that the downconversion in mixer 2 of LO1 does not fall into the image bands.

There are two central performance measures in a receiver chain, sensitivity and selectivity. Sensitivity is a measure on how small signals the receiver chain can detect and process. Selectivity is a measure on how well the receiver can distin- guish the signal from a noisy background. The background can, as in part 1 of Fig. 2.2, contain other strong signals that do not contain relevant information for the reception of the desired signal. These signals are called interferers, or blockers.

If the receiver is not properly designed, then these strong signals can saturate the receiver, in such a way that the desired signal cannot be processed, thus blocking the receiver. The linearity of the receiver is also important, in order not to create intermodulation products inside the receiver chain that may block the signal. To avoid these internal blockers to be created, strict specifications are given for the linearity of the blocks, especially at the end of the receiver chain where the signals have been amplified many times. The noise performance, or how much noise the different blocks add to the signal, is also important. This is particularly true for the first blocks in the receiver chain, where the signal levels can be small.

The super heterodyne receiver has previously been implemented in many types of applications, and a few examples are given in e.g. [86].

2.1.2 Homodyne receivers

In contrast to the heterodyne receivers, the homodyne receivers (homo = same, dyne = tone) use the same LO frequency to mix the signal down into zero frequency with one down conversion only. These receivers are also called direct conversion receivers. By using the same LO and RF frequencies, the image frequency problem is avoided. This was originally proposed by Colebroak in 1924 [27]. This architecture made the receiver less complex, since there was only one down conversion, which

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f (Hz) A (V)

1 ^{f (Hz)}

A (V)

2 Band select

filter

f (Hz) A (V)

3 LNA gain

f_s f_s f_s

f_IM1= f_LO1- (f_s- f_LO1)

Demod.

..trees of gr

een, red roses I see them bloo too,

m...

12

f (Hz) A (V)

4 Image reject

f_s ^{f (Hz)}

A (V)

5^f^s f_LO1

f_IM1

f (Hz) A (V)

f_IF1 Down conversion 1

f_LO1

f_IM1

f_IF1= (f_s- f_LO1)

6

f (Hz) A (V)

f_IF1 Channel

select 1 f_LO1

7

f (Hz) A (V)

f_IF1 IF amplifier 1

f_LO1

8

f (Hz) A (V)

f_IF1 Down conversion 2

f_LO1

f_IM2

f_IF2= (f_LO2- f_LIF1)

10 f_LO2

f_IF2 f (Hz)

A (V)

f_IF1

f_LO1

9

f_IM2= f_LO2+ (f_LO2- f_IF1) f_LO2

f_IM2

f (Hz) A (V)

Channel select 2

f_LO1

11 f_LO2

f_IF2

Figure 2.2: The signals through a super heterodyne receiver

required a lower number of components. The implementation of this architecture was not straight-forward, and the central difficulties were e.g. DC offset, and drift and inaccuracy of the components. The invention of the Phase Locked Loop (PLL) by the French scientist Bellescise in 1932 [18] later opened the door for improvement and further deployment of the homodyne receiver. A block diagram of a homodyne receiver for audio applications is shown in Fig. 2.3.

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LNA IF-A

Local Oscillator

Demod. Audio processing

Tuning

1 2 3

4

5 6 7 8 Audio

out

Figure 2.3: The homodyne receiver

Some of the blocks in the homodyne receiver are the same as in the heterodyne re- ceiver, when going through the receiver chain from left to right, e.g. the antenna, the band select filter, the LNA, and the mixer. The other blocks in the chain have small differences:

Frequency generator or LO, is set to the same frequency as the RF signal, in order to mix the received signal directly into the baseband.

Baseband filter provides the majority of the filtering after the mixer, includ- ing the mixer cross products that are not LO leakage to the RF port, and also the in-band interferers that may exist.

Baseband lowpass amplifier provides gain at baseband, and does some fur- ther filtering of the input signal, since it has an inherent low-pass characteristic.

At the end of the chain, the demodulator and the audio processing is a bit different, but the function of the blocks are the same.

The signals processed through the receiver chain are shown in Fig. 2.4, where it can be seen that there is no longer an image frequency problem.

The same performance requirements for sensitivity, linearity, noise and selectivity that applies to the heterodyne receiver also applies for the homodyne receiver.

There are several benefits associated with the homodyne receiver. The decrease in complexity and the absence of the image frequency were already mentioned.

Furthermore, the required low-pass channel filter is easier to implement than the IF band-pass filter, since it requires fewer poles to realize the same out-of-band attenuation. It also operates at lower frequency, which also can reduce the filter order.

The main design challenges for the homodyne receiver are:

Local oscillator stability this was alleviated to some extent by the invention

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f (Hz) A (V)

1 ^{f (Hz)}

A (V)

2 Band select

filter

f (Hz) A (V)

3 LNA

gain

f_s f_s f_s

f (Hz) A (V)

0

Down conversion

f_LO

f_s- f_LO = 0

5

f (Hz) A (V)

0

Baseband low-pass filter

f_LO

6

f (Hz) A (V)

0

Baseband amplification

f_LO

7

Demod.

..for me and you, and I think to myself.

..

8

f (Hz) A (V)

4

f_s f_LO

No image problem

Figure 2.4: The signals through a homodyne receiver

of the PLL.

Flicker noise or 1/f noise is low frequency noise, which is inversely proportional to the frequency [46]. It was originally discovered by Johnson in 1925. It is lower in Bipolar Junction Transistors (BJTs), compared to Complementary Metal Oxide Semiconductor (CMOS) transistors, and it is a concern in homodyne receivers, due to the low frequencies used.

Direct Current (DC) offset mainly comes from the self mixing of the LO signal.

This occurs in the mixer, since there is a leakage of the LO signal to the RF input.

This causes problems like saturation of the baseband filters and amplifiers after the mixer in the receiver chain. It can also cause distortion of the signal since there

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may be information at zero frequency. This can be avoided by making sure that there is sufficient isolation between the ports of the mixer. Sophisticated DC offset cancellation loops can today deal with the varying DC amplitudes which occurs in modern communication systems, due to even order intermodulation distortion [66].

One architecture that avoids the low-frequency issues is the low-IF receiver.

2.1.3 Low IF receivers

The low-IF receiver works like a single conversion super heterodyne receiver, as explained in Section 2.1.1. The signal is down-converted to a low frequency band near DC, and the low frequency problems are thus avoided. There are mainly two benefits of the low-IF receiver; the filter implementation is straight forwards, since the required bandwidths are small, and there is no information in the DC band that can be corrupted with DC offsets, which allows the DC value to be blocked. The signals through a low-IF receiver, which has a similar block diagram as the single conversion super heterodyne receiver shown in Fig. 2.1, are shown in Fig. 2.5. In this figure it can be seen that the IF band is much closer to DC, but it does not overlap DC.

One aspect that has not been discussed much in the chapter so far is the modulation. The early radio stations used Amplitude Modulation (AM) or Frequency Modulation (FM), or variations of these to transmit the radio signals. The strong point of these modulation schemes were that the receiver could be very simple. The downside was that the data rate was very low and sensitive to non-idealities. In addition, a lot of transmitter power was wasted in the carrier signal in AM stations.

As more data was to be transmitted over wireless communication links, new modulation schemes were invented to increase the efficiency. Some of these modulation schemes were analog, e.g. Single Side Band-Suppressed Carrier (SSB-SC), and later some of them were based on the robust digital modulation schemes. Common for both of them was that they required more from the transmitter and the receiver.

The information was no longer only encoded in either phase or amplitude, but in both. In order to differentiate the two, the quadrature receiver (and transmitter) were developed.

2.1.4 Quadrature receivers

The transmitter in most digital modulation schemes, e.g. Quadrature Amplitude Modulation (QAM), use simultaneous phase- and amplitude- modulation. The phase modulation is done with the use of two orthogonal sinusoidal signals (sin and cos). These signals also have to be generated in the receiver to demodulate the signal [88]. A receiver (or a transmitter) that uses these orthogonal references is called a quadrature receiver (or transmitter). A block diagram of a quadrature

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f (Hz) A (V)

1 ^{f (Hz)}

A (V)

2 Band select

filter

f (Hz) A (V)

3 LNA

gain

f_s f_s f_s

f (Hz) A (V)

4 f_s Image

band ^fLO

f_IM

f_IM= f_LO- (f_s- f_LO)

f (Hz) A (V)

f_IF

Down conversion

f_LO

f_IM

f_IF= (f_s- f_LO)

5

f (Hz) A (V)

f_IF

Channel select filter

f_LO

6

f (Hz) A (V)

f_IF

Channel amplification

f_LO

7

Demod.

..I see skies of blue, and clouds

of white.

..

8

Figure 2.5: The signals through a low-IF receiver

receiver is shown in Fig. 2.6, where two parallel receiver chains can be seen. The top receiver chain is called the quadrature receive chain, and it has a 90 degrees phase shift added to it. The second receiver chain is called the in-phase receive path. This allows both the amplitude and the phase information to be extracted.

This can also be used for high-IF and zero-IF receiver architectures. For further information and explanation, look in [88, 101]. A second change from the previous architectures is that the signal processing now has shifted from the analog domain, with equalizers and audio amplifiers, to ADCs, where the signal processing is done in the digital domain.

All of this development happened for many years ago, and it continues with into

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2.2. RADIO RECEIVER TRENDS 19

LNA

VGA

ADC

ADC I

Q LO

90o Baseband

processing

Figure 2.6: The quadrature low-IF receiver

smaller radios having more functionalities. To summarize the trends in modern receiver architectures, a small overview is given.

2.2 Radio Receiver Trends

There are two modern trends in radio receiver architectures, and they are Soft- ware Radio (SR) and Software Defined Radio (SDR). There is no clear distinction between the two approaches today, since many of the definitions comes from the higher levels of the radio standards, and the physical implementation is a level of abstraction where both of these explanations could fit. To make a distinction between the two concepts from a feasibility standpoint, and as a motivation why this work only targets one of the two approaches the following two sections will describe the two terms in more detail.

2.2.1 Software Radio

Software radio is a vision of moving the analog to digital conversion up in frequency and as close to the antenna as possible, in order to reduce the number of analog components that are needed in the design. This concept is illustrated in Fig. 2.7, where three blocks are shown in the receive path, the FEM, the ADC and the signal processing, which in this case is digital down conversion and demodulation.

The strongest benefit of the Software Radio, is that the majority of the RF signal processing is done in the digital domain. Even if this digital part is large and complex, it will decrease in size with new CMOS generations. It can also be set to any frequency within the range of the ADC and FEM. But at the same time, this is also the limitation. The ADCs cannot be made fast enough and sensitive enough to make this vision practical. The analog performance does not scale with technology as the digital does.

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ADC Signal

processing

Digital control

Data out L

₁

NF

_ADC

Figure 2.7: Software Radio receiver

One example of a Software Radio ADC specification is for a WCDMA system.

The noise floor of the antenna needs to be at -99 dBm, to fulfill the Bit Error Rate (BER) requirement for the standard. This allows the total Noise Figure (NF) of the receiver to be 9 dB [10]. This NF specification implies that the noise contributed by the receiver chain, (the FEM and the ADC in this case), can degrade the signal by 9 dB. The ADC in this scenario should have a sampling rate of 4.4 GHz, since the WCDMA band ends at 2.2 GHz. One tutorial on ADC performance related to Noise Figure (NF) is [11]. The NF of the ADC can be determined from the Friis formula [88], where the total noise factor Ftot for this receiver is determined by

Ftot= L1+F2− 1 1/L1

, (2.1)

where Ftotis the noise factor of the receiver (10^{N F/10}), L1 is the loss in the FEM, and F2 is the ADC noise factor. Assume that half of the noise is contributed by the FEM, and half comes from the ADC, then L1 = 10log(10^9/10/2) = 5.9 dB.

This is a high figure for a single-standard FEM, but since this is supposed to be a wide-band component it has to support both Time Division Duplexing (TDD) as well as Frequency Division Duplexing (FDD) it can be a realistic figure. This leaves the other half of the noise to be associated to the ADC, and its noise figure can be determined in the same way

Ftot− L1= F2− 1 1/L1

, (2.2)

which can be simplified to Ftot− L1

L1

+ 1 = F2=7.94 − 3.97

3.97 + 1 = 2.0, (2.3)

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2.2. RADIO RECEIVER TRENDS 21

which is 3 dB. A few more assumptions have to be made regarding the ADC in addition to the sampling rate, and one of them is the full-scale voltage, and its Root Mean Squared (RMS) value. A common ADC has a 1 V peak to peak full-scale voltage, which gives a RMS full-scale voltage of +4 dBm. In order to establish the SNR of the ADC, the input noise is assumed to be only the noise in a 50 Ohm resistor, which is -174 dBm/Hz, and the ADC NF is 3 dB, which implies that the output noise spectral density (NSD) of the ADC is -171 dBm/Hz. Now the SNR of the ADC over the whole band can be determined by [11]

SN R = Pf ull−scale− N SD^ADC− 10 · log fsamp

2

, (2.4)

where SNR is the Signal to Noise Ratio of the ADC, NSDADC is the -171 dBm/Hz from above, Pf ull−scaleis the ADC full scale power, and fsampis the ADC sampling frequency. This results in a SNR of 81.6 dBs. To this some margin needs to be added, since the quantization noise is not completely white, and a margin of 5 dB is suggested [11]. This total dynamic range of about 87 dBs can be achieved by a 14-bit ADC.

The fastest ADCs with 14 bit resolution that is reported has a sampling rate of 125 MHz [3], but the Effective Number Of Bits (ENOB) is only about 12.7 at 62.5 MHz. This ADC still has to increase the sampling frequency by a factor of 35, and to keep the SNDR at the full 14 bits up to 2.2 GHz. The design challenge is huge, and the processes are simply not ready for this kind of ADCs today.

What about Software Defined Radio, what is it, and is it more feasible today?

2.2.2 Software Defined Radio

The second vision for the future is SDR, where there is a single reconfigurable receiver chain that consists of reconfigurable blocks, as shown in Figure 2.8. These blocks have software settings that control to which of the available communication standards the receiver should be adjusted. This is in contrast with the SR, where any frequency could be freely selected. If a new standard is desired, the only mod- ification that has to be made is to download new software to the handset, which describes how the receiver should be configured to receive this new standard.

Let us do the same calculation experiment for WCDMA ADC again. Now the signal is mixed down to baseband, with a zero-IF receiver, and the required dynamic range of the ADC in the last stage of the receiver can be about 10 bits [28, 91], with a sampling frequency of 10 MHz. Such converters exist today.

This implies that the concept of SDR is more feasible today from an ADC design perspective. The ADC design challenges on the other hand occur as the ADC in this receiver needs to be reconfigured between many different standards.

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LNA ADC

Multi- Band Generator

Baseband processing

Digital control

Data out

Figure 2.8: SRD Zero IF receiver

A lot has been mentioned about wireless communication standards, and thus a summary of a few communication standards for handsets, without any intention of being complete, is presented in the following section.

2.3 Wireless communication standards

There is a large variety of available wireless communication standards. A few of the relevant standards for handsets is given in Table 2.1, where a few parameters of the standards is presented [2, 22, 25, 26, 40, 41, 43, 44, 47, 59, 85]. There are a number of abbreviations in the table, where some of them are associated with the names of the standards, and some are the modulation schemes. A list of the abbreviations in the table is given below, where a reference is given to where more information about the abbreviation can be found:

GSM Global Standard for Mobile communications [25].

WCDMA Wideband Code Division Multiple Access [26].

WLAN Wireless Local Area Network [40, 41, 43].

WiMAX Worldwide Interoperability for Microwave Access [44, 47].

UWB Ultra WideBand, defined by the WiMedia Alliance [22]

GFSK Gaussian Frequency Shift Keying [101].

GMSK Gaussian Minimum Shift Keying, used in GSM [25].

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2.3. WIRELESS COMMUNICATION STANDARDS 23

Table 2.1: Wireless standards overview

Name Freq. Bands Data rate Modulation Channel

(MHz) (MBPS) Sep. (MHz)

GSM 890-915 0.270 GMSK 0.2

935-960 1710-1785 1805-1880

Bluetooth 2400-2480 2 GFSK 1

WCDMA 1920-1980 3.84 QPSK 5

2110-2170

WLAN 5150-5350 5.5 to 54 BPSK/OFDM 20

802.11.a 5425-5675 QPSK/OFDM

5725-5875 16/64 QAM/

OFDM

802.11.b 2400-2484 1 to 11 CCK 5

802.11.g 2400-2497 54 BPSK/OFDM 30

QPSK/OFDM

WiMAX 2502-2625 1 to 25 QPSK/OFDMA 1.75 to 20

3500-3800 3 to 50 16 QAM/OFDMA 1.75 to 20 6 to 75 64 QAM/OFDMA 1.75 to 20

UWB 3100-10600 53 to 200 QPSK/OFDM 528

320 to 480 DCM/OFDM

QPSK Quadrature Phase Shift Keying [101].

BPSK Binary Phase Shift Keying [101].

QAM Quadrature Amplitude Modulation [101], there are two variations mentioned in the table, 16 QAM and 64 QAM, where the number only indicates how many points there are in the communication constellation.

OFDM Orthogonal Frequency Division Multiplexing [43, 44].

OFDMA Orthogonal Frequency Division Multiple Access [44].

CCK Complementary Code Keying [41].

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DCM Dual Carrier Modulation [22].

This selection of wireless communication standards presents only a few of the ones that are related to wireless handsets. A more complete list can be found in [2], and to some extent in [59], where more details about some of these standards are presenter.

A few of the wireless communication standards are now more familiar, but what requirements do these standards pose on the ADCs in the back end of the receiver chains?

2.4 Analog to Digital Converters for Multistandard Receivers

ADCs have been designed for Zero-IF receivers for these standards for a number of years. The specifications for these ADCs have been reported with large variations which depend on the variation of the full receiver chain for which they are intended.

A selection of these specifications are summarized in Fig. 2.9 [28, 31, 32, 37, 74, 91, 90, 110].

10⁵ 10⁶ 10⁷ 10⁸ 10⁹

20 40 60 80 100 120

Wireless standard overview

Required Bandwidth (Hz)

Reported ADC DR (dBV)

GSM

BT

WCDMA WLAN

WiMAX

UWB

Figure 2.9: ADC specifications overview for a Zero-IF receiver

These results are presented as a dynamic range-bandwidth figure, which is based on a link budget analysis done as a foundation for the respective work. The span of these standards is huge, from the 100 dB over 100 kHz for GSM, up to 30 dB over 528 MHz for UWB.

The ADCs that are built to meet the requirements of two or more of these standards, are called multistandard ADCs. The dynamic range-bandwidth information presented in Fig. 2.9 stems from papers that are discussing multistandard ADCs,

Reconfigurable Analog to Digital Converters for Low Power Wireless Applications