Design of Robust VLC Codecs
• Motivation
– Variable Length Codes (VLC) are known to give efficient compression
– VLC are also vulnerable in noisy environments because of synchronization losses that comes from bit errors
VLC
Coder Channel VLC
Decoder
Data packet
Bit error
symbol symbol
“Alternative” VLC Code
• Standardized error-resilient coding (MPEG-4)
– Reversible codes (can be decoded from both ends)
– Does not provided true error-resilience (relies on side information in the data)
– “High” computational complexity
• “Alternative” VLC code
– Coder and decoder simplified – Enables high-speed decoding
– Provides error-resilience to the price of less efficiency
“Alternative” VLC Code
• Current status
– HW implementation started – expected to be completed in September 2002
• Expected results
– Comparison to state-of-the art decoder
• HW complexity
• Decoding speed
• Power consumption
Hybrid Golumb (HG) Codes
• Motivation
– Compressed video data are very well modeled by “Generalized Gaussian Disribution”
G G p d f
• Existing VLC codes are sensitive to variations in the source parameters
Source paramters
,,
Hybrid Golumb (HG) Codes
• Our codes (HG)
• Always >70% for a wide range of parameter values
• Always higher efficiency under parameter scaling
• Not best for certain parameter values
– Golomb-Rice (GR) and exp-Golomb (EG) codes performs optimal or near-optimal for small range of values
Robust Window Discriminator for Photon Counting Pixel Detectors
• Goal
– Develop circuit design techniques for low-noise / low-power / area-efficient digital functions
Robust window discrimination
• Event-driven window discrimination
– Does not rely on internal or external timing references – To be used over a wide range of specifications
– All-digital solution (ADWD) – Area-efficient
– Constraints on the design of the integral discriminators – built-in hysteresis
Reported in: Bengt Oelmann, Munir Abdalla, and Mattias O'Nils,
On-going design work
• Goal:
– Design and fabricate photon-counting pixel
– Characterize pixels that are based on the design techniques that we propose
Shift_clk Low_th
High_th
Enable_count Read_in
Read_out ADWD
PRESCALE 7 bit
MUX LFSR
10 bit
Prescale-LFSR configuration
Low-power Finite-State Machine Design
• Goal:
– Develop optimization procedures and
implementation architectures for low-power FSM
• Current status
– “Extensive pre-study” completed
• Design model its formal description
• Procedures for “state bundling” and state encoding
• HW Implementation architecture
Future work on FSMs
• Demonstrators
– Implement the optimization procedures in a CAD-tool
– Use the CAD-tool in different application areas
CAD-tool
LIFS2
Microprocessor Data Digital Signal
