high aspect ratio tsvs fabricated by magnetic self-assembly of gold-coated nickel wires

High aspect ratio TSVs fabricated by magnetic self-assembly of gold-coated nickel wires

KTH Royal Institute of Technology Osquldas väg 10, 100 44 Stockholm, Sweden

email: andreas.fischer@ee.kth.se Abstract

Three-dimensional (3D) integration is an emerging technol- ogy that vertically interconnects stacked dies of electronics and/or MEMS-based transducers using through silicon vias (TSVs).

TSVs enable the realization of devices with shorter signal lengths, smaller packages and lower parasitic capacitances, which can re- sult in higher performance and lower costs of the system. In this paper we demonstrate a new manufacturing technology for high-aspect ratio (> 8) through silicon metal vias using magnetic self-assembly of gold-coated nickel rods inside etched through- silicon-via holes. The presented TSV fabrication technique en- ables through-wafer vias with high aspect ratios and superior elec- trical characteristics. This technique eliminates common issues in TSV fabrication using conventional approaches, such as the metal deposition and via insulation and hence it has the potential to re- duce significantly the production costs of high-aspect ratio state- of-the-art TSVs for e.g. interposer, MEMS and RF applications.

Introduction

During the past decades, hybrid integration of IC and MEMS technology has been dominated by 2-D approaches, resulting in Multi-Chip Modules (MCM) where different dies are integrated on a single substrate, and System-on-Chip (SoC) solutions where different functionalities are merged onto one die. CMOS and MEMS processing are both well-established and cost-efficient base technologies that are characterized by short development times, low fabrication costs and high yields. Separate manu- facturing of CMOS integrated circuit dies and MEMS dies and their subsequent integration into a System-in-Package (SiP) offers high versatility and low process costs, and thus is an attractive alternative to SoC solutions. Especially 3D-integrated System in Package (3D-SiP) solutions, which are based on vertical chip stacking, are a general trend in many integration approaches. Not only do 3D-SiPs decrease costs by reducing the volume and weight of the package, but they also improve system performance through enhanced signal transmission speed and lower power consumption which is of importance for various demanding applications [1, 2]. This is due primarily to the shorter signal path lengths and lower capacitive, resistive and inductive parasitic components that are enabled by TSVs [3].

3D-SiP implementations require vertical interconnects through selected dies in the stack in order to connect their functional layers. Large development efforts for the realization of reliable and cost-efficient TSVs are currently ongoing and the first commercially available devices such as MEMS inertial sensors

The structure and hence the fabrication of TSVs can be roughly divided into three major elements: a vertical hole through the substrate, a conductive core and a dielectric layer acting as an insulator between conductor and substrate. The exact design of the via and the fabrication process flow depends very much on the application.

Typical TSV diameters vary between a few microns [2, 7]

and several hundreds of microns [8, 9]. Basic via designs are either based on solid or lined metallizations for the vertical conductor. TSVs can have either straight [7–11] or tapered sidewall profiles [12, 13] as well as combinations of both [1, 14].

Various methods for the formation of via holes exist and can be categorized into dry etching [1, 7, 8, 10–14], wet etching [14] and drilling processes [4]. The majority of TSVs have an aspect ratio between 1 and 10. The most common techniques and challenges for the fabrication of the main TSV structures are discussed in the following sub-sections.

Via Holes — Deep Reactive Ion Etching (DRIE) is by far the most commonly used technology to form the TSV hole.

DRIE has an excellent process controllability and is capable of creating high aspect ratio vias with specific sidewall profiles and topographies. The etch rate of DRIE is aspect ratio dependent (ARDE) and may cause several topographic imperfections on the sidewalls such as scalloping, caused by alternating etch- and passivation-steps, which results in corrugated sidewalls.

By using state-of-the-art DRIE equipment, these effects can be minimized [12] and adopted to the demands of subsequent insulation, barrier and seed-layer deposition steps.

Laser ablation is an emerging low-cost and high-speed process for drilling TSV holes as it benefits from the absence of any litho- graphic process steps and is agnostic to different materials. This results in high process and design flexibility and thus, potentially lower overall costs compared to DRIE [4, 15]. Laser ablation however suffers from a high local thermal load, introduction of crystal defects and particle generation around the perimeter of the drilled via hole. Additional cleaning steps are therefore required and reliability issues may arise due to induced stresses on pores and micro-cracks [15, 16].

Via Insulator — Chemical Vapour Deposition (CVD) is a well-established CMOS process with moderate temperature requirements [1, 2, 7, 13] and is therefore the most commonly used method for a direct deposition of silicon dioxide or silicon

+LJK$VSHFW5DWLR769V)DEULFDWHGE\0DJQHWLF6HOIDVVHPEO\RI*ROGFRDWHG1LFNHO:LUHV

based polymers [8, 13], silicone [13] or Parylene [11] is also considered as viable option. Polymers, especially low-k types with a lower relative permittivity compared to silicon dioxide, are very attractive for the realization of TSVs with improved electrical characteristics [8]. In addition, polymers can further act as a buffer for thermo-mechanical stresses caused by coefficient of thermal expansion (CTE) mismatches [11, 18] as their Young’s modulus is approximately two orders of magnitude lower as compared to silicon dioxide or silicon nitride.

Via Conductor — The via metallization step is the most crit- ical and often most costly part of the via fabrication. Established processes are electrodeposition of copper [7, 8, 11, 13, 14, 18], CVD of tungsten [2, 19], CVD of polysilicon [2, 12] and the use of low-resistivity silicon [10]. Especially electrodeposition of copper, being a very well-established semiconductor process, is used by many research groups and implemented in most commer- cialized devices containing TSVs. Electrodeposition of copper benefits from widely available tool vendor support and process maturity as well as being amenable to processing at close to room temperature, but suffers due to its complexity in terms of process controllability, reliability and throughput [4]. In particular, high aspect ratio TSVs with void-free conductive metal cores are diffi- cult to implement [7]. Alternative approaches to plating processes have therefore been investigated, such as filling with conductive metal pastes [1, 20, 21], solder [22, 23] as well as the use of wire- bonded gold [9].

Concept of Self-Assembled TSVs

In this work we present the magnetic self-assembly of con- ductive via cores into through-silicon via holes. Magnetism as a non-contact force enables a controlled manipulation of ferromag- netic features over long-distances and is insensitive to the sur- rounding medium and independent of details of the surface chem- istry. Magnetic fields can have high energy densities and can in- fluence feature sizes from macro- to nano-scale. These advanta- geous characteristics are very attractive and have been reported in various assembly approaches [24]. A proof-of-concept of self- assembled pure nickel-TSVs has been shown by the authors ear- lier [17]. As depicted in figure 1 a and b, pre-formed ferromag- netic nickel rods are magnetically assembled into deep etched via holes. For the via insulation the thermosetting polymer Benzo- cyclobutene (BCB) is used, as shown in figure 1 c. This low-k insulator material has excellent electrical characteristics and can be filled void-free into trenches with high aspect ratios [25]. This method enables high aspect ratio vias with an inherently void-free conductor and insulator. This method has also been adopted for the assembly of SMD capacitors into through-silicon holes [26].

Even though the DC resistances of commonly used conduc- tive materials such as copper, gold, aluminum, or tungsten, are within a very close range to those of ferromagnetic materials like cobalt, nickel, or iron, there is an enormous discrepancy regard- ing their performance for high-frequency signal transmission as depicted in figure 2. Ferromagnetic materials show very poor RF

(a) (b)

Nickel

SiO2

Siliconn el BCBB

(c)

Figure 1: Via formation concept [17]: a) The via hole is formed by DRIE stopping on a silicon dioxide layer. b) A conductive, ferromagnetic nickel core is placed in the via hole by magnetic assembly. c) The remaining hollow space in the via cavity is filled with the thermosetting polymer Benzocyclobutene (BCB).

conductibility characteristics with sheet resistances that are two orders of magnitude greater than common TSV conductor mate- rials.

0 20 40 60 80 100 120

10⁻³ 10⁻² 10⁻¹ 10⁰ 10¹ 10²

Frequency [GHz]

Sheet Resistance [Ω/square]

Iron Nickel Cobalt Tungsten Aluminium Gold Copper

Figure 2: Simulated sheet resistances for various conductive ma- terials in dependence of the frequency. The values for ferromag- netic materials, such as Iron, Nickel, and Cobalt are almost two orders of magnitude bigger than the values for Tungsten, Alu- minium, Gold, and Copper.

In this work we present an automated magnetic assembly pro- cess for the fabrication of TSVs that are adopted for the transmis- sion of high frequency RF signals. Two materials are therefore combined for the conductive via core. Ferromagnetic nickel is used for the assembly process and a gold layer that is coated on the nickel wire serves as conductor for the RF signal. Due to the skin-effect the current density of high-frequency signals in a

conductor is largest close to the surface and hence most of the cur- rent flows along the outer perimeter of a circular TSV conductor.

Therefore it is sufficient to coat a thin layer of gold on a nickel core in order realize a TSV with good electrical characteristics for RF signals.

Wire preparation

The conductive cores of the TSVs are fabricated previous to the assembly. The electric and mechanical quality of the final via connection as well as the manufacturability of the wire assembly is strongly dependent on a thorough preparation of the conductive via cores. The preparation is divided in two steps, first the coat- ing of a nickel wire with gold by electroplating and second the cutting of the gold-coated nickel wire to a defined length. Crucial requirements are perfectly straight nickel wires and a very precise control of the gold layer thickness. A too thick gold layer would result in an enlarged diameter of the nickel rods which would then not fit into the via holes anymore. A distortion of the wires would have a similar effects since the wires would get stuck half way into the holes.

In order to ensure a defined fixation and a reliable electri- cal contact of the wire for the electrodeposition process, a carrier frame for the wire was manufactured, as depicted in figure 3 a.

The carrier is made of chemically resistant polypropylene (PP) and holds approximately 2.5 m of nickel wire. The wire that was used for this experiment was Nickel 270 with a purity of 99.97 % and a diameter of 35 µm. Prior to the gold-electroplating step, the native oxide on the surface of nickel wire was removed by a 10 % HCl dip. The gold-coating was performed with the elec- troplating agent Aurotron H 200 (Atotech GmbH, Germany) at a deposition rate of approximately 0.3 µm/min.

In order to cut the gold-coated nickel wire into rods of a de- fined length, a wire cutting process was developed. The carrier frame with the gold-coated nickel wires was therefore placed on a carrier wafer. As shown in figure 3 b, the wires were fixated with blue tape at the outer perimeter of the carrier wafer before the frame and the excess wire was removed. In order to fixate the wires on the carrier wafer and protect them from any deformation and burr creation during the cutting process a layer of AZ^�R 4562 photoresist was spin-coated on the carrier wafer at 1000 rpm for 30 s. As depicted in figure 3 c, the nickel wires were fully embed- ded in the photoresist matrix. A DAD 320 (DISCO Cooperation, Japan) wafer dicing tool was used to cut the wires to a length of 350 µm. The accurate alignment of the dicing machine allowed for perfectly perpendicular cuts and the length of the rods could be precisely controlled by the step size of the dicing blade. Sub- sequently the gold-coated nickel rods could easily be released by dissolving the resist layer with acetone. Since this process allows for a very precise cutting of many wires in parallel, a large num- ber of nickel rods can be manufactured in a short time, e.g. one process run of plating, mounting, cutting and releasing produces approximately 4000 nickel rods.

TSV Fabrication

The detailed fabrication process for the TSVs is depicted in figure 4 and starts with 350 µm thick double-sided polished, p-type silicon wafers with a diameter of 100 mm and a resistivity of 5000 − 8500 Ωcm. A 2 µm thick silicon dioxide layer was created by thermal wet oxidization at 1100^◦C on both sides. The silicon dioxide acts both as a hard mask for the DRIE step and as an electrical insulator for the metal lines, which will finally connect the via on the front- and back-side of the substrate. A standard lithography on the front-side of the substrate defines the circular openings for the vias. The silicon dioxide is dry-etched by RIE (figure 4 b). As depicted in figure 4 c, a Bosch DRIE process creates via holes with a diameter of 42 µm and straight side walls. The etch stops at the silicon dioxide on the bottom of the cavity. A subsequent thermal oxidation ensures an electrical insulation of the via sidewalls.

As depicted in figure 4 e, an excess amount of the gold- coated nickel wires is then randomly placed on the front-side of the substrate. By magnetic manipulation with a permanent magnet from the back-side, the nickel wires are aligned normal to the surface (figure 4 f). A lateral movement of the magnet drags the wires along the surface and forces them into the via cavities (figure 4 g). For this magnetic assembly process a robotic setup was devised and constructed based on a wafer handler robot.

Wafer Photo-

resist

Ni Wire Dicing

Groove Blue Tape Ni Wire

c)

a) b)

Figure 3: After the gold plating (a), the wires are cut by transfer- ring the nickel wires to a dummy wafer (b). The wafer is then spin- coated with photoresist (c). Embedded in this protective layer of photoresist, the wires can be cut with a dicing tool, without the risk of bending or loosing the wires. (c) shows the top and cross- sectional views of a cut nickel wire, still embedded in photoresist.

By dissolving the resist layer the wires can then be released.

(a) (b) (c)

(e) (f) (g)

Silicon Silicon Oxide Nickel

BCB Gold

(j) (i)

(h) Via FormationVia Filling by Magnetic Assembly

Via Contacts

N S

(d)

(k)

N S

N SMagnet

Figure 4: The TSV fabrication in three main steps: (a - d) Formation of via holes by DRIE. (e - h) Autonomous magnetic assembly of gold-coated nickel TSV cores and the application of BCB as an insulation layer. (i - k) Opening of the vias on back-side as well as deposition and patterning of the transmission lines.

Figure 5 shows a schematic depiction of the robot arm that was modified in order to mount the cubic permanent magnet with an edge length of 5 mm. This device enables a free movement of the magnet with three degrees of freedom which can be utilized to program an assembly motion to drag the nickel wires into the cavities. Also depicted in figure 5 is a camera which is mounted directly above the magnet and faces the front-side of the substrate. It is used to optically inspect the substrate surface and to monitor the assembly process.

x y

z

Permanent Magnet Wires

Robot Arm Camera

Wafer

Figure 5: Assembly robot setup: The assembly arm consists of a permanent magnet mounted on an aluminum sheet and a camera above the magnet.

The via cavities are subsequently filled with the thermoset- ting polymer BCB CYCLOTENE^�R 3022-46 (figure 4 g). In order to reduce the viscosity of the polymer, the substrate is placed on a hotplate with a temperature of 60^◦C before the polymer is manually applied with a syringe. As the polymer is not spin-coated the resulting polymer layer has a non-uniform thickness on the order of 100 − 150 µm. The subsequent hard-curing of the BCB is performed on a hotplate using the temperature profile according to the manufacturer’s standard process procedures [27]. The curing procedure was performed in a vacuum environment at 0.02 mbar in order to prevent any void formation in the polymer. A grinding and polishing step removes remaining nickel and BCB from the surface of the substrate (figure 4 i). A subsequent lithography and RIE of the silicon dioxide and BCB residues opens the contact area of the via on the back-side of the wafer, as depicted in figure 4 j. Two consecutive TiW / Au depositions (50 / 500 nm) on both sides of the wafer interconnects the nickel/gold core of the via. A lithography, wet Au etch and dry TiW etch define the transmission lines (figure 4 k) of the RF test structures.

Experimental Results

Figure 6 shows a scanning electron microscope (SEM) image of a gold-coated nickel wire. In order to evaluate the thickness of the electroplated gold layer, a small pit was formed on the wire surface by focused ion beam (FIB) milling. The gold thickness was measured to be 1.7 µm. The surface of the gold film has a rough surface, which is characteristic for electro-deposited layers.

Gold Nickel

Au-coated Ni wire

Figure 6: SEM image of a gold-coated nickel wire. Inset: Cross- section of the Ni/Au interface, generated by focused ion beam (FIB) milling.

A first unsuccessful fabrication run of non-functional TSVs was investigated by cross-section grinding and subsequent inspec- tion with a scanning electron microscope (SEM). As depicted in Figure 7, the lower part of the conductive via core is not in contact with the metallization on the back-side. The failure was caused by the DRIE that produced a slightly closing profile of the via side- walls. As a result, the diameter of the lower part of the via was smaller than the diameter of the gold-coated nickel rods. This pre- vented the conductive via core from a complete assembly down to the silicon oxide membrane. This issue was addressed by an in- creased etch time and subsequent fabrication runs were success- ful. Figure 7 indicates that the filling with BCB could be success- fully conducted without any visible air-voids or defects after the complete hard curing procedure. Also, the nickel wire is inher- ently void-free.

Au SiO

BCB Au Ni SiO

Au

Figure 7: SEM image of a cross section of a TSV with an aspect ratio of 8. It shows both, a void-free via core and a void-free BCB-filling.

For evaluating the RF performance of the gold-coated nickel wire TSV, the proposed via structures are employed as vertical through-wafer interconnections of the micromachined coplanar-waveguide (CPW) transmission lines implemented on the front- and back-side of a high-resistivity silicon substrate (5000-8500Ωcm) as shown in figure 8. The gold CPW has a signal line width of 120 µm and a gap of 60 µm, while the length of the transmission is 2400 µm, thus the unwanted signal cou- pling between the input and output port is avoided. To extract the transmission loss from the test structure, a reference CPW transmission line without any interconnections was fabricated on the front-side of the wafer. The RF measurement results indi- cate that the CPW integrated with gold-coated nickel wire inter- connections offers an excellent RF performance for a very wide band from DC to 66 GHz, which is a much larger operation fre- quencies as compared to other reported TSVs for RF applica- tions [8, 28, 29]. The measured maximum return loss at 66 GHz is lower than −10 dB, while the maximum insertion loss is better than −4.62 dB. As compared to the reference CPW transmission with the same length, a single section of the gold-coated nickel wire interconnection has an insertion loss of only −0.75 dB.

Si

Front-Side Back-Side TSV SiO2 Au

Ni BCB

Signal Trace

Ground Trace a)

b)

Figure 8: Cross section (a) and top-view (b) of the micromachined coplanar-waveguide (CPW).

Conclusions

We demonstrated a novel manufacturing technology for high- aspect ratio (> 8) through silicon metal vias based on the magnetic self-assembly of gold-coated nickel wires. The presented TSV approach offers an excellent RF performance up to 66 GHz.

Acknowledgements

This work has been funded by the European Research Coun- cil (ERC) through the Starting Grant (277879). The authors also would like to thank Umer Shah and Nora Heinig for their collab- oration and technical support.

References

[1] M. Motoyoshi, “Through-silicon via (tsv),” Proceedings of the IEEE, vol. 97, no. 1, pp. 43 –48, jan. 2009.

[2] M. Koyanagi, T. Fukushima, and T. Tanaka, “High-density through silicon vias for 3-d lsis,” Proceedings of the IEEE, vol. 97, no. 1, pp. 49 –59, jan. 2009.

[3] R. Weerasekera, D. Pamunuwa, L.-R. Zheng, and H. Ten- hunen, “Two-dimensional and three-dimensional integra- tion of heterogeneous electronic systems under cost, perfor- mance, and technological constraints,” Computer-Aided De- sign of Integrated Circuits and Systems, IEEE Transactions on, vol. 28, no. 8, pp. 1237 –1250, aug. 2009.

[4] P. Garrou, C. Bower, and P. Ramm, Handbook of 3D Inte- gration Technology and Application of 3D Integration Cir- cuits. Wiley, KGaA, 2008.

[5] J. Lau, R. Lee, M. Yuen, and P. Chan, “3d led and ic wafer level packaging,” Microelectronics International, vol. 27, no. 2, pp. 98–105, 2010.

[6] M. Lapisa, G. Stemme, and F. Niklaus, “Wafer-level hetero- geneous integration for moems, mems, and nems,” Selected Topics in Quantum Electronics, IEEE Journal of, vol. 17, no. 3, pp. 629 –644, may-june 2011.

[7] M. Wolf, T. Dretschkow, B. Wunderle, N. Jurgensen, G. En- gelmann, O. Ehrmann, A. Uhlig, B. Michel, and H. Reichl,

“High aspect ratio tsv copper filling with different seed lay- ers,” in Electronic Components and Technology Conference, 2008. ECTC 2008. 58th, may 2008, pp. 563 –570.

[8] S. W. Ho, S. W. Yoon, Q. Zhou, K. Pasad, V. Kripesh, and J. Lau, “High rf performance tsv silicon carrier for high fre- quency application,” in Electronic Components and Tech- nology Conference, 2008. ECTC 2008. 58th, may 2008, pp.

1946 –1952.

[9] A. Fischer, M. Grange, N. Roxhed, R. Weerasekera, D. Pamunuwa, G. Stemme, and F. Niklaus, “Wire-bonded through-silicon vias with low capacitive substrate coupling,”

Journal of Micromechanics and Microengineering, vol. 21, no. 8, p. 085035, 2011.

[10] M. Rimskog, “Through wafer via technology for mems and 3d integration,” in Electronic Manufacturing Technology Symposium, 2007. IEMT ’07. 32nd IEEE/CPMT Interna- tional, oct. 2007, pp. 286 –289.

[11] D. Tezcan, F. Duval, H. Philipsen, O. Luhn, P. Soussan, and B. Swinnen, “Scalable through silicon via with poly- mer deep trench isolation for 3d wafer level packaging,” in Electronic Components and Technology Conference, 2009.

ECTC 2009. 59th, may 2009, pp. 1159 –1164.

[12] D. Tezcan, K. De Munck, N. Pham, O. Luhn, A. Aarts, P. De Moor, K. Baert, and C. Van Hoof, “Development of

vertical and tapered via etch for 3d through wafer intercon- nect technology,” in Electronics Packaging Technology Con- ference, 2006. EPTC ’06. 8th, dec. 2006, pp. 22 –28.

[13] D. Tezcan, N. Pham, B. Majeed, P. De Moor, W. Ruythooren, and K. Baert, “Sloped through wafer vias for 3d wafer level packaging,” in Electronic Com- ponents and Technology Conference, 2007. ECTC ’07.

Proceedings. 57th, 29 2007-june 1 2007, pp. 643 –647.

[14] P. Nilsson, A. Ljunggren, R. Thorslund, M. Hagstrom, and V. Lindskog, “Novel through-silicon via technique for 2d/3d sip and interposer in low-resistance applications,” in Electronic Components and Technology Conference, 2009.

ECTC 2009. 59th, may 2009, pp. 1796 –1801.

[15] R. Landgraf, R. Rieske, A. Danilewsky, and K.-J. Wolter,

“Laser drilled through silicon vias: Crystal defect analysis by synchrotron x-ray topography,” in Electronics System- Integration Technology Conference, 2008. ESTC 2008. 2nd, sept. 2008, pp. 1023 –1028.

[16] Y.-H. Chen, W.-C. Lo, and T.-Y. Kuo, “Thermal effect characterization of laser-ablated silicon-through intercon- nect,” in Electronics Systemintegration Technology Confer- ence, 2006. 1st, vol. 1, sept. 2006, pp. 594 –599.

[17] A. Fischer, N. Roxhed, T. Haraldsson, N. Heinig, G. Stemme, and F. Niklaus, “Fabrication of high aspect ratio through silicon vias (tsvs) by magnetic assembly of nickel wires,” in Micro Electro Mechanical Systems (MEMS), 2011 IEEE 24th International Conference on, jan. 2011, pp. 37 – 40.

[18] K. Lu, X. Zhang, S.-K. Ryu, J. Im, R. Huang, and P. Ho, “Thermo-mechanical reliability of 3-d ics containing through silicon vias,” in Electronic Components and Tech- nology Conference, 2009. ECTC 2009. 59th, may 2009, pp.

630 –634.

[19] H. Kikuchi, Y. Yamada, A. M. Ali, J. Liang, T. Fukushima, T. Tanaka, and M. Koyanagi, “Tungsten through-silicon via technology for three-dimensional lsis,” Japanese Journal of Applied Physics, vol. 47, no. 4, pp. 2801–2806, 2008.

[20] Y.-H. Ham, D.-P. Kim, K.-S. Park, Y.-S. Jeong, H.-J. Yun, K.-H. Baek, K.-H. Kwon, K. Lee, and L.-M. Do, “Dual etch processes of via and metal paste filling for through silicon via process,” Thin Solid Films, vol. 519, no. 20, pp. 6727 – 6731, 2011.

[21] S. Lee, R. Hon, S. Zhang, and C. Wong, “3d stacked flip chip packaging with through silicon vias and copper plating or conductive adhesive filling,” in Electronic Components and Technology Conference, 2005. Proceedings. 55th, may- 3 june 2005, pp. 795 – 801 Vol. 1.

[22] Y.-K. Ko, H. T. Fujii, Y. S. Sato, C.-W. Lee, and S. Yoo,

“High-speed tsv filling with molten solder,” Microelectronic Engineering, vol. 89, no. 0, pp. 62 – 64, 2012.

[23] J. Gu, W. Pike, and W. Karl, “A novel capillary-effect- based solder pump structure and its potential application for through-wafer interconnection,” Journal of Micromechanics and Microengineering, vol. 19, no. 7, p. 074005, 2009.

[24] M. Mastrangeli, S. Abbasi, C. Varel, C. Van Hoof, J. Celis, and K. Böhringer, “Self-assembly from milli- to nanoscales:

methods and applications,” Journal of Micromechanics and Microengineering, vol. 19, no. 8, p. 083001, 2009.

[25] H. Mahfoz Kotb, K. Isoird, F. Morancho, L. Théolier, and T. Do Conto, “Filling of very deep, wide trenches by benzo- cyclobutene polymer,” Microsystem Technologies, vol. 15, pp. 1395–1400, 2009.

[26] J. Hoo, K. Park, C. Varel, R. Baskaran, and K. Böhringer,

“Wafer-level high density integration of surface mount tech- nology components in through-silicon trenches,” in Micro Electro Mechanical Systems (MEMS), 2012 IEEE 24th In- ternational Conference on, jan. 2012, pp. 373–376.

[27] T. D. C. Company. Processing procedures for cyclotene 3000 series resins, p 5. [Online]. Available: http://www.

dow.com/cyclotene/docs/cyclotene_3000_dry_etch.pdf [28] J. Tian, J. Iannacci, S. Sosin, R. Gaddi, and M. Bartek, “Rf-

mems wafer-level packaging using through-wafer via tech- nology,” in Electronics Packaging Technology Conference, 2006. EPTC ’06. 8th, dec. 2006, pp. 441 –447.

[29] J. Wu and J. del Alamo, “Fabrication and characterization of through-substrate interconnects,” Electron Devices, IEEE Transactions on, vol. 57, no. 6, pp. 1261 –1268, june 2010.