Institutionen för systemteknik
Department of Electrical Engineering
Examensarbete
Study on Zero-Crossing-Based ADCs
for Smart Dust Applications
Examensarbete utfört i Elektroniksystem vid Tekniska högskolan vid Linköpings universitet
av
Shehryar Khan and Muhammad Asfandyar Awan LiTH-ISY-EX--11/4491--SE
Linköping 2011
Department of Electrical Engineering Linköpings tekniska högskola
Linköpings universitet Linköpings universitet
Study on Zero-Crossing-Based ADCs
for Smart Dust Applications
Examensarbete utfört i Elektroniksystem
vid Tekniska högskolan i Linköping
av
Shehryar Khan and Muhammad Asfandyar Awan LiTH-ISY-EX--11/4491--SE
Handledare: Supervisor
J Jacob Wikner isy,Linköpings universitet
Examinator: Examiner
J Jacob Wikner isy, Linköpings universitet Linköping, 18 August, 2011
Avdelning, Institution
Division, Department
Division of Electronics Systems Department of Electrical Engineering Linköpings universitet
SE-581 83 Linköping, Sweden
Datum Date 2011-008-18 Språk Language Svenska/Swedish Engelska/English Rapporttyp Report category Licentiatavhandling Examensarbete C-uppsats D-uppsats Övrig rapport
URL för elektronisk version
http://www.es.isy.liu.se http://www.es.isy.liu.se ISBN — ISRN LiTH-ISY-EX--11/4491--SE
Serietitel och serienummer
Title of series, numbering
ISSN
—
Titel
Title Study on Zero-Crossing-Based ADCs
for Smart Dust Applications
Författare
Author
Shehryar Khan and Muhammad Asfandyar Awan
Sammanfattning
Abstract
The smart dust concept is a fairly recent phenomenon to engineering. It as-sumes monitoring of a real natural environment in which motes or smart dust machines swarm in collective and coordinate information among themselves and/ or to a backend control platform. In analog mixed signal field work on such devices is gaining momentum such that it is conceived to be one of the emerging fields in technology, and work was only possible once the technology for fabrication touched the nanoscale regions.
Smart dust network involves remote devices connected in a hive sensing burst type datum signals from the environment and relaying information amongst themselves in an energy efficient manner to coordinate an appropriate response to a detected stimulus. The project presumed a RF based communication strategy for coordina-tion amongst the devices through a wireless medium. That is less susceptible to stringent requirements of LOS and a base band processing system that comprised of an environment sensor, an AFE module, an ADC, a DSP and a DAC. Essentially a 10 bit, 2 Mega Hertz MHz pipelined ADC implemented in a STM 65 nm technology. The ADC benefits the smart dust device in allowing it to process data in an energy efficient way and also focusing on reduced complexity as its design feature. While it differs in the other ADC of the system by operating at a higher frequency and assuming a different design philosophy assuming a coher-ent system sensitive to a clock. The thesis work assumes that various features of energy harvesting, regulation and power management present in the smart dust mote would enable the system to contain such a diverse ADC. The ADCs output digital datum would be compatible to the rest of the design modules consisting mainly of DSP sections. The ADC novelty is based on the fact that it removes the necessity of employing a high power consuming OpAmp whose design parameters become more complex as technology scales to the nanoscale era and further down. A systematic, bottom up, test driven approach to design is utilized and various behaviours of the system are captured in Cadence design environment with verilog to layout models and MATLAB and Simulink models.
Nyckelord
Keywords smart dust, Comparator Based Switched Capacitor (CBSC), Zero Crossing Based
Abstract
The smart dust concept is a fairly recent phenomenon to engineering. It assumes monitoring of a real natural environment in which motes or smart dust machines swarm in collective and coordinate information among themselves and/ or to a backend control platform. In analog mixed signal field work on such devices is gaining momentum such that it is conceived to be one of the emerging fields in technology, and work was only possible once the technology for fabrication touched the nanoscale regions.
Smart dust network involves remote devices connected in a hive sensing burst type datum signals from the environment and relaying information amongst themselves in an energy efficient manner to coordinate an appropriate response to a detected stimulus. The project presumed a RF based communication strategy for coordina-tion amongst the devices through a wireless medium. That is less susceptible to stringent requirements of LOS and a base band processing system that comprised of an environment sensor, an AFE module, an ADC, a DSP and a DAC.
Essentially a 10 bit, 2 Mega Hertz MHz pipelined ADC implemented in a STM 65 nm technology. The ADC benefits the smart dust device in allowing it to process data in an energy efficient way and also focusing on reduced complexity as its design feature. While it differs in the other ADC of the system by operating at a higher frequency and assuming a different design philosophy assuming a coherent system sensitive to a clock. The thesis work assumes that various features of energy harvesting, regulation and power management present in the smart dust mote would enable the system to contain such a diverse ADC. The ADCs output digital datum would be compatible to the rest of the design modules consisting mainly of DSP sections. The ADC novelty is based on the fact that it removes the necessity of employing a high power consuming OpAmp whose design parameters become more complex as technology scales to the nanoscale era and further down. A systematic, bottom up, test driven approach to design is utilized and various behaviours of the system are captured in Cadence design environment with verilog to layout models and MATLAB and Simulink models.
Acknowledgments
First of all, we would like to Thank the Almighty for helping us sustain our efforts in weaving together some insights from the mosaic of the rational and irrational world of Integrated Chip (IC) design.
Secondly, we would like to thank J Jacob Wikner, our supervisor for this thesis work, a man of supreme inertia with an iconoclastic laser sharp thinking ability in the realm of mixed signal design who guided our search in understanding the inner mechanisms of our ADC project. He also possesses an almost poetic documentation ability which we tried to sample at our best inherent frequency.
Also we would like to thank Venkata Narasimha Manyam and Qazi Syed Wajahat Ali for their opposition of our thesis, their opposition was fair and gave us solid material to work on. We would also like to extend a special thank you to Dhruv Chhetri for his support throughout academics and most fondly for his frequent invitations to his generous and creative kitchen. And we must remember the camaraderie shared in the “Signal och Bild” room with Murad Kabir Nipun, Sajib Roy, Tanvir Ahmad and Mohammad Lababidi.
Also I, Shehryar Khan, would like to thank my mother and my sister, for their constant support and encouragement throughout my study period and always cheering me up when things went gloomy. I would also like to thank my friend Adeel-ur-Rehman who I constantly ignored but he still had a big enough heart to tolerate such weird behaviour. I would like to thank Waqas Zafar of KTH university for giving me the tip of coming to Sweden for my masters education. And lastly, I would like to thank Asfandyar Awan for his magnificent amount of patience for the length of the thesis.
I hope this thesis work to be a stepping stone for all the nafs-e-la-mutmoena mixed signal design engineers that are to follow in the yellow brick road leading to the world of IC design.
Contents
1 Introduction 15
1.1 Thesis Organization . . . 15
1.2 Smart Dust Specification . . . 16
1.3 Thesis Objective . . . 16
1.4 Motivation for ADC . . . 16
1.5 Zero-Crossing Based Detector ADC . . . 18
1.6 Conventional OpAmp Versus ZCBC Systems . . . 19
1.7 Results of ZCBC Gain Stage . . . 20
2 Smart Dust - An Overview 23 2.1 Smart Dust: Distributed Sensors . . . 23
2.2 Smart Dust - Hierarchical Network . . . 25
2.3 Smart Dust: Characteristics . . . 25 ix
x Contents
2.4 Smart Dust: ADC . . . 26
2.5 Smart Dust: subsystems . . . 27
3 ADC Basic Architectures 29 3.1 ADC Configurations . . . 30
3.1.1 Nyquist Rate ADC . . . 31
3.1.2 Oversampled ADC . . . 32
3.2 Successive Approximation ADC Architecture . . . 32
3.3 Pipeline ADC . . . 35
3.4 Flash ADC . . . 38
3.5 Sigma Delta ADC Converters . . . 40
4 Ultra Low Power ADC 43 4.1 Smart Dust ADC Performance Metrics . . . 44
4.1.1 Accuracy . . . 44
4.1.2 Resolution . . . 44
4.1.3 Aliasing . . . 45
4.1.4 Quantization Error . . . 45
4.1.5 Offset and Full-Scale Error . . . 45
Contents xi
4.1.7 Missing Codes . . . 46
4.1.8 Signal to Noise Ratio . . . 46
4.1.9 Signal to Noise and Distortion Ratio . . . 47
4.1.10 Spurious Free Dynamic Range . . . 47
4.1.11 Dynamic Range . . . 47
4.1.12 Effective Number of Bits . . . 48
4.2 Quantization . . . 48
4.3 Leakage . . . 48
4.4 Figure of Merit . . . 50
4.5 Coherent Sampling . . . 51
5 Zero Crossing Based Converter 53 5.1 Introduction to OpAmp Based Switched-Capacitor Gain Stage . . 54
5.2 Comparator-Based Switched Capacitor CBSC Gain Stage . . . 58
5.3 Charge Analysis of ZCBC Gain Stage . . . 61
5.3.1 Initial Phase . . . 61
5.3.2 Second Phase . . . 63
5.3.3 Third Phase . . . 65
xii Contents
5.3.5 Charging and Speed . . . 68
5.3.6 Conclusion . . . 69
5.4 SAR Based ADC Converter . . . 69
5.4.1 SAR Logic . . . 73
5.4.2 SAR Capacitor Array . . . 75
5.4.3 SAR Comparator . . . 76
5.4.4 SAR Transmission Gate Register . . . 77
5.4.5 SAR Logic Timing . . . 78
5.4.6 Conversion Time . . . 79
5.4.7 Power Consumption . . . 79
6 Behavior Level Simulation Results 81 6.1 Design Challenges . . . 81
6.2 Work Flow . . . 82
6.3 SFG of ADC . . . 82
6.3.1 Optimum Number of Stages . . . 84
6.4 Simulink Modelling of ADC . . . 86
7 Common Error Sources in ADCs 95 7.1 Design Considerations . . . 95
Contents xiii
7.1.1 Capacitor Matching . . . 95
7.1.2 Capacitor Linearity . . . 96
7.1.3 Flicker Noise . . . 96
7.1.4 Thermal Noise . . . 96
7.1.5 Thermal Noise in Pipelined MDAC . . . 98
7.1.6 Comparator Offset . . . 99
7.1.7 Finite OpAmp Gain . . . 99
7.1.8 Finite Current Source Output Impedance . . . 99
7.1.9 Multiple Stage Errors . . . 100
7.2 Redundancy . . . 101
7.3 Noise Analysis . . . 101
8 Schematic Level Implementation Details 103 8.1 The Schematic Level Model . . . 103
8.2 Switches . . . 103
8.2.1 MOS Switch . . . 105
8.2.2 Transmission Gate . . . 106
8.2.3 Boot-strapped Model . . . 107
xiv Contents
8.2.5 Voltage Control Delay Line . . . 109
9 Schematic Level Simulations 113 9.1 CBSC Pipelined ADC . . . 113
9.1.1 Bit Decision Comparators . . . 114
9.1.2 Bit Decision Latch . . . 116
9.1.3 Ramp Generation . . . 117
9.2 Schematic Level Simulations . . . 118
9.2.1 Clock Phases . . . 119
9.2.2 Ideal switches . . . 122
9.2.3 Dependency of the Pull-up Current . . . 127
9.2.4 Varying the Transistor Sizes . . . 129
9.2.5 Simulation Conclusions . . . 129
9.3 Block Simulations . . . 130
9.3.1 Determining the Voltage Levels . . . 130
9.3.2 Bit Detect Signals . . . 131
9.3.3 Other Concerns . . . 133
9.4 The Pipeline . . . 133
Contents xv 9.6 Modified Gain Stages . . . 137
10 Conclusion and Future work 143
10.1 Thesis contribution . . . 143 10.2 Conclusion . . . 144 10.3 Future Work . . . 145
Bibliography 147
A Appendix A - Matlab Codes 151
B Appendix B - VerilogA Codes 153
B.1 Bit Detect VerilogA . . . 153
C Appendix C - Skill Code 155
C.1 smartDustAdcHsZcbcAmpEval . . . 155 C.2 smartDustAdcHsZcbcPipe . . . 156 C.3 smartDustAdcHsZcbcPipe alternate . . . 157
D Appendix D - Linux 158
List of Figures
1.1 IEEE reference architecture for pipeline Zero-Crossing Based
Detec-tor ADC . . . 19
1.2 CBSC Ideal Schematic . . . 21
1.3 CBSC Ideal Schematic Result . . . 21
2.1 Smart dust Network. . . 24
2.2 Smart dust architecture. . . 28
3.1 Performance space of various ADC architectures. . . 29
3.2 Signal processing followed by filtering and quantization by Nyquist and Oversampled ADC. . . 30
3.3 Filtering and quantization FFT spectrum by Nyquist and Oversam-pled ADC . . . 31
3.4 Block diagram of simplified N bits SAR ADC architecture [15]. . . 33
3.5 ZCBC charge-redistribution DAC. . . 34
3.6 Charge redistribution concept. . . 34
3.7 Block diagram of a simplified Pipeline ADC with 3-bits stages (each stage resolves 2-bits) [20]. . . 36
3.8 1-bit stage residue and transfer curve. . . 37
3.9 1-bit stage residue and transfer curve with offset. . . 37
2 Contents
3.11 1.5-bit stage residue and transfer curve with offset. . . . 39
3.12 Block diagram of flash ADC architecture.If the analog input is lying between VX4and VX5, the comparators X1 to X3 will produce 1, while the other will produce 0 as output [20]. . . 40
3.13 Block diagram of simplified sigma delta ADC. . . 41
3.14 Signal flow of sigma delta ADC. . . 41
4.1 Quantized signal: Mid-rise and mid-tread quantization. . . 49
4.2 Gate leakage current components Igb, Igc, Igd, Igsflowing between NMOS terminals. . . 49
5.1 Circuit synthesis of an OpAmp based integrator. . . 53
5.2 An OpAmp based switched capacitor circuit. . . 54
5.3 Bottom plates open loop sampling (a) sampling circuit (b) sampling clocks. . . 55
5.4 OpAmp base switched capacitor circuit charge plot when Φ0is active Vin will be sampled on C1 andC2 . . . 55
5.5 OpAmp base switched capacitor circuit when Φ1is active high. Both of the capacitors C1 and C2 are reconfigured for the charge transfer and to perform the multiplication. . . 56
5.6 OpAmp based switched capacitor circuit charge plot Phase 2, when Φ1 is active high and virtual ground condition is accurately realized. 57 5.7 Alternative SFG for the OpAmp base switched capacitor circuit. . 57
5.8 Switched-capacitor circuit gain stage with an idealized zero delay comparator. . . 58
Contents 3 5.9 Comparator-Based Switched Capacitor CBSC gain stage, during
Phase 2. Both of the capacitors C1and C2are reconfigured for the
charge transfer operation. . . 59
5.10 Comparator-Based Switched Capacitor CBSC gain stage, during
Phase 3. The current source I1 switches on and ramps the VO and
the summing node voltages to their steady state values. . . 59
5.11 Block diagram of zero crossing based circuit ZCBC gain stage with
zero crossing detector ZCD . . . 61
5.12 zero crossing based circuit ZCBC gain stage sampling phase
configu-ration. . . 62
5.13 Zero Crossing Based switched-capacitor ZCBC gain Stage showing
the ZCD internal circuitry(components). . . 62
5.14 Block diagram of zero crossing based switched-capacitor gain Stage,
when sampling phase φ0 is active high . . . 63
5.15 Sample transient response/charge plot of ZCBC switched capacitor
gain stage for active high sampling Phase φ0. . . 63
5.16 Block diagram of ZCBC gain stage, when the P reset Phase is active.
Transistor M4 is conducting to Vss and C2 gets discharged by Vss. 64
5.17 Sample transient response/charge plot of ZCBC switched capacitor
gain stage, during active P reset phase. . . . 64
5.18 Block diagram of ZCBC switched capacitor gain stage, when φ1is
active high for the charge transfer operation. . . 66
5.19 Sample transient response/charge plot of ZCBC switched capacitor
gain stage, when φ1 is active high. The current source I1 is on and
will ramps the VO and the summing node voltages to their steady
state values. . . 67
4 Contents 5.21 Block diagram of ZCBC switched capacitor gain stage using SAR
logic. The DAC used is replaced by an analog capacitive array DAC,
that provides different threshold voltage levels . . . 70
5.22 Block diagram of ZCBC switched capacitor gain stage Using SAR
logic, when sampling phase φ0 is active high. . . 71
5.23 Sample transient response/charge plot of ZCBC switched capacitor
gain stage introducing SAR logic when φ0 is high. Vin is sampled
on sampling capacitors. . . 72
5.24 Block diagram of ZCBC switched capacitor gain stage introducing
SAR logic, When P reset phase is active high. . . . 73
5.25 Sample transient response of ZCBC switched capacitor gain stage
including SAR logic, when P reset is high. . . . 74
5.26 Block diagram of ZCBC switched capacitor gain stage introducing
SAR logic, when φ1 is high to perform charge transfer. . . . 75
5.27 Sample transient response/charge plot of ZCBC switched capacitor
gain stage with SAR logic when φ1 is high. . . . 76
5.28 Block diagram of SAR Logic implemented using D-flip flops. . . 76
5.29 Block diagram of SAR Logic with less number of flip flops for low
power consumption. . . 77
5.30 SAR Binary Search. . . 77
5.31 Compare shift register. . . 78
5.32 Transmission gate DFF. . . 78
5.33 Timing diagram of SAR logic. . . 79
Contents 5
6.2 SFG precedence model of ADC pipeline stage. . . 83
6.3 Performance spectra of 10 bit ADC. Each stage is approximated as
a 1.5 bit stage with 10 stages strewn together. . . . 84
6.4 1 bit intermediate stage SNDR vs frequency plot. . . 85
6.5 4 bits intermediate stage SNDR vs frequency plot. . . 85
6.6 4.5 bits intermediate stage SNDR vs frequency plot. . . . 85
6.7 5.5 bits intermediate stage SNDR vs frequency plot. . . . 86
6.8 6 bits intermediate stage SNDR vs frequency plot. . . 86
6.9 Integrator as an ideal model and an equivalent Simulink model with
hold and saturation blocks. . . 87
6.10 10 bits pipeline ADC model. . . 87
6.11 Sample and hold architecture used in pipeline ADC Model. . . 88
6.12 Internal architecture of single stage pipeline ADC model. . . 88
6.13 MDAC model of the single stage of a ADC. . . 88
6.14 Flash ADC model used in pipeline ADC Model as sub ADC. . . . 89
6.15 DAC architecture in addition with mismatch errors used in individual
single stage of pipeline ADC model. . . 89
6.16 Four level pipeline ADC model. . . 90
6.17 Frequency plot. . . 91
6 Contents
6.19 Histogram plot. . . 92
6.20 INL DNL plot. . . 93
7.1 Capacitor and switch noise model . . . 96
8.1 Schematic level implementation of 1.5 bit ZCBC stage. . . 104 8.2 Block diagram of switch model. . . 104 8.3 MOS switch model. . . 105
8.4 Ron versus VdsNMOS and PMOS. . . 106
8.5 Block diagram of transmission gate. . . 107
8.6 Transmission Gate Ron versus Vds. . . 107
8.7 Block diagram of Boot-strapped switch model. . . 108 8.8 Block diagram of Boot-Strapped switch circuit level Implementation.108 8.9 Refined block diagram of Boot-Strapped Switch circuit. . . 109 8.10 Voltage controlled delay line. . . 110 8.11 ZCBC Replica stage . . . 111
9.1 CBSC Pipeline. . . 113 9.2 Comparator-Based-Switched-Capacitor Bit Decision Comparator. . 114 9.3 Comparator-Based-Switched-Capacitor DFF. . . 114
Contents 7 9.4 Comparator-Based-Switched-Capacitor bit decision comparator NAND
schematic. . . 115 9.5 CBSC bit decision comparator latch. . . 116 9.6 CBSC Current Source. . . 117 9.7 Pulse Generator. . . 118 9.8 ZCBC Amplifier. . . 119 9.9 Clock Phases. . . 119 9.10 ZCBC Amplifier Simulation. . . 120 9.11 ZCD Amplifier Small Signal. . . 121 9.12 ZCD Amplifier Parametric Sweep. . . 121 9.13 Pulse Generator Test Bench. . . 122 9.14 ZCD Amplifier Parametric Sweep with Ideal Switches. . . 122 9.15 ZCD Amplifier Parametric Sweep with Ideal Switches. . . 123 9.16 ZCD Amplifier Test Bench. . . 123 9.17 ZCD Amplifier Parametric Sweep with Ideal Switches Zoomed. . . 124 9.18 ZCD Amplifier Parametric Sweep with Ideal Switches Zoomed. . . 124
9.19 Vp detection using Ideal Switches. . . 125
9.20 Vp detection using MOS Switches. . . 126
8 Contents
9.22 Vp detection using MOS Switches aggressive Parametric Sweep. . . 126
9.23 Vin and Vcm MOS Gates Parametric Sweep. . . 127
9.24 PullUp Current dependence. . . 128 9.25 PullUp Current dependence. . . 128 9.26 Varying the Transistor Size. . . 129 9.27 Voltage Scaling. . . 130
9.28 φBD Generator. . . 131
9.29 Alternate ZCBC Schematic replacing φBD Generator. . . 132
9.30 Voltage Range Bit Detect. . . 132 9.31 Bit Detect. . . 133
9.32 Pipeline Stage with φBD. . . 134
9.33 Pipeline Stage with φBD TestBench. . . 134
9.34 Pipeline Stage with φBD. . . 135
9.35 Pipeline Stage with φBD Simulation Results. . . 136
9.36 Pipeline stage with a modified first stage. . . 136 9.37 Pipeline stage with a continuous time first stage. . . 136 9.38 Modified Architecture - version 1. . . 137 9.39 Modified Architecture - version 2. . . 137 9.40 Modified Architecture - version 3. . . 138
Contents 9 9.41 Modified Architecture - version 4. . . 139 9.42 Modified Architecture - version 5. . . 139 9.43 Version 5 Schematic Result. . . 141
10 Contents
List of Tables
1.1 Smart dust high speed ADC project specifications. . . 16
1.2 Conventional OpAmp Stage versus ZCBC Stage: a comparison . . 19
2.1 Comparison of ADC architectures [11] [12]. . . 27
3.1 VDAC range and input dependence. . . 37
3.2 VDAC range for 1.5-bit. . . . 38
5.1 SAR binary search algorithm [31]. . . 74
6.1 Performance values for 10 stage ADC in a pipeline architecture. . . 83
6.2 Investigating optimum number of stages. All the results obtained
are in dB . . . 84
6.3 Performance parameters of Simulink model. . . 90
9.1 DFF Width Sizes . . . 115 9.2 NAND Gate Sizing for bit decision comparator. . . 116 9.3 Bit decision latch Sizing. . . 117 9.4 Current source transistor sizing. . . 118
Contents 11
List of Abbreviations
AI Analog Interface
TI Timer Interleaved
ADC Analog-to-Digital Converter
SAR Successive Approximation Register
BIA Biologically Inspired Architecture
DAC Digital-to-Analog Converter
SNDR Signal-to-Noise and Distortion Ratio
SNR Signal-to-Noise Ratio
CBSC Comparator Based Switched Capacitor
ZCBC Zero Crossing Based Circuit
MSB Most Significant Bit
LSB Least Significant Bit
MDAC Multiplying Digital to Analog Converter
CDAC Capacitive Digital to Analog Converter
MUX Multiplexer
LOS Line of Sight
RF Radio Frequency
AFE Analog Front End
nm Nanometer
OP Operational Amplifier
OpAmp Operational Amplifier
STM Standard Tech M
MHz Mega Hertz
DSP Digital Signal Processing
IC Integrated Chip
12 Contents
FOM Figure Of Merit
mW milli Watts
MSPS Mega Samples Per Second
CCD Charge Coupled Device
HDTV High Definition Tele Vision
xDSL Digital Subscriber Line
SAH Sample And Hold
DEC Digital Error Correction
ENOB Effective Number of Bits
SFG Signal Flow Graph
SFDR Spurious Free Dynamic Range
INL Integral Non Linearity
DNL Differential Non Linearity
THD Total Harmonic Distortion
MIM Metal in Metal
DFF D Flip Flop
TGFF Transmission Gate based D Flip Flop
NMOS N type Metal Oxide Semiconductor
PMOS P type Metal Oxide Semiconductor
MOS Metal Oxide Semiconductor
DC Direct Current
AC Alternating Current
FFT Fast Fourier Transform
ZCD Zero Crossing Detector
VCDL Voltage Controlled Delay Line
PDP Power Delay Product
SDR Signal Distortion Ratio
Contents 13
STF Signal Transfer Function
NTF Noise Transfer Function
IO Input Output SR Set Reset BD Bit Detect BW Bandwidth SC Switched Capacitor SA Successive Approximation
DCL Digital Correction Logic
CM Component Matching
H High
M Medium
Chapter 1
Introduction
This chapter provides a brief introduction to the thesis project and describes the context of the project. Section 1.1 presents an overview of information distribution in the thesis document. Section 1.2 presents the specifications for the ADC project. Section 1.3 presents the objective of the thesis and section 1.4 motivates the application of ADC to be used in the smart dust project.
1.1
Thesis Organization
The thesis is organized in ten chapters. Chapter 1 introduces the topic and gives an overview of discussions to follow. Chapter 2 gives an overview of the smart dust project unique to linköping university. Chapter 3 discusses some common ADC architectures. Chapter 4 introduces the concepts involved in low power ADC. It also discusses some performance measurement indexes that help chart such ADC. Chapter 5 details the Zero Crossing Based Circuits (ZCBC) that form a specific type of ADC by removing OpAmp. Chapter 5 motivates the ZCBC design and discusses the challenges involved, mathematical description of such an ADC is also given.
Chapter 6 describes the behavioral model in MATLAB and Verilog-A. Chapter 7 walks through the various error sources encountered during the ADC design. Chapter 8 transcends into the schematic level operation of the ZCBC ADC and also detailed description of the ADC sub modules is discussed. The simulation results of the schematic implementation are discussed in chapter 9.In chapter 10 conclusions and future work are discussed and suggested in detail.
16 Introduction
1.2
Smart Dust Specification
This section provides the specifications of the ADC to be used in the smart dust motes. The specification for the high speed smart dust ADC are given in the table 1.1.
Table 1.1: Smart dust high speed ADC project specifications.
Parameter Variable Specification Unit
Supply voltage Vdd Vdd= 1.2 V
Process - STM 65 nm
-Power consumption Pd Pd= 100 µW
External components - None
-Temperature Top −10 < Top<125 °C
1.3
Thesis Objective
The target objective of the thesis is to study the zero crossing based ADC archi-tecture . To investigate its use in the application for the smart dust system that comprises the ADC module linked in a chain to DSP and AFE sections. The thesis adopts a top-down yet test-driven approach to design the architecture, in contrast to a bottom-up approach previously under use for ZCBC. It verifies the ADC functionality in the switched capacitor ZCBC that removes the complexity of using OpAmp. ZCBC ADC architectures are studied for overcoming the challenges in data conversion of scaled complementary metal-oxide semiconductor (CMOS), with regards to energy efficiency. At nano-scale, a significant bottleneck is OpAmp, which is removed. Thus, in a way, investigating a more upstream use of a data converter as a digital device than a pure analog converter. This new association of the data converter lends more operating frequency, promises ultra low power operation, improves figure of merit (FOM) derivations. It open new chapters of architectures based on multiple clock triggering concepts that are more dynamic in nature.
1.4
Motivation for ADC
Evolution of technology to nanoscale domain introduces a new set of challenges which have to be tackled in conventional architecture design. Building the ADC in
1.4 Motivation for ADC 17 less than 100 nm technology places more energy efficiency challenges on the ADC components. For example, in a switched capacitor based OpAmp circuit for an ADC, the speed and accuracy of a switched capacitor stage is directly dependent on the gain and bandwidth of the OpAmp component. Therefore, scaling of technology has made the design of a high energy efficient OpAmp a challenge. Firstly, the headroom available for analog signal processing shrinks, secondly, small device sizes also means that certain desired device properties are also compromised. Such
as gmroproduct is low for smaller technology nodes and furnishes a lower gain for
any amplifier topology.
Migration to nano-scale integration is established in IC design due to the indus-trial demand for new, more compact and low power systems in state-of-the-art applications. This trend can be exploited to produce products that have a high operating speed due to reduced device sizes. Reduced device size in the transistor domain means that the geometry attributes reduced resistance to the current flow through it. As a result the conductance of the device being increases. The gain
of devices is usually given as in equation gm/gds. Lower operating device voltage
in nano-scale technology means less transistors can be stacked and the dynamic range of systems can suffer due to reduced gain.
With reduced supply voltage the maximum allowed signal swing also shrinks, in most cases the input signal swing cannot be larger than the supply voltage. This condition places limitations on the input sampling capacitance as the sampling capacitance is inversely proportional to the square of the input signal swing, as given in equation 1.1
C= P
V2
dd
, . (1.1)
Where, P is the power consumed. Vdd is the supply voltage. C is the capacitance
of the circuit.
For a gain stage of the pipeline ADC, the sampling capacitance at the input scales when we change technology. If we move from a technology twice of 65 nm to 65 nm then the sampling capacitance quadruples to provide the same accuracy of its function [1]. In ADC the sampling capacitance defines the speed and the accuracy desired for the system. The capacitance of the architecture also effects the SNR of the system, expressed in equation 1.2
SNR = A
2
2
kTC (1.2)
Where, k is the Boltzmann constant and A is the signal amplitude. C is the circuit capacitance.
To maintain the same SNR, the noise should be proportionally decreased for the smaller signal headroom. Using a larger capacitance increases the power consumed if the same speed of operation is desired. For example, if the headroom is halved the power of the signal decreases by four times. To maintain an acceptable SNR the noise power has to decrease by four times, which means that the capacitance has to increase by four times. This affects the signal bandwidth which is related
18 Introduction by equation 1.3
BW =gm
C (1.3)
Where, gmis the intrinsic gain and C is the circuit capacitance.
Another observation relates to the reduction in transistor output resistance. As the transistors are scaled down, channel length decreases, giving birth to channel length modulation effects and drain-induced barrier lowering such that the output
resistance (1/gds) decreases.
In essence the device gain reduces as technology scales down. This makes it more and more difficult to design complex devices such as OpAmp that form traditional analog circuit structures. They are difficult to design, since they require a huge design effort to be effectively utilized in modern process. However, scaling down in technology has advantages such as improved operating speed, reduced parasitics, and higher integration. These properties can be exploited and we can allow ourselves to look at more “Digital” ADC architectures. If the focus shifts to reduce static power dissipation and make the circuit more dynamic a considerable amount of power can be saved.
1.5
Zero-Crossing Based Detector ADC
Digitizing the analog domain yielded the CBSC and ZCBC ADC structures which were introduced in [2] and [3], respectively. Both CBSC and ZCBC ADC were model of the power efficient MDAC structure of [4]. The characteristic feature of these switched capacitor circuits include: multiple clock domains of operation, minimizing static power dissipation. Employing an architecture that makes obsolete the use of an OpAmp and allows operation in the high frequency range to allow the employment of an ADC in low-powered yet high frequency range of applications. The CBSC [2] is an alternative circuit intended to remove OpAmps in switched capacitor circuits, where the amplifying OpAmp is replaced by a current source and a comparator topology. The OpAmp functions in a closed loop topology and acts upon the output for each continuous step of operation. While the CBSC operates in a semi-open loop to achieve the same analog operation. Yet, it is more power efficient as it needs, to accurately act upon the output at the sampling instance as suggested in [2].
This thesis goes through a novel ADC architecture described in figure 1.1 [3]. The design of the reference architecture resulted from the desire to remove the use of generic comparators from ADC architectures at sub-micron level. Also an efficient and monotonic zero-crossing detection is more optimal than using full-blown comparator designs with larger analog circuitry. Fiorenza’s work [2] in CBSC ADC paved the way for a design of a more general type of comparator particularly one that optimizes power consumption. The zero-crossing based gain stage 1.1 is a result of such efforts and aims to improve the speed, accuracy and overall design complexity encountered in ADC design. A general purpose comparator is
1.6 Conventional OpAmp Versus ZCBC Systems 19 <1:0> Vin Dj<1:0> PHI1 Vref<1:0> Vrefm<2:0> PHI0 PHI0 C1 C2 PHI0 Vcm Preset Vx I1 Vp Dj<1:0> PHI0 Vrefm<2:0> PHI1 PHI1 C1 C2 Vp Vcm Preset Vx I2 PHIBD<1:0> D Stage 2 Vp ZCD Preset Vp1 ZCD Preset VO Stage 1
Figure 1.1: IEEE reference architecture for pipeline Zero-Crossing Based Detector ADC
implemented for the comparison of two arbitrary voltage waveforms, while the ZCBC is implemented to detect the time instant when an input ramp voltage will cross the threshold voltage and establish the virtual ground condition. Thus, the ZCBC general purpose comparator is a faster and simpler zero crossing detector ZCD, than a generic comparator. Some of the results for the ideal Zero-Crossing Based Circuit ZCBC gain stage is given in the Section 1.7.
1.6
Conventional OpAmp Versus ZCBC Systems
The comparison for the of ZCBC and OpAmp circuit gain model is given in table 1.2, The architecture of OpAmp and ZCBC gain stages are compared in table 1.2 in
Table 1.2: Conventional OpAmp Stage versus ZCBC Stage: a comparison S.no comparison
Point
OpAmp ZCBC based system
1 Hardware Lesser Clock domains, only
two needed More clock domains, fourin each stage
2 Noise Higher noise floor injected
by OpAmp Only dominant is the ZCDnoise
3 Design
com-plexity Complex design with strin-gent OpAmp specifications in nanoscale
Simpler design as OpAmp replaced by a current source and comparator
4 Power
con-sumption High power consumptionin the OpAmp block Low power consumptionmore dynamic in nature
5 Performance More robust high gain
out-put Less robust
different dimensions. If hardware is contrasted for an individual gain stage then it is clearer that the ZCBC has fewer circuit components or transistors and is
20 Introduction more simple in its design. From a power perspective, less hardware translates to less power consumption but this cannot be expected to be a linear change. The additive power utilization is added by the ZCBC requirement for more frequent clock response triggers and domains of operation. Secondly, from a noise stand point, the ZCD is the major contributor of noise besides gain stage resistance and capacitance. In the OpAmp architecture the noise is added by various components in the current mirror, the comparator etc and the noise manifests as a constant noise floor. Thirdly, from a designers perspective, as technology process shrinks, the design of the gain stage becomes even more time consuming to keep the multitude of transistors out of linear mode of operation. In comparison, the design of a ZCD with less transistor management is simpler. Lastly, one major advantage the OpAmp design still has over the ZCBC design is that it is more robust to slight changes in operating conditions and yields a good enough gain for the output. That is, it is more stable for a range of operating conditions, whereas, the ZCBC stage needs more calibration.
1.7
Results of ZCBC Gain Stage
The ZCBC circuits are not only limited to ADC [5] applications but can be used in filters, integrators and DACs easily. In this work an effort has been made to accuratley model the ZCBC at the functional level in Verilog-A, MATLAB and as an ideal circuit than as a transistor design. The error functions critical to ADC performance with a ZCBC architecture are also modelled at the behavioural level. Also an effort has been made to design new ZCBC architectures in the design space.
The ideal schematic in “Cadence” was designed as in figure 1.2 [6]. The model assumes a transition from the MATLAB model to the transistor design model but also simulates a multi-pole output system and amplification based on the small-signal model of the comparator architecture. Components from the daisy flow library are used in order to get flexibility of design especially if layout of the architecture is desired [2].
The ZCBC design as shown in figure 1.1 was simulated using ideal components to yield the results of figure 1.3. A 10-bit ZCBC MHz range ADC is designed with a pipeline, SAR and continuous time architecture with the perspective to be used in the smart dust project. The modified architectures with associated results are displayed and discussed in chapter 9.
1.7 Results of ZCBC Gain Stage 21
Figure 1.2: CBSC Ideal Schematic
Chapter 2
Smart Dust - An Overview
This chapter presents an overview of the smart dust concept and goes through some of the attributes common to such a conceptualization. Section 2.1 describes the smart dust concept macroscopically. Section 2.2 talks about smart dust hierarchical network. Smart dust motes for this project are assumed flat in hierarchy, as all motes are equipped to perform the same type of functionality. Section 2.3 discusses some smart dust characteristics. Section 2.4 talks about the features required in an ADC from a smart dust project perspective. Finally section 2.5 gives an outline of the various modules in the smart dust system.
2.1
Smart Dust: Distributed Sensors
Smart dust [7] is a name coined by the University of California, Berkeley to describe a distributed network of miniature electronic devices or motes. These electronic devices or motes sense environmental conditions such as temperature, light, acous-tics, vibration, magnetic field, movement, humidity, chemical stimulus, etc. They are equipped through sensors to carry out information. The sensor information can be a burst-type physical variance or a continuous-time variance depending on the type of application. The physical variance is converted to an electrical signal by the sensors. Once an electrical signal is obtained, it is amplified, filtered and converted into a digital representation by an ADC.
Energy is consumed in various transformations of signal processing. Usually, the initial detected signal may be in millivolt or microvolt range. Although, the energy or perhaps more appropriately power can be reduced by power management
24 Smart Dust - An Overview rithms. From the perspective of an ADC the energy consumed in converting the signal from analog to digital domain is dependent on the resolution of the ADC. If an ADC with 15-bits of resolution is used then the power consumed is measured to be 100 mW but if the resolution is increased to 16-bits the power consumption jumps to 400mW [8].
The motes are randomly distributed in geographical space as shown in figure 2.1.They have the attributes to self-organize, and adopt to their geographical spacing. They apply DSP processing, network algorithms and therefore must conserve power in architecture. Computation and communication should be from a low power
Figure 2.1: Smart dust Network.
perspective, as if the motes have at all a battery elements. The small size of the mote also means a smaller size for the battery and hence a shorter battery lifetime. This limit of short battery life time of the electronic sensory device can be enhanced by employing energy harvesting and /or storing techniques. As battery replacement possibility is non-existent for these devices deployed on a large scale to form a swarm community. Usually the motes are bound to their random existence. Environmental changes affects their individual energy efficiency, for example, motes deployed close areas are more susceptible to physical variance.
Motes can be turned to idle state if necessary after a period of time. Sometimes a particular physical variance such as light variance can be of more importance [9]. Power management can be utilized to turn other non relevant features off during that time period. Also the central intelligence or distributed network intelligence must be aware of a presence of active motes. Over a period of time it interrogates the mote for its livens. Such interrogations cost energy and in some Smart Dust networks energy in motes is replenished by the central network during such in-terrogations by wireless energy transmissions. Interrogation can be done through specific pilot frequencies or reference points close to a mote or group of motes. Interrogation feeds the network with information that the network algorithms will use to help actively sensing the nodes by adjusting the state of other nodes to trigger alert in the distributed system or reduce noise in the environment [8]. In more sophisticated smart dust networks, ability of event tracking is featured. Event tracking is a power saving feature. It may or may not be utilized in a
2.2 Smart Dust - Hierarchical Network 25 particular smart dust network depending on its design philosophy. Event tracking conceptually means that the network becomes aware of a particular event existence in a vicinity. It may then identify motes that are close to the event and require more assistance in active state and shut off motes that are less needed.
2.2
Smart Dust - Hierarchical Network
Smart dust motes for this project are assumed flat in hierarchy and all motes are equipped to perform the same type of function. Flat in heirarchy assumes that all mote nodes are identical in function, if a model is made, it will furnish the same functional logic. The nodes, however, have to communicate through a designed network protocol. This is captured in control FSM design used. The FSM can have multiple states of “SEND”, “RECEIVE”, “HARVEST” and “SLEEP” as per functional requirement. Identical functionality benefits in a logical protocol design for low power and cost effectiveness.
If a heirarchical network is assumed, one heirarchy of motes concerns itself with data delivery, another with data preprocessing and another for managing actual decisions for events etc. A tiered structure allows data traffic control and managing resources under certain performance constraints. A cluster of motes may be in a static or dynamic administrative control. Dynamic heirarchy benefits in scalability and flexibility but involves administrative preprocessing. A flat one, simplifies management requirements and has simple routing mechanisms etc [10].
2.3
Smart Dust: Characteristics
The smart dust project makes use of miniature electronic devices called motes which have distinct functional attributes such as.
1. Limited power consumption, compact size, necessary computing power, energy harvesting and limited communicating transmit strength.
2. They are densely deployed in an environment in which observation is desired. 3. They have to be intelligent in communication protocols and should employ state of the art architecture and technology for seamlessly integrating with the environment.
26 Smart Dust - An Overview Area of applications for smart dust sensor networks are quite diverse [10]. Some examples are: 1. Environment monitoring 2. Disaster detection. 3. Border/Commercial/Residence security. 4. Precision agriculture. 5. Operation monitoring.
The most important technical challenge for the sensor motes are its energy con-straints and network communication.
Key metrics for measuring the effectiveness of the smart dust project can be: 1. System Lifetime
2. Accuracy of the processing and components
3. Fault tolerance where system should function even if some motes are compro-mised over the time.
4. Scalability and flexibility
5. Management of power and use of energy harvesters and regulators [10]. The energy comes foremost, as it has to be distributed for hardware operation, digital signal processing and communication. To meet the energy constraints, energy efficiency has to be increased through circuit optimization, processing and communication protocols. Intelligence has to be inherent in the system.
2.4
Smart Dust: ADC
Different features required for the smart dust ADC are outlined in this section. As power constraints are critical for the smart dust mote it is of course also desired to have the ADC that consumes extremely low power. One approach adopted is to have a clockless ADC which aims to remove noise processing and dependence on clock trigger for signal processing. Another approach explored in this thesis, is to combine the facts of the ADC conversion in packed architecture but reduces
2.5 Smart Dust: subsystems 27 circuit complexity in the ADC architecture. The presence of the clock allows the ADC to retain high resolution and high operating speed without compromising the signal bandwidth.
Also, there is a possibility of using successive approximation SAR algorithms in the ADC as studied during thesis work. SAR allows to adjust the resolution order, which is required for stimulus detection. SAR algorithm offers more selectivity in resolution that can be adjusted per cycle.
Different ADC architectures are measured for their quality in terms of encoding, accuracy, resolution etc. Table 2.1 contrasts the different ADC architectures.
Table 2.1: Comparison of ADC architectures [11] [12].
ADC Latency Encoding Speed Accuracy Resolution Area
Flash No Thermometric Ultra-H L 8N H
Folding No Integrating M L-M N6∝CM M-H
∆Σ Yes Modulating L-M H N∝CM M
SAR Yes SA M M-H N∝CM L
Pipeline Yes DCL H M-H N∝CM M
2.5
Smart Dust: subsystems
For the smart dust project the smart dust system is composed of the following components as listed:
1. Digital signal processor. 2. Harvesters. 3. Logic. 4. Networks. 5. Phone. 6. Regulator. 7. Sensors. 8. Low speedADC. 9. High speedADC.
28 Smart Dust - An Overview
Processor
LS Interface
HS Interface
Energy harvestor Energy Storage Regulator Controller
Tx
Rx RF FE
Sensors and AFE
Input Input Control Signal Tx/Rx Data Transceiver
Figure 2.2: Smart dust architecture.
The various modules can be referred in figure 2.2. Smart dust essentially is an environment sensing device. Therefore, the mote has to be equipped with different types of sensor types for sound, and light etc. The sensors merit different speeds of operation depending on data acquisition time and load delivery, therefore, to cover a range of operation two ADC architectures are needed. The focus of this thesis work is on the high speed operating range ADC, therefore, a pipelined type ADC is considered due to high speed demands. The second ADC of the low speed type has a continuous time data consideration.
Since the mote modules need different modes of operation a regulator is needed to provide various voltage references. For smart dust interoperation a protocol communication scheme is also devised along with harvesting capability which is kept as a protocol feature. The smart dust mote also has digital signal processing and logic modules in order to embed intelligence in design such that challenges of effective communication are overcome effectively.
Chapter 3
ADC Basic Architectures
There exist several types of ADC architectures where each one is suited to a certain resolution and range of operation. The different types of ADC architectures include pipeline analog-to-digital converters (ADC), successive approximation ADCs, sigma-delta ADCs and the time-interleaved ADC concept. The performance space of the ADCs are illustrated in figure 3.1. There is also an effort here to highlight the
Flash SAR Sigma -Delta Pipeline Sampling Rate (Hz) Resolution (bits) 1k 10G 24 b 4 b
Figure 3.1: Performance space of various ADC architectures.
motivations of each of the ADC architectures. For example, Flash ADCs are best used in applications requiring low resolution and high speed. Pipeline and SAR have inherent latency and the number of bits of resolution can be sustained in a few applications.
The pipeline architecture is preferred for ZCBC based designs because it allows error cancellation techniques as well as fast circuit operation for conversion of the less tested zero-crossing based structure. However, configuration structure of
30 ADC Basic Architectures ADC use also determines the need for a particular type of ADC, therefore section 3.1 shows some of the ADC configurations in a signal processing chain. Whereas, section 3.2 will give details of the SAR structure, followed by section 3.3 which will explain pipelined ADC. The most widely used Flash-type ADC architecture is described in section 3.4 and finally the sigma-delta ADC useful in low speed yet high resolution applications is described in section 3.5.
3.1
ADC Configurations
Illustration of some of the ADC configurations in a signal processing chain is shown in figure 3.2. In figure 3.2a signal processing technique occurs that provides filtering
X(t) M(t) y(n)
Nyquist ADC
(a) Nyquist ADC
Oversampled ADC Oversampled ADC X(t) X(t) m(n) y(n) M(t) m(n) y(n) (b) Oversampled ADC
Figure 3.2: Signal processing followed by filtering and quantization by Nyquist and Oversampled ADC.
of the signal in the analog domain and then conversion to its digital representation. The filter selects a specific frequency of signal from a receiver side and then the ADC following it send it through at a desired sampling rate.
In figure 3.2b it can be seen that this type of signal processing allows the signal to be converted first into a digital value and then filters in the digital domain. In figure 3.2b a combination architecture allows signal to be filtered in the analog domain, then converted to digital and then followed by a filtering process in the digital domain. As illustrated in the figures the various placement of the ADC means two distinct type of the ADC has to be used. The type of the ADC used in the first row of the figure is called a Nyquist rate ADC. The one used in subsequent figure is an oversampling type ADC architecture. Figure 3.3 illustrates the concept of aliasing. Where an analog signal is sampled and the spectrum in time and frequency domains are plotted. Aliasing occurs if the Nyquist sampling theorem is not satisfied. In order to allow the ADC to work in such faster rates that the noise sources are not allowed to alias in the same band as the desired signal. Oversampled ADC simplifies the design of the analog filter by easing the transition bandwidth requirements and reducing the order of the filter required for convolution.
3.1 ADC Configurations 31
X(t) M(t) y(n)
Nyquist ADC
(a) Nyquist ADC
X(t) M(t) y(n)
Oversampled ADC
(b) Oversampled ADC
Figure 3.3: Filtering and quantization FFT spectrum by Nyquist and Oversampled ADC .
3.1.1
Nyquist Rate ADC
Nyquist rate ADC is a term used to explain a structure of the ADC that places a minimum limit on the sampling interval of the ADC to its input signal. If the signal is sampled at a frequency that is twice then its bandwidth, then the ADC is called a “Nyquist” rate ADC. Its significance can be understood in the frequency domain where the transformation resolves harmonic components. In frequency domain it can be easily seen that at the minimum sampling rate of Nyquist there is no aliasing effect on the signal. The Nyquist relationship is expressed as in equation 3.1
Fnyquist= 2 · Fsignal. (3.1)
Nyquist rate ADC is characterized by the fact that each signal is sampled to produce only one output sample. The obtained sample only depends on the signal that is processed at that time point and not on the previous states of the input signal, in essence a memory less conversion. The ADC generally has analog and digital blocks, where in nano-scale era the analog parts of the ADC have more influence on the performance of the ADC system when scaled. Hence they are more performance critical.
Furthermore, as evident from figure 3.2a the analog filtering preceding the Nyquist rate ADC is a special type called anti-aliasing filtering. The effort of the filter is basically to have minimum distortions in the signal at the output of the ADC. The distortions are expected to exist as the process of conversion from analog to digital conversion from a very high resolution to a lower resolution. The effort of the filter is to resolve frequency components that are larger or higher than its sampling frequency. The concept is further illustrated in figure 3.3, which shows that the filter blocks the out of band components in the input signal. Once the output is ready, it generally is represented in a finite number of bits, called the resolution of the ADC. To trigger 1 LSB change at the output, the input signal must change by a value given in equation 3.2,
LSBstep= OutRange
32 ADC Basic Architectures This is also called the quantization level of the signal at output and its noise power is given as in equation 3.3
PQuant2=
LSBstep2
12 . (3.3)
Where we assume uniform quantization and a larger number of bits.
3.1.2
Oversampled ADC
A second type of ADC structure used in configuration of figure 3.2b is an over-sampled ADC. It works at a sampling frequency much greater than that for the Nyquist-rate ADC. The relationship is now expressed in equation 3.4.
Foversampling= 4n· Fnyquist. (3.4)
Where, n is the resolution of the ADC. For each additional bit of resolution “n” the signal must be oversampled four times.
The difference in this architecture despite the increase in operating speed of the ADC is that it further gives room to improve the resolution of the converted signal by decreasing the distortion effects. Figure 3.3 illustrates the concept, where first
the signal is spread in a K · (Fs) range but the digital filtering further removes the
out of band quantization noise. Quantization level of the signal at output is given as in equation 3.5,
PQuant2 = 1LSBstep 2
12 · K . (3.5)
Such that, it should however be noted that 1 LSB step remains unchanged for this type of ADC structure. The use of this type of the ADC in figure 3.2b is of the advantage that it reduces the complexity in the design of the analog anti aliasing filter preceding the ADC. Reduction in complexity means the transition band width of the filtered signal is now increased and hence its order is reduced. Reduction in order also means lesser analog components used, and hence the performance of the system increases as the percentage of an analog components in the ADC are reduced. The complexity instead is shifted to the digital domain which is more easier to handle from the design perspective. From a pipeline ADC perspective the loop complexity of the ADC and the DAC chain is reduced as the signal can now be represented in less number of bits [13].
3.2
Successive Approximation ADC Architecture
Traditional successive approximation based SAR ADC topology, as illustrated in figure 3.4 consists of the following components: a comparator, a track and hold
3.2 Successive Approximation ADC Architecture 33 circuit, a DAC and usually a binary search SAR logic function [14]. The use of one comparator regardless of the resolution of the ADC is of the advantage in low power applications. Where a good design of the comparator can save on power and provide accurate conversion. In the single-ended setup the input signal is sampled
S&H VIN N NBit DAC VREF DIGITAL DATA OUT EOC NBit Register SAR Logic Clock + COMPARATOR
Figure 3.4: Block diagram of simplified N bits SAR ADC architecture [15]. and compared with the DAC output, the digital input of a DAC is controlled by a SAR unit. The SAR ADC can be implemented in a voltage scaling [14] or a charge sharing approach [9], however some architectures of a mixed type also exist [16]. The voltage scaling approach injects quite a lot of resistor noise into the system. Since state-of-the-art SAR ADC has the charge-redistribution approach [17], this method is adopted for the ZCBC based SAR architecture.
The same principles in a general SAR ADC also apply to the ZCBC version which is also essentially a feedback system that converts analog inputs to a digital value cyclically. Initially, the input to the ADC is estimated to a middle value which is represented by placing a 1 on the most significant bit MSB. Digitally represented
for a 10 bit architecture (1000000000) and with an analog value Vref
2 (the middle
value). The signal value is compared with this voltage and then the reference value is increased or decreased based on the comparator result until the output resolves the input analog value to the most accurate digital representation.
In a ZCBC based charge-redistribution DAC, refer to figure 3.5, the analog mux
allows the voltage of the SAR unit to select between two reference levels, Vb and
Vss or VGnd. For simplicity, the analog mux can be replaced by a clocked inverter.
For this thesis work, a fully binary weighted capacitor array has been utilized, which can be improved in future for a segmented circuitry [17]. The aim in this architecture design is to have as low as possible duty cycle operation, and the
34 ADC Basic Architectures ZCD Vb [N:0] Gnd [N:0]C2 [N:0]/2^(N-1) VDAC[N:0] PHI2I Multipying Phase
Figure 3.5: ZCBC charge-redistribution DAC.
dynamic nature of the circuit, as well as the less complex components used, ensures a very low power consumption. The only drawback to the this implementation, as presented in [17], was that the DAC voltages must be accurate. This was solved using voltages being taken off-chip and the big capacitors needed for step-wise charging were removed [18]. Although, energy is reduced when step-wise charging is employed [19]. In this case a simpler comparator architecture, along with step-wise charging and a fast charge transfer phase allows relaxation for the overall ADC implementation.
EDAC=
CM SBVb
S (3.6)
Where, S is the number of steps in step-wise charging. EDAC is the energy
consumed by the DAC. CM SB is the capacitance of the most dominant bit.
VSAR [N:0] Vin VDAC C2 [N:0] ZCD PHI2I SAR Logic
Figure 3.6: Charge redistribution concept.
VDAC(Φ1) = VIN, (3.7)
In the multiplication phase,
VDAC(Φ2) = VIN+
CM SB
CT OT
· Vb (3.8)
Now this architecture is suitable for use in low power ”internet of things“ or low power wireless devices. The SAR ADC requires a clock to be a multitude of the sampling rate for correct operation. This can be avoided if a delay line controlled charge distribution were allowed to occur [17].
3.3 Pipeline ADC 35
3.3
Pipeline ADC
Pipeline ADC is a well-known architecture suitable for usage in high speed appli-cations employing a resolution greater than 10 bits [5]. The speed of sampling used in this ADC varies from a few MSPS up to 100 MSPS [20]. Pipeline ADC resolution ranges from 8 bits at faster sample rates up to 16 bits. This high resolution and sampling rates with comparably low power and good dynamic per-formance makes pipeline ADC suitable for a wide range of applications; including CCD imaging, medical imaging, digital tranceivers, base stations digital video (for example, HDTV), xDSL etc [21].
A pipeline ADC consists of low resolution stages concatenated together to achieve an ADC of a desired resolution. An architectural block diagram of a pipeline ADC is shown in figure 3.7. The block diagram contains four identical stages of 3-bits which employ a coarse resolution function up to 2-bits, a flash ADC and a low resolution DAC are used. The last stage of 4-bits uses a flash ADC structure entirely. These pipeline stages are isolated by sample and hold (SAH) buffers. The benefit of splitting the conversion process to intermediate stage steps is to increase the speed of the conversion by allowing the stages to work concurrently. The total number of stages needed is independent of the desired resolution and the number of bits per stage [22], this gives flexibility in choosing different ADC resolution stages depending on the speed and power resource. ADC works in two phases, in the first phase, sampling occurs and in the second phase, multiplication occurs [21]. During the first phase ADC works on the most recent samples while during the second phase, ADC works on the analog reminder voltages, which is known as residue from previous stage. More precisely, a residue is defined as the difference signal between the sampled analog signal of the input and the output of the DAC. Here a number of quantization types can be used, if a symmetric quantizer is used
then the residue is limited between ±0.5VLSB. Each stage consists of SAH, a low
resolution ADC, a low resolution digital-to-analog converters DAC, a subtracter and controlled gain amplifier. The amplifier serves to change the range to the full scale voltage swing required for the next stage.
For this particular example, the analog input signal VIN is first sampled and held
steady by SAH circuit. The held signal is then quantized by flash ADC into 3-bits, the 3-bits output is processed by 3-bits DAC to analog signal. The analog output from DAC is subtracted from the input. Each stage gives k = 3 − bits and the
residue is then gained by factor of 2k−1, the amplification corresponds to the
resolution of the stage to use the full voltage range available that is passed to the next stage. The amplifier can be placed in front of, the subtracter. The residue gained up by amplifier continues to passed through the pipeline stages until it reaches the 4 bit flash ADC which will resolve last four LSB bits. Bits correspond to each stage are determined at different points in time, all the bits correspond to same sample are time aligned by feeding them to shift register before processed by digital error correction (DEC) logic.
As each sample propagates through the pipeline stages before its all associated bits are available to combine them in the DEC logic, data latency is associated
36 ADC Basic Architectures
Stage 2 Stage 3 Stage 4
Digital Error Correction Stage 1 3 3 3 3 4 12 VIN VIN S&H +
+
3Bit DAC 3Bit Flash ADC 3 bits 2k1 Residue 4Bit Flash ADCFigure 3.7: Block diagram of a simplified Pipeline ADC with 3-bits stages (each stage resolves 2-bits) [20].
with pipeline ADC. Although, latency is not considers to be the problem in many applications. In the pipeline ADC a single circuit known as the MDAC may be used to perform functions of amplification, SAH and subtraction while an ADC such a flash type may be used with it.
If a 1-bit ADC is assumed then the flash ADC has one threshold voltage for
comparison for the input signal VIN let us assume that voltage is Vcmand the value
is assumed to be zero to simplify the mathematics required. The quantized output
obtained from the Flash ADC is Di, it is also converted to an analog value by the
DAC, this value is either half the minimum voltage range of input 0.5Vmin or half
the minimum voltage range of input 0.5Vmax. The DAC output is subtracted from
the input voltage to give the i-th stage quantization error as given in equation 3.9, the multiplicative output of the quantization error is the residue
Vout= 2(VIN− VDAC). (3.9)
Thus, the quantization error is expanded by the multiplication to the full swing
input range of the next stage. Where, Vmaxis the maximum input range and Vmin
is the maximum output range.
When, the first stage is in multiplication phase, the second stage is in sampling phase. Each output of the intermediate stage may be placed in a shift register. This is done to preserve the time alignment of the generated code even though the input is digitized by the previous stage half a cycle later to achieve B-bits of precision. The residue transfer curve and the output transfer curve are shown in
3.3 Pipeline ADC 37
Table 3.1: VDAC range and input dependence.
Voltage Value
VDAC = 0.5Vmax Vin> Vcm
VDAC = 0.5Vmin Vin< Vcm
figure 3.8. If the threshold of the comparator has an offset voltage, a positive offset Residue Vmin Vmax Vmin Vcm Vmax Output Code 000 111 Vmin Vcm Vmax
Figure 3.8: 1-bit stage residue and transfer curve.
voltage such that, the comparator in the flash ADC part could not process a range
of input data correctly. Then this leads to a wide code error in the region near Vcm.
It is indicated by a flat line in figure 3.9 in the output transfer curve. Figure 3.9 shows that the flat line is followed by a step in the digital output code and a portion of the digital code is missing due to the step change. This corresponds to a notch patch in the output transfer curve and leads to INL and DNL errors in of the ADC structure. One way to improve upon the error associated with the output
Residue Vmin Vmax Vmin Vcm Vmax Output Code 000 111 Vmin Vcm Vmax Comparator Offset
Figure 3.9: 1-bit stage residue and transfer curve with offset.
transfer curve of the ADC and to reduce INL and DNL errors is to add another threshold logic comparator and make the intermediate stage into a 1.5-bit stage.
The threshold voltages Vrn and Vrp are expressed as in equations 3.10 and 3.11,
respectively,
Vrn=
Vcm−(Vmax− Vmin)
38 ADC Basic Architectures
Vrp=
Vcm+ (Vmax− Vmin)
8 . (3.11)
The table is now modified to table 3.2. where,
Table 3.2: VDAC range for 1.5-bit.
Voltage Value VDAC = 0.5Vmax Vin> Vrp VDAC= 0.5Vcm Vrn < Vin< Vrp VDAC = 0.5Vmin Vin< Vrn Vcm= Vmax− Vmin 2 . (3.12)
The modified equations for Vrn and Vrpnow are expressed as in equation 3.13 and
3.14, respectively, Vrn= 3 8Vmax+5 8Vmin, (3.13) Vrp= 5 8Vmax+ 3 8Vmin. (3.14)
If there is a comparator offset it has no significance on the output transfer curve Residue Vmin Vmax Vmin Vcm Vmax Output Code 000 111 Vmin Vcm Vmax Vrn Vrp
Figure 3.10: 1.5-bit stage residue and transfer curve. as shown in figure 3.11.
3.4
Flash ADC
Flash ADC is the fastest conversion scheme from analog to digital. Its high conversion rates make them suitable for high speed applications even for very
