Performance Evaluation of Modular Multilevel Converters for Photovoltaic Systems

Master of Science Thesis in Electrical Engineering

Department of Electrical Engineering, Linköping University, 2019

Performance Evaluation of

Modular Multilevel Converters for

Photovoltaic Systems

Master of Science Thesis in Electrical Engineering

Performance Evaluation of Modular Multilevel Converters for

Photovoltaic Systems

Arvind Balachandran

LiTH-ISY-EX–19/5262–SE

Supervisors:

Ahmed Abdelhakim

Department of Energy Conversion, ABB Corporate Research, Västerås, Sweden

Tomas Uno Jonsson

EKS, ISY, Linköping University

Examiner:

Mark Vesterbacka

EKS, ISY, Linköping University

Division of Integrated Circuits and Systems

Department of Electrical Engineering

Linköping University

SE-581 83 Linköping, Sweden

2019/10/01

Abstract

Modular Multilevel Converters (MMCs), over the recent years, have gained popularity in high-voltage (HV) and medium-high-voltage (MV) applications due to their high reliability. Also, with rapid growth of solar photovoltaics (PV) and energy storage systems, there is high demand for efficient and reliable power converter solutions. Therefore, due to the seen merits behind MMCs, this thesis assesses their performance for low-voltage (LV) applications. This is accomplished by comparing basic MMC solutions with an equivalent flying capacitors based solution. Such comparison is based on the evaluation of the passive elements requirements, semi-conductor losses, area, voltage and current stresses, and common mode voltage. It is worth mentioning that the evaluation is based on utilizing LV MOSFETs. Furthermore, the thesis introduces a modulation scheme for the full-bridge submodule MMC, thus further exploring the different operating regions of the full-bridge based MMC.

2019/10/01

Acknowledgements

I would first like to thank my thesis advisor Prof. Tomas Uno Jonsson of the Department of Elec-trical Engineering at Linköping University and Dr. Ahmed Abedlhakim of the ElecElec-trical System department at ABB Corporate Research. The doors of Prof. Tomas Uno Jonsson and Dr. Ahmed Abedlhakim’s offices were always open whenever I ran into a trouble spot or had a question about my research or writing. They consistently allowed this paper to be my work but steered me in the right the direction whenever they thought I needed it.

I would like to thank my fellow master students for their feedback, cooperation and of course friendship. Besides, I would like to express my gratitude to the engineers of ABB Corporate Re-search for the last-minute favors.

I would also like to thank Prof. Mark Vesterbacka for being the examiner for my thesis and also guiding me through the entirety of my master’s program.

Nevertheless, I am also grateful to all the professors of Linköping University and all the engi-neers of ABB Corporate Research for their valuable lessons, and an inspiration to pursue a PhD. I would also like to thank my friends for accepting nothing less than excellence from me. Last but not least, I would like to thank my family: my parents for supporting me spiritually throughout writing this thesis and my life in general.

Contents

2.1 Power Converters: An Overview . . . . 2.1.1 DC-DC Boost Converter . . . . 2.1.2 DC-AC Voltage Source Inverter . . . . 2.1.3 Neutral Point Clamped Inverter . . . . 2.2 Photovoltaics: An Overview . . . . 2.3 Three-Level Boost Converter . . . . 2.3.1 Mode I (Vin< Vout) . . . .

2.3.2 Mode II (Vin > Vout) . . . .

2.4 11-level Flying Capacitors Inverter (FCI) . . . . 2.5 HB-SM Based MMC . . . . 2.5.1 Nearest Level Control (NLC) . . . . 2.5.2 Level Shifted Carrier-Based PWM . . . . 2.5.3 Phase Shifted Carrier-Based PWM . . . . 2.6 FB-SM Based MMC . . . . 2.6.1 FB-SM Based MMC Modulation . . . . 2.6.2 Circulating Current Controller . . . . 2.7 MOSFET Operation and Losses . . . . 2.7.1 MOSFET Switching Behavior . . . . 2.7.2 MOSFET Losses: An Overview . . . .

3 Method 24

3.1 State-of-the-art PV Inverter Topologies: Pre-Study . . . . 3.2 Implementation of Topologies Using PLECS . . . . 3.3 MOSFET Loss Estimation Using PLECS . . . .

4 Results 35

5 Discussion 40

5.1 Comparative Assessment of Topologies . . . . 5.1.1 Semiconductor Devices . . . . 5.1.2 Passive Elements . . . .

CONTENTS 2019/10/01

6 Conclusion 45

Bibliography 49

List of Figures

2.1 Boost converter operation and PWM . . . . 2.2 The operation and modulation of a voltage source inverter . . . . 2.3 3-level neutral point clamped inverter operation and modulation. . . . 2.4 PV module equivalent circuit, VI characteristics, and different PV grid-tied inverters. 2.5 Three-level boost converter (3L-BC) schematic and modulation. . . . 2.6 11-level flying capacitors based inverter schematic, modulation and operation. . . . 2.7 5-SM HB-MMC schematic and modulation. . . . 2.8 5-SM FB-MMC schematic and modulation. . . . 2.9 Dual-level-shifted carrier-based PWM scheme for a FB based MMC at different operating regions . . . . 2.10 Average peak-to-peak capacitor voltage as a function of maand d at different power

factors assuming a 3-phase 30kW load. . . . 2.11 MOSFET structure and V-I characteristics . . . . 2.12 MOSFET switching behavior equivalent circuits . . . . 2.13 MOSFET turn-on and turn-off transients . . . . 3.1 State-of-the-art PV inverter topologies . . . . 3.2 Modified 5-level flying-capacitor topology by SolarEdge and quasi Z-source inverter 3.3 Modified 5-level active-neutral-point-clamped inverter topology by ABB and cascade

H-bridge inverter (CHB) . . . . 3.4 3-Level boost converter fed 11-level flying capacitors based inverter schematic em-ployed in PLECS . . . . 3.5 3-Level boost converter fed HB-MMC schematic employed in PLECS . . . . 3.6 Direct fed FB-MMC schematic employed in PLECS . . . . 3.7 3L-BC schematic and PWM employed in PLECS . . . . 3.8 Schematic of the 11L-FCI and the phase shifted PWM (PSPWM) scheme in PLECS 3.9 Schematic of the 5-SM HB-MMC, PSPWM, and the HB-submodule in PLECS . . 3.10 Schematic of the 5-SM FB-MMC, dual-level-shifted carrier-based PWM and the FB-submodule in PLECS . . . . 3.11 Schematic of circulating current controller implemented in PLECS . . . . 3.12 Turn-on, turn-off energies and conduction losses in PLECS . . . . 4.1 Steady state full-load common mode, and output waveforms of all the converter topologies over the fundamental period considering an input voltage of 600V. . . . 4.2 Steady state semiconductor and capacitor full-load voltage and current waveforms at different input voltages over the fundamental period. . . . 4.3 Steady state full-load circulating currents over the fundamental period and boost converter wave-forms over 5 switching cycles at different input conditions. . . . 5.1 Full-load average capacitor voltage per phase for all topologies at different operat-ing input voltages, where Cf c is the flying capacitor of a single level, Csm is the

LIST OF FIGURES 2019/10/01

5.2 RMS full-load semiconductor and capacitor phase currents at different input volt-ages. (a) RMS phase currents through semiconductor devices, where S1corresponds

to an arm switch of FC-inverter. The MMC submodule switches are given by S1

and S1, and S2 and S2. SBC,u and DBC,u are the upper switch and upper diode

of the 3-level boost converter, respectively. (b) RMS capacitor phase currents at full-load, where Cf c is the flying capacitor of a single level, Csm is the submodule

capacitor for the MMCs. . . . 5.3 Full-load condition and switching losses distribution in a semiconductor device for all the topologies, where S1 corresponds to an arm switch of flying capacitors inverter.

Submodule switches are given by S1and S1, and S2 and S2. SBC,uand DBC,uare

the upper switch and upper diode of the 3-level boost converter, respectively. Full load conduction and switching loses at (a) 400V input and (b) 600V input. . . . . 5.4 Total losses normalized to output power is Ptot.,loss/Pload at 400V input voltage. A

load 30kW resistive load is considered a full-load condition. . . . 5.5 Normalized total full-load semiconductor area (Atot), total switching loss (Psw.,tot),

total conduction loss (Pcdn.,tot), peak capacitor current (ˆic,a,u), and total energy

stored in the inductors (El−tot) and capacitor (Ec−tot) for all the topologies. (a)

Represents different operating points ,i.e, (a) 400V, (b) 600V, and (c) the worst case normalized parameters. . . .

List of Tables

List of Abbreviations

Abbreviation Definition

3L-BC 3-level boost converter

3L-NPC 3-level neutral point clamped

AC Alternating current

DC Direct current

FB Full-bridge

FC Flying capacitor

FCI Flying capacitor inverter

HB Half-bridge

HV High voltage

IGBT Insulated gate bipolar junction transistor

LV Low voltage

MMC Modular multilevel converter MOSFET Metal-oxide filed effect transistor

MV Medium voltage

PSPWM Phase-shifted pulse width modulation

PV Photovoltaic

PWM Pulse width modulation

SM Submodule

THD Total harmonic distortion

VSI Voltage source inverter

ZCS Zero current switching

Chapter 1

Introduction

The introduction is divided into the following sections:

.

Motivation

The penetration of renewable energy sources into the power systems is continuously increasing along with higher utilization of different energy storage systems. Energy storage is important to extend the availability in applications such as solar self-consumption, off-grid systems and to sup-port grid frequency regulation. [1]. Typical reason for such utilization are solar self-consumption (i.e, off-grid systems) and frequency regulation [2]. For a long time, wind-based energy generation systems dominated renewable electricity capacity expansion; however, in 2017, the solar power outperformed traditional energy generation technologies and also deployed nearly twice as much capacity as wind energy generation [3].

A prominent challenge with photovoltaic (PV) and other renewable sources is its non-regulated power output [4], i.e, the availability is limited by solar and wind conditions. The power converter performance required to efficiently utilize PV and energy storage systems is based on several tech-nologies such as converter topology, modulation and control, semiconductor devices and passive components.

Many different PV inverter topologies are discussed over the recent years and the most common solution is the two-level VSI topology [5]. Several merits are seen behind this topology such as simple design and good galvanic isolation. Furthermore, multilevel converter topologies benefit from having multiple output voltage levels, thus resulting in lower total harmonic distortion (THD) and thereby reducing the output filter requirements [6]. The 3-level neutral point clamped and 3-level flying capacitor multilevel inverters are often used. On the other hand,modular multilevel converters (MMC), have gained popularity over last few years in HV and MV applications with several advantages, such as a low THD, low dv/dt, scalable and no DC voltage link limitation, reduction of bulky filters on the AC side and, lower losses [7, 8]. Over the last couple of years, modular multilevel converters (MMC) fed LV systems have gained higher attention as discussed in [9–15] where the results show significantly lower semiconductor losses for MOSFET based MMC.

.

Aim

Although the shown interesting effort in the literature, none of these research articles investigate the performance of MMC compared to the state-of-the-art equivalent solution, which is flying capacitors-based solution. It is worth mentioning that it is quite obvious that the reliability of these MMC solutions are much higher due to their capability to continue operation with faulted cells, but the overall performance is not yet clear considering low-cost 100-200V MOSFETs and electrolytic capacitors. Hence, this thesis considers a base solution, which is a flying capacitors-based, and compared with two MMC solutions.

. . RESEARCH QUESTIONS 2019/10/01

.

Research Questions

The comparison considers a 275V, 30kW three-phase system for each of these topologies. Further-more, the DC input voltage is varied from 400 - 600V relating to the typical output voltage of a PV system. The comparison considers three topologies; the first two topologies include a 3-Level boost converter (3L-BC), where the output voltage is maintained at 800V, followed by an inver-sion state that utilizes the 11-level flying capacitors based inverter (FCI) and the five-submodules per arm half-bridge based MMC (HB-MMC). The third topology includes only the inversion state considering the five-submodules per arm full-bridge based MMC (FB-MMC).

The comparison includes the following: 1. The number of semiconductor devices. 2. The number of passive elements employed.

3. Forecasted switching and conduction losses using PLECS. 4. Estimated volume of the semiconductor devices utilized.

5. Estimated energy ratings of the employed magnetic and capacitive elements

.

Report Structure

The Thesis report is organized as follows: chapter 2 reviews fundamental operations of photo-voltaic, power converters, MOSFET and its losses. Furthermore, the design and modulation of the considered three inverter topologies are also discussed. Chapter 3 covers the implementation of inverters, discussed in the previous chapter, in PLECS. A 30kW three-phase system is then simu-lated for each of these topologies in chapter 4. From the obtained simulation results in chapter 4, a comparative assessment is then presented in chapter 5. The comparison includes the number of semiconductor devices and passive elements employed, rated voltage and current of these different semiconductor devices, the forecasted switching and conduction losses using PLECS, and the esti-mated energy ratings of the employed magnetic and capacitive elements. Finally, the conclusions are reported in chapter 6.

Chapter 2

Theory

This chapter covers the theory behind power inverters, MOSFET operation, and the design and modulation review of the three inverter topologies under comparison.

The chapter is divided into several sections, where section 2.1 covers the operation and modulation of three-level inverters, in particular, the three-level neutral point clamped inverter (3L-NPC). The Section 2.7 covers the basic operation of a MOSFET and its losses, sections 2.3, 2.4, 2.5, and 2.6 give the design review of the 3-Level boost converter (3L-BC), flying capacitors (FC) based inverter, half-bridge (HB)-submodule (SM) based MMC, and full-bridge (FB)-SM based MMC, respectively.

.

Power Converters: An Overview

The power converters are an integral part of an electronic system because they aid in the transfer of energy from a non-regulated input source to a voltage/current regulated output. Over the last few decades, semiconductor-based power electronic converts have gained popularity in applications such as control of a wind turbine, HVDC transmission, SMPS, electric vehicle battery charging, PV plants, etc. Power converters aim to ensure a high power conversion efficiency with accurate output voltage/current, reducing the power converter volume requirements and thereby reduction in cost. The section covers two of the operation and modulation of a boost converter, 2-level voltage source inverter, and 3-level NPC.

. .

DC-DC Boost Converter

In this power converter, the DC output voltage Vo is greater than the input voltage Vin as is

used commonly in PV applications. In a boost converter, the energy is stored and released in the inductor L is controlled by the means of a switch S, such that the output voltage rises greater than the input. Furthermore, capacitor C acts as a low pass filter to the output voltage and is designed to ensure a low output voltage ripple. Figure 2.1 gives the operation and schematic of

i L S1 1
L Vin D C Vo i L S1 2
L Vin D C S1 0 1 amplitude (p.u) → Vo VS₁ i L Vo Vo tri_(t) D

. . POWER CONVERTERS: AN OVERVIEW 2019/10/01 + −Vdc2 io vo S1 S1 io S1 S1 1  2 +Vdc 2 −Vdc2 +Vdc 2 vo voutvout vout

(a) VSI operation

tri_(t) 1 -1 0 ma DC bias: 1-ma amplitude (p.u) → 0 T/2 T ON OFF ON OFF vo S1 S1 +Vdc/2 -Vdc/2 Dead Time v∗_(t) (b) VSI PWM scheme

Figure . : The operation and modulation of a voltage source inverter

a typical boost converter. From the figure, in-state 1O, S is ON and diode D in OFF causing the output voltage to drop from Vdcand the energy stored in the inductor increases. in state 2O, S is

OFF and D is ON and the energy stored in the inductor causes the output voltage to rise further than the input voltage Vin.

The output voltage is given by the relation: Vo=

Vin

1 − D, ( . )

where D is the duty cycle.

Furthermore, the inductor value can be calculated using the following relations: L = D Vo

∆iLfs

(1 − D), ( . )

where ∆iL is the inductor current peak-to-peak ripple, fs is the switching frequency.

. .

DC-AC Voltage Source Inverter

The purpose of the converter is to produce a sinusoidal AC output given a DC input. This conver-sion is based on the switch-mode principle. The purpose of this converter is to ensure a sinusoidal AC voltage of controlled magnitude and frequency. These are commonly used in uninterruptible AC power supply, AC motor drives, PV plants, etc. Figure 2.2(a) gives the schematic an operation of a half-bridge based inverter, where the output voltage is controlled by controlling the comple-mentary switches S1and S1. From the figure it can be seen that when the switch S is ON and S1

is OFF, the voltage vois +Vdc/2 and when S is OFF and S1is ON, vobecomes −Vdc/2. Therefore,

controlling the ON and OFF times of these switches in a sinusoidal fashion an approximate sine wave can be produced. Figure 2.2(b) shows a sinusoidal reference signal v∗_{(t)and the triangular}

carrier signal tri(t). When v∗_{(t) amplitude is greater than the tri(t), then the switch S}

1 is ON

and vise Versa. Therefore, the output voltage Vout after filter L is a sinusoidal waveform. It is

important to mention that in practice, a dead time is introduced between two switching intervals of switches S1 and S1. This is used to ensure that both the switches are turned OFF during the

turn ON and OFF transients as the semiconductor switches employed are not ideal. Furthermore, there exists a forbidden state where the neither switches are turned ON, else this would cause a short circuit at the DC and AC sides.

. .

Neutral Point Clamped Inverter

The purpose of the Neutral Point Clamped Inverter is to provide additional voltage levels at the output, compared to a conventional VSI that provides only two or three output voltage levels.

. . POWER CONVERTERS: AN OVERVIEW 2019/10/01 −Vdc2 io vo S2 S1 io S2 S1 1  2 +Vdc2 −Vdc2 +Vdc2 vo vvoutout vout S1 S1 0 S2 S2 0 −Vdc2 io vo S2 S1 io S2 S1 3  4 +Vdc₂ −Vdc2 +Vdc₂ vo vvoutout vout S1 S1 0 S2 S2 0

(a) -L NPC: Steady state operation

triu(t) 1 -1 0 _ma DC bias: 1-ma amplitude (p.u) → 0 T/2 T ON OFF ON OFF vo S1 S1 +Vdc/2 -Vdc/2 v∗_(t) tril(t) S2 S2 0

(b) -L NPC: Level Shifted Carrier-based PWM

Figure . : -level neutral point clamped inverter operation and modulation.

This is possible by introducing clamping diodes that can provide additional current paths for cur-rent so that the AC-terminal can be connected to DC levels split across the DC-link capacitors during operation. This also results in an additional voltage level at the output. As a result, a large number of output levels can thus be produced. However, with an increase in the number of levels, the amount of interconnects between the switching elements also increases, thus increasing the complexity of the design. The steady-state operation of an NPC is shown in Figure 2.3(a). States 1O and 4O, in principle, same as a VSI. In these state both either upper or lower switches are gated ON in order to achieve the voltage Vo states, Vo = +Vdc/2 and Vo = −Vdc/2, respectively.

However, in states 2O and 3O, the AC terminal is connected to the DC-link mid-point, where switches S₂ and S₁ are gated ON and S₁ and S₂ are switched OFF. Furthermore, in both NPC and VSI, the current direction can be neglected while considering the switching pattern, as long as there is sufficient dead time introduced between two switching intervals. Another advantage of the NPC is that at any given state the semiconductors need not block more than Vdc/2.

Many modulations schemes have been employed for the NPC [16] and the most commonly employed modulation scheme is the level-shifted carrier based PWM. In this modulation scheme the sinusoidal reference wave v∗_(t)is compared with two level shifted carriers tri

u(t)and tril(t),

as shown in the Figure 2.3(b). When v∗_(t)> tri

u(t), S1and S2are ‘ON’ state. However, if triu(t)

> v∗_(t)> tri

l(t), then S2and S1are ‘ON’ and as a result, vo= 0. and the process is repeated till

. . PHOTOVOLTAICS: AN OVERVIEW 2019/10/01 IL ID ISC V I RS RSH

(a) PV module equivalent circuit

0 5 10 15 20 25 30 35 40 Voltage (V) 0 2 4 6 8 Current (A)

Module type: 1Soltech 1STH-215-P

1 kW/m2 0.5 kW/m2 0.1 kW/m2 0 5 10 15 20 25 30 35 40 Voltage (V) 0 50 100 150 200 250 Power (W) 1 kW/m2 0.5 kW/m2 0.1 kW/m2

(b) V-I characteristics of a PV module

= ¬ Generator Connection Box Inverter PV module PV String PV String (c) PV central inverter = ¬ Inverter PV module PV String PV String = ¬ (d) PV string inverter = ¬ Inverter PV module PV String PV String = = = = DC - DC Converter

(e) PV multi-string inverter

= ¬ Inverter PV module PV String PV String = ¬ Inverter (f) PV micro inverter

Figure . : PV module equivalent circuit, VI characteristics, and different PV grid-tied inverters.

.

Photovoltaics: An Overview

The basic component of every photovoltaic (PV) plant is a solar cell. The solar cell constructed mostly of silicon. However, It is not uncommon to introduce foreign atoms (doping) thus creating a p-n junction. When light falls on the solar cell, the charge carriers are dissolved out of the crystal bindings and moved by an electric field onto the conduction leads. These solar cells thus produce small voltages (about 0.5 V) with a current that depends on the load. To achieve higher voltages, a serial connection of many solar cells is required. However, the current output is unaltered, thereby limiting the output power. To achieve a higher output power level, several solar cells are connected in series and are often referred to as strings. These strings are then connected in parallel to each other, thereby creating a PV module. An equivalent circuit of the PV system can be seen in Figure 2.4(a) where IL gives the current produced by the PV module which is directly proportional to

the total solar irradiance (the power produced by the sun per unit area) [17]. There also exists a Schottky diode, D that models the p-n junctions in each solar cell of the module; Rsh and Rsare

the lumped series and shunt resistance of the module. Figure 2.4(b) gives the V-I characteristics, and it is clear that the maximum power point (MPP) for a single module is directly proportional to the solar irradiance. This is the maximum power that can be obtained from the PV module at any instant of time. In a typical PV plant many of these modules are connected in different

. . THREE-LEVEL BOOST CONVERTER 2019/10/01

combinations to supply the load. It is important to consider the possibility that some modules could be subjected to different irradiance (partial shading), or that they could be faulty as a con-sequence, cause a massive drop in the MPP, thus questioning the reliability of the PV system. Therefore, maximum power point tracking (MPPT) is introduced and it is critical, especially for grid-tied plants. There exist several algorithms that help to achieve MPPT. Furthermore, the use of a converter aids in better MPPT. There are many types of PV systems but the focus in the thesis is limited to PV grid-tied systems.

Figures 2.4(c), 2.4(d), 2.4(e), and 2.4(f) represents a broad classification of different PV plants that can be connected to a public grid [17]. Large scale PV plants employs a single central MV inverter. On the other hand, medium-scale plants usually employ string inverters, enabling inde-pendent MPPT for every string. Multi-string inverter topology is another combination for better MPPT for medium to large scale plants, which comprises of a central inverter fed by different DC-DC converters each connected to a PV string. Although there an increase in the number converts, a decentralized MPPT is rather economical. Furthermore, transistors operated at MV owes to fewer losses than operating at HV. Finally, for small scale plants with less number of PV modules, each module having an independent converter enabling a module-based MPPT.

It is important to mention the performance requirements of a typical PV converter. The PV converters should have high efficiency, high power density with low initialization cost and very lit-tle leakage current [5]. In addition, there are several legal requirements such as, galvanic isolation (i.e, only required in some countries, ex. Spain), Anti-islanding detection, i.e, the PV inverter should disconnect after the grid has tripped. If a converter does not incorporate the anti-islanding detection then this will lead to equipment damage and also is a potential safety hazard for utility line workers. Furthermore, there are some other standards by ICE, IEEE, EN 61000, etc.

.

Three-Level Boost Converter

With increase in the power level of a DC-DC converter, the voltage rating of the semiconductor devices increases, and also the inductor becomes large, bulky, costly and heavy [18]. Thus, 3L-BC is utilized in order to achieve lower voltage stresses on the semiconductor devices, and also reduction in volume of the inductor [19]. Figure 2.5(a) gives the schematic of the 3L-BC un-der consiun-deration, were SBC,u and SBC,lare upper switch of the boost converter and lower switch

of the boost converter, respectively. Vinand Vdcare input voltage and output voltage, respectively.

The 3L-BC has two operating modes and each mode has three switching states, hence the name 3L-BC. The operating modes depend on weather the input voltage is lesser or greater than half of the output voltage [18, 19]. Figure 2.5(b) shows the modulation scheme employed for the 3L-BC over one switching period TBC, where tribc,u(t) and tribc,l(t) are 3L-BC upper switch triangular

carriers and 3L-BC lower switch triangular carriers, respectively.

. .

Mode I (V

< V

)

When switches SBC,u in ON and SBC,l is OFF, the inductor current decreases (i.e, voltage drop

across the inductor vl = Vin− Vdc/2 < 0) through SBC,u, lower capacitor Cdc, and DDC,l. As

a result, the lower capacitor Cdc is charged. This state is known as the energy transfer state,

shown as 3O in Figure 2.5(b). Similarly, when switches SBC,lin ON and SBC,uis OFF, the inductor

current decreases and the upper capacitor charges, shown as state 2O in Figure 2.5(b). On the other hand, when both switches SBC,u and SBC,l are ON, the inductor current increases, and this state

is referred to as the inductor charging state, shown as 1O in Figure 2.5(b).

. .

Mode II (V

> V

)

When switches SBC,uin ON and SBC,lis OFF, the inductor current increases (i.e, vl= Vin− Vdc/2

> 0) through SBC,u, lower capacitor Cdc, and DDC,l. This state is shown as the inductor charging

. . 11-LEVEL FLYING CAPACITORS INVERTER (FCI) 2019/10/01 SBC,u SBC,l LBC DBC,u DBC,l Iin V_dc n Cdc Cdc Idc Vin + –

(a) Three-level boost converter

1 0 D>0.5 amplitude (p.u) → 0 TBC triu(t) tril(t) TBC/2 D<0.5 0 TBC SBC,u SBC,l mode I mode II
 
  ON OFF ON OFF Iin VLBC Vin Vin-Vdc/2 1  2 11 3 1 a b a c a TBC/2 Vin-Vdc Vin-Vdc

(b) Three-level boost converter PWM over one switching cycle Tbc, where a , b , c , , , and are switching

states.

Figure . : Three-level boost converter ( L-BC) schematic and modulation.

current increases through DBC,u, upper capacitor Cdc, and DDC,l, shown as state, bO in Figure.

2.5(b). On the other hand, When both switches SBC,u and SBC,l are OFF, the inductor current

decreases (i.e, vl= Vin− Vdc< 0) through the output capacitors Cdc, and diodes DBC,uand DBC,l.

As a result, the capacitor charges and therefore, This state is the energy transfer state shown as aO in Fig. 2.5(b).

It is important to mention that with the modulation scheme (phase-shifted pulse width modu-lation, PSPWM) employed, the capacitor voltage balancing is maintained inherently, and also the states 1O and aO will not occur at simultaneously.

The output voltage of the boost converter is given by the following expression: Vdc=

Vin

1 − D, ( . )

where D is the duty cycle of the boost converter.

The capacitor can be designed using the following equation Cdc=

IdcD

2 (1 − D) fBC∆Vdc

, ( . )

where IDBC,u is the average output current, fBC is the boost converter switching frequency, and

∆Vdcis output peak-to-peak ripple.

The inductor can be designed using the following equation: Lbc=

|1 − 2D| Vdc

4 fBC∆Iin

, ( . )

where Iinis the average input current, Vinis the average input voltage, ∆Iinis peak-to-peak input

current ripple.

.

11-level Flying Capacitors Inverter (FCI)

A Flying capacitors inverter phase leg consists of several capacitors that hold controlled direct volt-ages, thus providing additional voltage levels [8, 20]. These capacitors are not directly connected to the DC-link, thus the name flying capacitors. In order to achieve a 11-level output waveform, the voltages of the flying capacitors namely, C1 to C9, should be maintained at 1/10th, 1/5th, ....

to 9/10th _{of the DC-side pole-to-pole voltage, respectively. With large number of flying capacitors}

. . 11-LEVEL FLYING CAPACITORS INVERTER (FCI) 2019/10/01 Vdc /2 Idc i_a i_b i_c Lf,a Lf,b Lf,c v_a n v_b v_c Vdc /2 3L-BC Vin + – Iin

(a) -level flying capacitors based inverter

1 -1 0 ma v∗_{a(t) = m}acos(θt) 2π/N amplitude (p.u) → 0 T /2 T tri1(t) tri2(t)

(b) Phase shifted PWM for -level flying capacitors based inverter over one fundamental period, where mais the

modulation index Vdc /2 Idc S1,a S10,a i_a Lf,a Cfc,a S10,a S1,a n Vdc /2 Cfc,a Cfc,a Cdc Cdc vc1 = Vdc /10 vc9 = 9· Vdc /10 va va= +V_dc/2

⇐

⇐

(c) -level flying capacitors based inverter switching states, where vciis the DC voltage across the ithflying capacitor.

. . HB-SM BASED MMC 2019/10/01

capacitors based inverter (FCI) where Si corresponds to the ith switch of a phase leg, Cf c is the

FC, Ic is the RMS current through the FCs, and Vc1 to Vc9 are the voltages across the 9-levels of

flying capacitors of a phase leg.

The most commonly employed modulation scheme is the phase-shifted carrier-based pulse width modulation (PSPWM), where phase-shifted carrier signals are compared with a sinusoidal refer-ence. This comparison produces the gate pulses that drive the switches. Furthermore, in this modulation scheme, the capacitor voltage balancing is maintained to a certain degree by applying the same time to the charging and discharging switch states [21]. Figure 2.6(b) shows the PWM scheme employed for the 11-level FCI over one fundamental period. The figure shows triangular carriers tri1(t), tri2(t), etc. with a phase difference of 2π/10. There exist 10 such carriers and

these are compared with the reference signal v∗_{(t)to generate the gate pulses.}

Figure 2.6(c) gives the operation of the 11-level FCI, where the capacitors hold controlled DC voltages. When all the upper switches S1 to S10 are ON, then the output voltage is equal to

+Vdc/2, since the output voltage is measures across the phase and the neural (i.e, DC-link mid

point n). In the next state, S1to S9 are ON and S10is ON, then the capacitor across the switches

S10and S10 is now connected serially with the DC-link, thus the output voltage becomes:

vo= Vdc/2 − vc1 = Vdc/2 − Vdc/9 = 7 Vdc/18

Similarly, in the next state when switches S1to S8and S9, S10are ON, then the output voltage is

5Vdc/18. As the number of inserted FCs increases, then the output voltage decreases. Since, there

are 9 FCs the number of output voltage levels that are possible is 11.

By inspection, the duration of the charging and discharging switch states is equal the period of the carrier. Assuming the switching period of a carrier to be Ts, then the maximum voltage ripple

across the FC can occur as Ts/2. Therefore, the current through a phase leg FC can thus be given

by the following relation:

Cf c

∆Vci

0.5 Ts

= ˆic, ( . )

where, ∆Vciis the maximum peak-to-peak capacitor voltage ripple across the ithFC of a phase leg,

Ic,max is the peak current through the phase leg FC. Therefore, the phase leg FC can be designed

using the following equation:

Cf c ≈

ˆic

2 fs∆Vci

, ( . )

where fef f is the effective switching frequency, and Ic is the RMS capacitor phase current.

Similarly, the charging and discharging period of the filter inductor Lf,a is also Tef f. By

inspection, The instant for the maximum peak-to-peak current ripple through the inductor is 0.5Tef f, and the instantaneous voltage drop across the inductor at this instant is Vdc/10. Therefore,

Larm,acan be written as:

Lf,a =

Vdc

20 fef f(∆Ia)

, ( . )

where ∆Ia is the maximum peak-to-peak output current ripple.

.

HB-SM Based MMC

MMCs consists of several legs with two arms, each connecting to one AC terminal and one DC terminal. The most common submodule (SM) variant is the half-bridge (HB) variant as shown in Figure 2.7(a). In the figure, each submodule contains two switches S1 and S1 connected in series

across a capacitor Csm, with the midpoint connection between the two switches and one of the two

capacitor terminals brought out as external connections. Depending on the states of the switches, the capacitor is either bypassed or connected into the circuit. Therefore, each submodule acts as an independent two-level converter generating a voltage of either 0 or Vc, assuming all submodules

capacitor voltages to be equal [8, 22–24]. These SMs have several advantages such as, having a simple construction resulting in a simple control and design, and during normal operation, only

. . HB-SM BASED MMC 2019/10/01 SM1,a,u SM5,a,u SM5,a,l SM1,a,l iarm,a,u iarm,a,l Vdc /2 icrc,a v_a Idc/3 Larm,a,u Larm,a,l i_a varm,a,u varm,a,l i_c i_b v_b v_c S1,a,u S1,a,u n Idc Vdc /2 Csm,a,u 3L-BC Vin + – Iin

(a) Half-bridge based MMC with five submodules per arm

1 -1 0 ma v_{a,u(t) = ma}∗ _cos(θt) 2π/N amplitude (p.u) → triu1(t) 1 -1 0 ma v∗ a,l(t) = macos(θt) π_/N 0 T /2 T tril1(t) amplitude (p.u) →
  Lo w er Submo dules
  Upp er Submo dules triu2(t) tril2(t)

(b) Phase shifted PWM for half-bridge based MMC with five submodules per arm over one fundamental period

Figure . : -SM HB-MMC schematic and modulation.

one device will be in ON state [25]. Hence, the HB-SM has low power loss and high efficiency. This SM can operate at two possible switching states. One, bypass state; where the switch S1 is

conducting and the terminal voltage v_S1 is zero. Two, insertion state; the switch S1is conducting,

implying that the voltage at the terminal equals the submodule capacitor voltage. The HB-SM can thus produce N+1 levels at the AC side. Figure 2.7(a) shows the schematic of the half-bridge based MMC with five submodules per arm, where vu,armand vl,arm are arm voltages, iu,armand il,arm

are arm currents, Lu,arm and Ll,arm are the arm inductors, and SMi,u and SMi,l are the ithSM

of the upper and lower arms, respectively. icrcis the circulating current, ia is the output current,

and va is the output voltage of a single phase leg. The average submodule capacitor voltage is

given as:

Vc =Vdc/N, ( . )

where N is the number of submodules in an arm.

Applying KVL to the upper and lower loops in the schematic shown in Figure 2.7(a), we obtain the following equations:

Lu,arm dia dt = vemf − va, ( . ) Ldicrc dt = Vdc 2 − vcm, ( . )

where vemf and vcm are the differential and common mode voltages of a phase leg, respectively.

Applying KCL to the same schematic, the above equations (2.10) & (2.11) can be rewritten as follows: icrc= iu,arm+ il,arm 2 , ia= iu,arm− il,arm, ( . ) vcm= vl,arm+ vu,arm 2 , vemf = vl,arm− vu,arm 2 . ( . )

It is clear from these equations that the circulating current is driven by the common mode voltage vcm,awith opposite sign, and the output phase current iais driven by the differential voltage vemf.

. . HB-SM BASED MMC 2019/10/01

In relation to the sum of sub-module capacitor voltages in an arm the magnitude of vl,arm and

vu,arm is limited. The circulating current is responsible for transferring the energy from the DC

to the submodule capacitors.The circulating current consists of a dominant double fundamental frequency component and this can increase converter power losses and SM capacitor voltage magni-tude, and thus reduces the power conversion efficiency [26–28]. Therefore, this double fundamental frequency must be eliminated . This is achieved by employing a circulating current controller that controls the the converter in such a fashion that vcm ≈Vdc/2. Therefore, for a controlled MMC,

the above equations (2.10)–(2.12) can be rewritten as: iu,arm= Idc 3 + ˆia 2 cos(ωt − ϕ), il,arm= Idc 3 − ˆia 2 cos(ω − ϕ), ( . ) vu,arm= Vdc 2 − ˆva cos(ωt), vl,arm= Vdc 2 + ˆva cos(ωt), ( . ) where ω is the angular fundamental frequency, cos(ϕ) is the power factor, and ˆia cos(ωt − ϕ) and

ˆ

va cos(ωt) are the instantaneous output phase currents and voltages, respectively. It is clear from

these equations that arm voltages and currents consists of both DC and fundamental frequency components. This proves the assumption that each submodule can be behaves like a voltage source with a DC off-set. The DC component in the arm currents, equal in magnitude to the circulating current along with power balance (i.e, vu,arm× iu,arm = 0) are responsible for maintaining the

submodule capacitor voltage at a constant level [23].

Numerous modulation strategies for the MMCs have been proposed [29] such as, nearest level control (NLC), Level Shifted Carrier based PWM and PSPWM schemes.

. .

Nearest Level Control (NLC)

This scheme is the simplest of all the modulation schemes and can be easily implemented in hardware using FPGAs. In the NLC the reference is sampled at high frequency and is approximated to the nearest available level. The reference now becomes a staircase and is quite obvious that the lower level will be active for a longer period than the higher levels leading to capacitor voltage imbalance. NLC is thus not suited for direct assignment to SMs and a sorting algorithm is necessary. An attractive feature about NLC is that no carriers are involved, the harmonic content for a given number of SMs can be altered only by modifying the sampling frequency. To completely utilize all the SMs and always obtain N+1 levels at the output with voltage steps equal to 1 level, the minimum sampling frequency, fs,min ≥ πN f. Where, f is the line frequency and N is the number

of SMs. Using different arm frequencies for the upper and lower causes different switching angles and thereby the resulting in an artificial doubling the number of emf levels at AC side. The NLC will also result in a stationary tracking error, i.e, the difference between the obtained staircase waveform and the reference, as a consequence a higher number of SMs must be utilized. For large N, NLC and PSPWM will exhibit similar harmonic performance when measured as THD. However, the spectrum of the NLC is more distributed, while the PSPWM shifts the harmonics to higher orders, resulting in lower WTHD and lowering filter requirements. To implement this modulation scheme, a submodule voltage sorting algorithm is required due to uneven switching between the SMs causing uneven loading [8]. The algorithm is given as follows:

• State 1, Arm current positive, SM must be inserted: The bypassed submodule with the lowest capacitor voltage must be chosen.

• State 2, Arm current negative, SM must be inserted: The bypassed submodule with the highest capacitor voltage must be chosen.

• State 3, Arm current positive, SM must be bypassed: The inserted submodule with the highest capacitor voltage must be chosen.

• State 4, Arm current negative, SM must be bypassed: The inserted submodule with the lowest capacitor voltage must be chosen.

. .

Level Shifted Carrier-Based PWM

This modulation scheme involves several carriers that are level shifted from each other and can be achieved in the following ways:

. . HB-SM BASED MMC 2019/10/01

1. Phase Disposition (PD): In this case, all carriers have the same phase angle and only differ in terms of level offset.

2. Phase Opposition Disposition (POD): In this method, all carries above the zero levels are π rad shifted concerning the ones below zero level.

3. Alternative Phase Opposition Disposition (APOD): This scheme utilizes the alter-nating phase shifts of zero and π rad so that adjacent carriers will be in anti-phase.

If each submodule is connected to one of the level-shifted carriers, then the switching would be unevenly distributed between the SMs, causing uneven loading and uneven distribution of switching losses, this would also not offer any possibility of capacitor energy balancing. In practice, methods that decouple the waveform from the submodule selection are used. The PD and POD concentrate much of the spectral density to the harmonic component of the pulse frequency. However, the limitation is that the harmonics of significant amplitude stretch to very low frequencies. The waveform produced by APOD is identical to one of the PSC scheme, the harmonics will be the side-bands at the carrier frequency and drop-off fast, i.e, harmonics exceeding down to zero are much smaller than In the other two cases [8].

. .

Phase Shifted Carrier-Based PWM

This modulation scheme also involves several carriers that are phase-shifted from each other. The phase angle between the triangular pulses is 2π/N rad. The aforementioned triangular pulses are compared with a reference to generate gate pulses. If the upper and lower triangular waves are interleaved then there exists an apparent doubling of the number of levels at the AC side. Another attractive feature about PSC modulation scheme is that the switching pattern can be fully defined by the modulation scheme and no additional submodule selector is required as energy balancing is upheld. However, At lower switching frequencies, when the carrier frequency is three times the reference frequency, the first lower side-band will occur at the fundamental frequency there is thus no way by which the energy balance can be fulfilled in all SMs simultaneously. Instead, non-integer pulse numbers generally have to be used to allow for balancing of the capacitor voltages over time [8,25].

A PSPWM scheme is thus employed for the HB based MMC. Figure 2.7(b) gives the PSPWM technique employed for the HB-MMC. The figure shows two triangular carriers triu(t)and tril(t),

and two sinusoidal reference signals v∗

u,a(t)and v∗l,a(t)for the upper and lower arms, respectively

over one fundamental period. It is worth mentioning that the number of output voltage levels for the HB-MMC can be increased from N + 1 to 2N + 1. This is achieved by interleaving the carriers triu(t)and tril(t), i.e, the phase angle between carriers is π/5 (2π/N for general case). As

a result, the effective switching frequencies of interleaved carriers is twice when compared to the non-interleaved case. The insertion indices; Na,u and Na,l for upper and lower arms respectively,

describes the average number of submodules connected in each arm [22, 24]. Assuming a high switching frequency, the insertions indices can be written as:

Na,u=

1

2 1 − macos (ωt − ϕ)
, Na,l= 1

2 1 + macos (ωt − ϕ)
, ( . ) where ma is the modulation index of the reference signals, it is defined as the amplitude of the

reference signal.

For simplicity, the load is assumed to have a unity power factor (upf) and the converter is assumed to be loss-less (i.e, output power = input power). Thus, the phase current through the upper arm submodule capacitor can be written as:

ic = iu,armNu, ( . ) =⇒ ic = Idc 3ma  1 −m 2 a 2  cos(ωt) − I dc 6 cos (2ωt). ( . )

From (2.18), we can conclude that the fundamental and second harmonic components dominate for the submodule capacitor current. This instantaneous current through the SM capacitor ic,a,u

is thus given by:

Csm

dvc

. . FB-SM BASED MMC 2019/10/01

where vc is the instantaneous voltage across the submodule capacitor.

The instant where the maximum submodule peak-to-peak capacitor voltage ripple occurs is: dvc

dt = ic

Csm

= 0. ( . )

From (2.18), (2.20) can be rewritten as: Idc 3ma  1 −m 2 a 2  cos(ωt) − I dc 6 cos (2ωt) = 0, =⇒ ωt = cos −1 1 ma  . ( . )

Integrating (2.19) over the fundamental period T, the net charge stored on the submodule capacitor over the fundamental period is thus obtained.

CsmdVc= Z _I dc 3ma  1 − m 2 a 2  cos(ωt)dt − Z _I dc 6 cos (2ωt)dt + Qo, ( . ) where Qois the initial charge stored in the submodule capacitor.

From (2.21) and (2.22), the Value of the submodule capacitance is given by: Csm=

Idc 4 − ma2
3/2

24 maw (∆ Vc)

, ( . )

where ∆ Vc is the maximum peak-to-peak average submodule capacitor voltage ripple, and Vc is

the average submodule capacitor voltage and is equal to Vdc/N, where N is number of SM per arm.

By inspection, the charging and discharging period of the current iarm,a,u through the arm

inductor Lu,arm is Tef f, where Tef f = Ts/10, and Ts is the switching period. Furthermore, the

instant for the maximum peak-to-peak current ripple through the inductor ∆Iu,armis 0.5Tef f, and

the instantaneous voltage drop across the inductor at this instant is Vdc/10. Therefore, Lu,armcan

be written as: Lu,arm= Vdc 2 · N fef f(∆Iu,arm) . ( . )

.

FB-SM Based MMC

The Full-bridge submodule (FB-SM) variant requires twice the number of semiconductor devices as compared with the HB-SM for the same voltage rating. However, the control and design complexity are similar to that of the HB-SM [25]. Figure 2.8(a) shows the schematic of the FB-SM based MMC. The figure shows that in FB-SM, two devices carry the current during the normal operation, resulting in a higher device power loss and low efficiency. On the other hand, three voltage levels of 0, Vc and −Vc are attained. With theses voltage levels, the sum of sub-module

capacitor voltages may be boosted higher than the input voltage (Vdc). For FB-SMs, four different

switching states are possible, i.e, two insertion states; when S1, S2 and S2, S1 are ON, and two

bypass states; when S1, S2and S1, S2are ON, are possible. Unlike the half-bridge, the full-bridge

is thus able to provide a bipolar voltage [8]. However, it is important to mention that the current through the submodule will follow different paths in these states. Both of these states should be normally be used alternately in order to achieve even loading of the semiconductor switches and symmetric distribution of power losses [30]. Since the design complexity of the FB and HB SMs are similar, (2.10) – (2.15) are also applicable for the FB-SM.

. .

FB-SM Based MMC Modulation

The modulation techniques utilized for the HB based MMC such as, NLC, Level Shifted Carrier based PWM and PSPWM can be also employed for the FB based MMC. However, an additional rotation selector algorithm is required to achieve an even loading of the semiconductor switches [30]. In order to develop a PWM scheme without a selector algorithm, A Dual reference Phase Shifted PWM scheme is proposed [31, 32]. However, with this scheme output voltage boosting cannot be achieved. Therefore, this thesis proposes a dual level shifted carrier based phase shifted PWM scheme. This modulation scheme enables the MMC to operate in different regions, they are as follows:

. . FB-SM BASED MMC 2019/10/01 SM1,a,u SM5,a,u SM5,a,l SM1,a,l iarm,a,u iarm,a,l Vin/2 Vin/2 Icrc,a v_a Idc/3 Larm,a,u Larm,a,l i_a varm,a,u varm,a,l i_c i_b v_b v_c Iin S1,a,u S2,a,u S2,a,u left right S1,a,u Cdc Cdc n Csm,a,u Vin + – in this case, Vin = Vdc

(a) Full-bridge based MMC with five submodules per arm

triu1,l(t) 1 -1 0 m a d = 1 - ma v_{a,u(t) = ma}∗ _cos(θt) 2π/N amplitude (p.u) → triu1,r(t) tril1,l(t) 1 -1 0 ma d = 1 - ma v_{a,l(t) = ma}∗ _cos(θt) π/N 0 T /2 T tril1,r(t)
  Lo w er Submo dules
  Upp er Submo dules triu2,l(t) triu2,r(t) tril2,r(t) tril2,l(t) amplitude (p.u) →

(b) Dual level shifted carrier phase shifted PWM, buck-boost mode for full-bridge based MMC with five submod-ules per arm, where d is the DC bias point for the reference signals.

Figure . : -SM FB-MMC schematic and modulation.

• Linear operating region. • Buck-boost operating region. • Ripple-reduction operating region.

The PWM schemes for the different operating regions are illustrated in figures- 2.9 and 2.8(b), where the triangular carries are represented as triu,r(t)and triu,l(t)for the upper arm right and

left switches, respectively. Similarly, tril,r(t)and tril,l(t) are the triangular carriers for the lower

arm right and left switches, respectively. v∗

u,a(t)and vl,a∗ (t)are the reference signals for the upper

and lower arms respectively, ma and d are the modulating index and DC-bias point respectively.

From the figure, it can be seen that the value of the DC bias point d is varied for each operating region. If d is fixed to a constant value of 0.5 then the FB-MMC operation is similar to the HB-MMC, and the output is a linear function of the input DC-link voltage. If d varies as a function of ma, then the FB-MMC operates in buck-boost mode, implying that the output voltage is greater

than the DC-link voltage when ma > 0.5. Finally, in the ripple-reduction operating region, the

ratio of ma to d is varied in such a fashion that the capacitor peak-to-peak ripple is maintained at

a minimum.

. . . Ripple-Reduction Operating Region

The ripple reduction mode is fist analyzed. Figure 2.9(a) gives the ripple reduction operating region. In this region both d and maare variable. The insertion indices are given by the following:

Nu= d − ma cos(ωt), Nl= d + ma cos(ωt), ( . )

where ω is the angular fundamental frequency.

. . FB-SM BASED MMC 2019/10/01 tri_u 1,r(t) tri_u 2,l(t) 1 -1 0 ma d triu2,r(t) triu1,l(t) v∗a,n(t) amplitude (p.u) → 0 T/2 T triu1,r(t) tri_u 2,l(t) ma d triu2,r(t) tri_u 1,l(t) v∗_a,n(t) amplitude (p.u) → 1 -1 0
 
  Upp er Submo dules Lo w er Submo dules

(a) Ripple reduction region

tri_u 1,r(t) tri_u 2,l(t) 1 -1 0 ma d_{= 0.5} triu2,r(t) triu1,l(t) v∗a,n(t) amplitude (p.u) → 0 T/2 T triu1,r(t) tri_u 2,l(t) ma d= 0.5 triu2,r(t) tri_u 1,l(t) v∗_a,n(t) amplitude (p.u) → 1 -1 0
 
  Upp er Submo dules Lo w er Submo dules (b) Linear region

Figure . : Dual-level-shifted carrier-based PWM scheme for a FB based MMC at different operating regions

the submodule capacitor ic can thus be given by:

ic= Idc

ma

(2d2− m2

a)cos(ωt) − Idcdcos(2ωt) +

Idcd

2 cos(ϕ)(cos(2ωt − ϕ) − cos(2ωt + ϕ)) + Idcd

2

ma,cos(ϕ)

(cos(ωt + ϕ) − cos(ωt + ϕ)). ( . ) From the above equation it can be concluded that icis dominated by the first and second harmonic

components and it is a function of both d and ma. In order to eliminate the fundamental frequency

component, (2.26) is equated to zero: Idc ma (2d2− m2a)cos(ωt) + Idcd2 ma cos(ϕ) (cos(ωt + ϕ) − cos(ωt + ϕ)) = 0. ( . ) From (2.27) and (2.26), and also assuming a upf load, the following equation is obtained:

ma = ±d

√

2 ∨ ma6= 0. ( . )

From the equation it can concluded that, minimum peak-to-peak submodule capacitor voltage ripple occurs when the ratio of ma to d is about

√ 2.

Following the same procedure as (2.19)–(2.22), the instantaneous submodule capacitor voltage is thus given by:

vc,a,u= Idc ω ma (2d2− m2 a)sin(ωt) − Idc ω dsin(2ωt) + Idcd

4 ωcos(ϕ)(sin(2ωt − ϕ) − sin(2ωt + ϕ)) + Idcd

2

ω macos(ϕ)

(sin(ωt + ϕ) − sin(ωt + ϕ)). ( . ) Figure 2.10 shows the variation of the submodule capacitor voltage ripple as a function ma and

d, using (2.29), at both upf and a power factor 0.75 lagging (inductive load). From Figure 2.10(a), it can be seen at upf, the voltage ripple is minimum when the ratio of ma to d is approximately

√

2. However, from Figure 2.10(b), i.e, at 0.75 pf, the ratio of ma to d for minimum voltage ripple

. . FB-SM BASED MMC 2019/10/01 0 0.5 2 4 0.4 6 % V c 0.3 8 d 10 0.2 _0.45 0.5 0.4 m a 0.35 0.1 _0.25 0.3 0.2 0 _0.1 0.15 (a) upf 0 2 0.6 4 6 % V c 8 10 0.4 d 0.5 0.45 0.2 0.4 m a 0.35 0.3 0.25 0.2 0 0.1 0.15 (b) . power factor

Figure . : Average peak-to-peak capacitor voltage as a function of maand d at different power factors

assuming a -phase kW load.

Therefore, integrating (2.29) and following the procedure in (2.21) for HB-MMC, the value of the submodule capacitance for a maximum peak-to-peak voltage ripple of ∆Vc at upf is given as:

Csm= Idc 4d2− m2a
maω ∆Vc r 4d2_{− m}2 a d2 . ( . )

It is important to note that; although the capacitor ripple reduction is achieved, the peak submod-ule capacitor voltage increases significantly, given by the relation:

Vc=

Vdc

2 N d. ( . )

The output voltage varies linearly with respect to the DC-link voltage, given by the relation: Va=

ma

d Vdc

2 . ( . )

From the equation is it clear that maintaining the average capacitor voltage ripple at a minimum consequently causes the output voltage to be√2Vdc/2.

. . . Linear Operating Region

In the linear operating region, the DC bias point is kept at a constant, i.e, -0.5, as shown in the figure - 2.9(b). The insertion indices can thus be written as:

Nu=

1

2− ma cos(ωt), Nl=

1

2+ ma cos(ωt). ( . )

Comparing figures-2.7(b) and 2.9(b), and (2.33) and (2.16), it can be inferred that the the linear operating region of the FB-MMC and HB-MMC are identical. Hence, (2.17)–(2.23) can also be applicable to the linear operating mode. However, ma for the FB-MMC is half of HB-MMC case.

Therefore, (2.23), (2.31) and (2.32) can be rewritten as: Csm= Idc 1 − ma2
3/2 6 maw (∆ Vc) , ( . ) Vc = Vdc N , ( . ) Va= 2 ma Vdc 2 . ( . )

. . FB-SM BASED MMC 2019/10/01

. . . Buck-Boost Operating Region

Since the FB-MMC does not employ a boost converter, and the required peak output voltage is twice the DC-link voltage, the FB-MMC most be operating in the buck-boost operating region. In this scheme, as shown in Figure 2.8(b), the upper and lower arm references v∗

u,a(t)and v∗l,a(t)are

clamped to their respective negative peaks, i.e, the DC bias point d is varied as a function of ma.

This variation in d is responsible for the average submodule capacitor voltage to vary as a function of ma. This intern results in a non-linear behavior of the output voltage. The output voltage and

the average submodule capacitor voltages are thus given by the relation: va= ma 1 − ma Vdc 2 , Vc= Vdc 2 N (1 − ma) . ( . )

Also, under the assumption that the switching frequency is high, the insertion indices can thus be given by:

Nu= 1 − ma 1 +cos (ωt)
, Nl= 1 − ma 1 −cos (ωt)
. ( . )

The procedure for theoretically estimating the submodule capacitor voltage ripple for the FB and HB-SMs are identical. Therefore, (2.17) can be re written as follows:

ic,a,u= Idc 3 m2 a+ 2 − 4ma 2ma ! cos(ωt) −Idc 3 (ma− 1)cos(2ωt), ( . ) where ic is the instantaneous current through the submodule capacitor. It is important to mention

that (2.39) was developed using the same conditions assumed for the HB-SM case.

From the equation it is clear that the fundamental and the second harmonic frequency components dominate ic. However, when the value of ma approaches 0.58, the fundamental component of ic

tends to zero. Thus the icwill be dominated by the second harmonic component, thereby reducing

the average submodule capacitor voltage ripple.

Substituting (2.39) in (2.19), and following the same procedure as (2.19)–(2.22), the value of the submodule capacitance is thus given by:

Csm= Idc(3m2a− 8ma+ 4) 12 maω (∆ Vc) v u u t 3m2 a− 8ma+ 4 (ma− 1)2 ! , ( . )

where ∆Vc is the maximum peak-to-peak average submodule capacitor voltage ripple.

With the Linear operating region, the output voltage cannot be boosted, greater than the DC-link voltage. To boost the input voltage, the ripple reduction and buck-boost operating modes can be utilized. However, with the ripple reduction, the peak capacitor voltage is twice as much as the buck-boost mode. Therefore, the buck-boost operating mode is utilized for the FB-MMC dual level-shifted carrier-based PWM in this thesis.

Similar to the HB-SM the charging and discharging period of arm inductor Lu,arm current

iu,arm is also Tef f, where Tef f = Ts/10. However, the instantaneous voltage drop across the

inductor at this instant is given by (2.37). Therefore, Lu,armcan be written as:

Lu,arm=

Vdc

20 (1 − ma) fef f(∆Iu,arm)

, ( . )

where ∆Iu,armis the maximum peak-to-peak inductor current ripple.

. .

Circulating Current Controller

To develop a circulating current controller we must first understand the tracking of sinusoidal Reference using PID control.

. . MOSFET OPERATION AND LOSSES 2019/10/01

Assuming a current, i, flowing through an inductor then the open loop transfer function is given by:

Gk(s) =

kps + Ki

s2_L ( . )

The closed loop transfer function is thus given by: GC(s) = Kps + Ki s2_{L + K} ps + Ki =⇒ Gc(jω) = jωKp+ Ki Ki− ω2L + jωKp ( . )

For s = 0, Gc(0) = 1. And it is also clear that ω > 0, |Gc(jω)| 6= 1& argGc(jω) 6= 0. However,

i∗, reference current, is a sinusoid with frequency, ω > 0. The PI controller is therefore incapable of tracking a sinusoid without resulting in phase and amplitude errors.

In order to remedy the failure of PI controller to track a sinusoid, a versatile control block with use of resonant filter is introduced. The transfer function is given by:

Hh(s) = Kh(scos(φh) − hω sin(φh)) s2_{+ α} hs + (hω)2 =⇒ Hh(jhω) = Khejφh αh ( . )

Where, Kh is the filter gain, αh is the filter bandwidth, φh is the compensation angle. It acts

as a band-pass filter(BPF) about the angular frequency hω. When Kh = αh an φh = 0, then

Hh(jhω) = 1implying that a frequency component at hω is admitted without amplitude or phase

shift.

In order to implement the circulating current controller, the converter has to be controlled in such a fashion that vc = Vdc/2 + Ric ≈ Vdc/2(2.12).

.

MOSFET Operation and Losses

The switches are the most integral part of any power electronic converter and can be catego-rized into several types. Firstly, Thyristors: they are unidirectional gate-controlled semi-conductor stitches that are turned on by applying a pulse signal at the gate terminal which will turn ON the switch [33]. However, the device will turn OFF when the current through the device goes to zero and is not controlled by the gate signal. Therefore, thyristor based converters are line com-mutated and operate at the grid (line) frequency. To control achieve an ON-OFF control of the device, metal oxide semiconductor field effect transistor (MOSFET)s an IGBTs were introduced. An IGBT is a combination of a MOSFET and BJT and therefore, an IGBT has an additional

Drain N -N+ P ionized acceptors Source Gate Gate oxide

(a) MOSFET structure

Vds= Vdd Id=Vdd_Rds Idss Vgs= 0 Vgs= 5V Vgs= 10V Vgs= 15V Cut-off Region Saturation Region Linear Region 0 Vds(V ) → Id ( A ) →

(b) MOSFET V-I Characteristics

. . MOSFET OPERATION AND LOSSES 2019/10/01

I

V

D

(a) Equivalent circuit during td(on)

I

V

D

(b) Equivalent circuit during tri

I

V

I

(c) Equivalent circuit during miller Plateau

I

V

I

C

_C

R

(d) Equivalent circuit after miller Plateau

Figure . : MOSFET switching behavior equivalent circuits

pn-junction voltage drop as compared to the MOSFET which results in higher on-state losses for low voltage devices [34]. However, ON-state resistance may be lower in the IGBT due to bipolar carrier injection, which is better for high voltage. SiC increases the voltage capability for the MOSFETs and it can also be used to operate at very high switching frequency thus an advantage to low voltage device applications.

The basic structure an n-type MOSFET is given in Figure 2.11(a). From the figure, it can be inferred that a MOSFET is a three-terminal device namely, source, drain, and gate. The source terminal is in contact with N+_{substrate. There exists an oxide layer sandwiched between the gate}

terminal and the P substrate. Finally, a drain terminal is in contact with the N-_{substrate. When}

a positive voltage is applied between the gate and source terminals of an n-channel MOSFET, a layer of electrons is formed near the junction of the gate-oxide layer and the P substrate, thus providing a conduction path and the MOSFET turns ON.

From Figure 2.11(b) it can be seen that a MOSFET has three operating regions namely, Cut-off (or sub-threshold, weak-inversion) region, linear (or resistive) region and saturation (or active) region. First, the cut-off region, when the gate to source voltage (Vgs) < threshold voltage (Vth).

In this region, the transistor is turned OFF and there is no conduction path between the drain and the source. Second, the linear region, when Vgs > Vth and drain to source voltage (Vds) <

Vgs − Vth. In this region, the MOSFET behaves like a resistor and V-I characteristics have a

linear response. The resistance is controlled by Vgs and gate to drain Voltage (Vgd). Finally, the

saturation region, when Vgs > Vth and Vds > Vgs − Vth. Here, the MOSFET is still turned ON,

However, the current is limited due to pinch off of the channel.

. .

MOSFET Switching Behavior

The Switching behaviour of a MOSFET is rather complex however, for engineering calculations a linear approximation of the MOSFET switching process is sufficient. Figure 2.13 gives the typical

. . MOSFET OPERATION AND LOSSES 2019/10/01

turn ON/OFF transients of a MOSFET over one switching cycle. The turn ON/OFF transients can be divided into three sections, they are as follows:

Section 1: In section, a turn ON transient occurs when drive circuit potential changes from

0 to Vgg, as a result Vgs rises to Vth over a certain period of time determined by a time-constant.

The time-constant is given by Rgand Ciss, where Ciss= Cgd + Cgs, Cgdis gate-drain capacitance,

Cgsis gate-source capacitance, and Rg is the gate drive resistance. This can be observed in Figure

2.12(a).

Section 2: The transient occurs when Vgs > Vth, In this section drain current (Id) starts to

increase but however, the body diode still in conduction. Therefore, Vds ≈ Vdd, where Vdd is the

drain-drain voltage (i.e, voltage applied at the drain terminal of the MOSFET). The body diode stops to conduct when all minority charge carriers are removed. This extra current required to remove all the extra charge carriers is referred to as reverse recovery current. The equivalent circuit is shown in Figure 2.12(b).

Section-3: In this section, the body diode stops to conduct and Vds reduces to Id×Rds(on)

with a rate determined by another time constant. This time constant however, is determined by a non-line capacitance Cgd and the gate current. During this period however, Vgs = Vplateau due to

miller effect. This plateau exists because All charge entering the gate goes to Cgs, changing Vds.

This is illustrated in Figure 2.12(c). Eventuality however, Cgd will be get in parallel with Cgs.

This causes the Vgs to increase even further. The equivalent circuit is given in Figure 2.12(d).

This operation is often referred to as Hard switching and leads to unnecessary power dissipation especially during the switching transients thereby reducing the efficiency of the converter. In order to reduce this unnecessary power dissipation, soft switching techniques are thus introduced [16, 35–37]. This is achieved in a couple of ways: zero voltage switching, where Vds is forced to 0

before Id begins to rise during turn ON transient. And zero current switching, where Idis reduced

before Vds begins to increase.

. .

MOSFET Losses: An Overview

MOSFET losses can be divided into three different categories, they are:

First, conduction losses (Pcdn.): the losses observed when device is in conduction, i.e,

Pcdn.= Id2Rds(on). ( . )

Second, switching losses (Psw.): the losses observed when the device is transitioning from the

non-conduction state to the conducting state or vice-versa. The characterization of these loss are rather complex as they dependent on the following factors:

• Impedance of the gate drive has a significant impact on the switching performance of MOS-FETs.

• Reverse recovery transient arises due to losses in the diode that are difficult to quantify. It also has a significant impact on the turn ON losses of the transistor that carries the reverse recovery current, in addition to the load current.

• Parasitics have a significant impact on switching losses.

• Increase in temperature increases switching losses in all minority carrier devices.

In order to mathematically determine Psw., the energy dissipated in each transition is multiplied by

fs. The detailed procedure to determine the losses are described in [38]. Due to the non-linearity

. . MOSFET OPERATION AND LOSSES 2019/10/01 Vdr Vplateau Vgs(th) ICon IGoff Vdd IDoff IDon

tfu1 tfu2 tru2 tru1

Vdd IDon+ Irr IDon -Irr trr1 trr2 tri trr tfu

tri tfu tru tfi

A) Vdr,IG,VGS

B)ID,VDS

B)ID,VDS

D) p(t)

C) IF,ID,VDS

Reverse-recovery effect during MOSFET turn ON

. . MOSFET OPERATION AND LOSSES 2019/10/01

and tf u2 defined through Cgds1 and Cgds2, respectively, and given by:

tf u= tf u1+ tf u2 2 , ( . ) tf u1= (Vdd− Idt Rds(on)) Rg Cgds1 Vdr− Vplateau , ( . ) tf u2= (Vdd− Idt Rds(on)) Rg Cds2 Vdr− Vplateau , ( . )

where Vdr is gate drive voltage, Cgds1 is gate to drain capacitance when Vds= Vdd, and Cgds2 is

gate to drain capacitance when Vds = Vdd/2. Similarly, Vds rise time tru during the turn OFF

transient is given by:

tru= tru1+ tru2 2 , ( . ) tru1= (Vdd− Idt Rds(on)) Rg Cds1 Vplateau , ( . ) tru2= (Vdd− Idt Rds(on)) Rg Cds2 Vplateau . ( . )

The worst case turn ON energy loss in a MOSFET (Eon)and worst case turn OFF energy loss in

a MOSFET (Eof f) can be calculated as follows [38]:

Eon= Z tri+tf u 0 vds(t) id(t) dt = VddId tri+ tf u 2 + QrrVdd, ( . ) Eof f = Z tf i+tru 0 vds(t) id(t) dt = VddId tf i+ tru 2 , ( . ) where

tri= tdon+ tdon, tf i= tdof f+ tf, ( . )

where td(on), td(of f ), tr, and tf are turn ON delay time, turn OFF delay time, rise time, and fall

time, respectively. It is important to mention that, LV MOSFETs with very little Qrr are utilize

in this thesis. Therefore, Qrr and Vdd terms can be neglected and thus, (2.52) can be re-written

as:

Eon= VddId

tri+ tf u

2 , ( . )

irrespective of the topology. Using (2.45), (2.55), and (2.53), the switching energies and conduction losses are then plotted in PLECS, where the switching and conduction losses are forecasted.