Development of an FPGA-based High-Speed Wireless Communication System in the 60GHz Frequency Band For CERN facilities and 5G deployment

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Master of Science Thesis in Communication Systems

Department of Electrical Engineering, Linköping University, 2018

Development of an

FPGA-based High-Speed

Wireless Communication

System in the 60GHz

Frequency Band For CERN

facilities and 5G deployment

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Master of Science Thesis in Communication Systems

Development of an FPGA-based High-Speed Wireless Communication System in the 60GHz Frequency Band For CERN facilities and 5G deployment

Mohamed Jaoua LiTH-ISY-EX--18/5112--SE Supervisor: Senior Fellow Leif Gustafsson

Ångströmlaboratoriet, Uppsala universitet Dr. Dragos Dancila

Ångströmlaboratoriet, Uppsala universitet Dr. Richard Brenner

Ångströmlaboratoriet, Uppsala universitet Dr. Mikael Olofsson

isy_{, Linköpings universitet} Examiner: Dr. Danyo Danev

isy_{, Linköpings universitet}

Division of Communication Systems Department of Electrical Engineering

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Abstract

The work is devoted in the development and the exploration of the capabilities of the state of art unlicensed 60GHz (V-Band) mm-wave band that has raised so much interest and attention from numerous companies and laboratories for im-plementing Multi-gigabit communications [17] and especially for the 5th genera-tion of cellular network and wireless systems. Implementing a high wireless data transfer system requires a high bandwidth and the one around the 60GHz fre-quency turned out to be a very promising candidate [13]. In this thesis, different protocols were investigated and simulated on MATLAB and implemented on low-cost Field-Programmable Gate Arrays (FPGAs) in order to test its performance with different transmission protocols and systems and insure a robust commu-nication system at the frequency band around 60GHz. Furthermore, the system was tested with a series of different binary sequences such as pseudo-random bi-nary sequences (PRBS-7, PRBS-15, PRBS-23 and PRBS-31) and a high data rate communication link also in the design. The link has been tested in the lab en-vironment and two systems have successfully achieved a relatively low bit-error rate.

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Acknowledgments

I would like to show my profound gratitude to my supervisor Senior fellow Leif Gustafsson for the opportunity and his tremendous help and support during the master work when I was in Uppsala and in Linköping. Moreover, I would like to thank him for steering me to the right direction which was extremely help-ful since it helped me learn much more about designing embedded systems for communication systems.

In addition, I would like to thank my supervisor Dr. Dragos Dancila for giving the opportunity to join the 60GHz CERN related project and work on my master thesis in it. Furthermore, I would like to thank him for his openness and patience whenever I ran into trouble or needed support with my work.

I would also like to thank Prof. Richard Brenner for checking my work, for giv-ing me access to his lab equipment and for givgiv-ing me continuous encouragement and innovative ideas to use and make my work better.

I would also like to thank supervisor Dr. Mikael Olofsson for his help and support. Furthermore, I would also like to thank his for reading and checking my report.

I am thankful to and fortunate enough to get constant encouragement, sup-port and guidance from Examiner Dr. Danyo Danev. I am gratefully indebted to him for providing me with very indispensable comments on this thesis.

Finally, I must express my very profound gratefulness to my family for provid-ing me with constant unfailprovid-ing support and continuous encouragement through-out my years of study and through the process of researching and writing this thesis. This accomplishment would not have been possible without them. Thank you.

Linköping, February 2018 - Mohamed Jaoua

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List of Tables

2.1 Maximum throughput with different Modulation schemes in a noise-less channel . . . 10 2.2 Maximum throughput with different Modulation schemes in a noisy

channel . . . 12 2.3 Different Pseudo-Random Binary Sequence orders [10] . . . 14 2.4 Modulation schemes and the respective number bits needed . . . . 15 3.1 Cyclone V GX FPGA resource distribution . . . 23 3.2 Cyclone V GX clock sources . . . 24 3.3 Hardware implementation of different modulation schemes

ampli-tude for the In-phase axis of the constellation diagram . . . 32 3.4 Hardware implementation of different demodulation schemes

re-gion borders of detection on the constellation diagram . . . 33 4.1 Functions of the Pushbuttons . . . 40 4.2 Functions of the Pushbuttons . . . 41 4.3 Bit-error rate relative to the digital modulation scheme and the

chosen throughput . . . 43 4.4 Bit-error rate relative to the data generation scheme at a

through-put of 3Gbps . . . 50

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List of Figures

1.1 A sample structure of OFDMA [3] . . . 2

1.2 The ATLAS particle detector in CERN [11] . . . 2

1.3 Schematic of a wireless data communication transfer using passive repeaters [19] . . . 3

1.4 A 60GHz patch antenna properties [12] . . . 5

1.5 Schematic of one passive repeater [13] . . . 6

2.1 Rectangular pulse in time and frequency domain . . . 11

2.2 Received signal after passing through a passive repeater structure [12] . . . 12

2.3 A conventional 7th order Pseudo-Random Binary Sequence gener-ator [15] . . . 13

2.4 Different Pseudo-Random Binary Sequences simulated on Matlab over 300 samples interval . . . 14

2.5 Brief digital modulation flowchart followed in the Matlab algorithm 15 2.6 Pseudo-Random Binary Sequence of the 23rd order generated on Matlab transmitted with BPSK digital modulation schemes . . . . 16

2.7 Pseudo-Random Binary Sequence of the 23rd order generated on Matlab transmitted with QPSK digital modulation scheme . . . . 17

2.8 Pseudo-Random Binary Sequence of the 23rd _{order generated on} Matlab transmitted with 16-QAM digital modulation scheme . . . 17

2.9 Pseudo-Random Binary Sequence of the 23rd order generated on Matlab transmitted with 16-QAM digital modulation scheme . . . 18

2.10 Simulated received signal over an Additive White Gaussian Noise channel with different modulation schemes . . . 19

2.11 Maximum Likelihood detection of a 16-QAM digital modulated received signal without estimating the signal attenuation . . . 20

3.1 General system overview . . . 22

3.2 Cyclone V GX Starter Kit . . . 23

3.3 Schematic of the HSMC bank in the Cyclone V device . . . 24

3.4 Basic LVDS circuit operation [5] . . . 25

3.5 AD/DA Data Conversion Card . . . 26

3.6 XTS-HSMC Card . . . 27

3.7 SIVERSIMA 60 GHz transceiver module . . . 28 x

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LIST OF FIGURES xi

3.8 SIVERSIMA 60 GHz transceiver internal circuit . . . 29

3.9 High-speed Serial link generation hardware design . . . 30

3.10 Phase Locked Loop (PLL) . . . 31

3.11 Time delay between the transmitter and receiver . . . 31

3.12 Implementation of ML detection region borders for 16-QAM . . . 33

3.14 Word alignment automatic synchronization state machine . . . 36

4.1 Labview platform of the 60GHz SIVERSIMA transceiver . . . 38

4.2 Transmitted and received sinusoidal signal up-converted and down-converted with the 60GHz SIVERSIMA transceiver measured with RTO-1024 R& S oscilloscope . . . 39

4.4 Pseudo Random Binary Sequences implementation read using Signal-Tap II . . . 41

4.5 Different modulation schemes generated from the FPGA Cyclone V board before transmission obtained using a Rohde & Schwarz RTO 1024 oscilloscope[22] . . . 42

4.6 High-speed digital modulations loop-back test over an SMA cable channel . . . 43

4.7 Different modulation schemes transmitted and received from and to the FPGA Cyclone V board in time domaine . . . 44

4.8 Different modulation schemes received from the SIVERSIMA transceiver to be sent to the FPGA Cyclone V board in time domain . . . 45

4.9 Received QPSK in the FPGA Cyclone V board from the SIVER-SIMA transceiver in time domain measured using MATLAB . . . . 46

4.10 High-speed Serial link loop-back test over an SMA cable channel . 47 4.11 High-speed Serial link loop-back test over an SMA cable channel . 48 4.12 High-speed Serial link loop-back test over the 60GHz channel . . 49

4.13 High-speed Serial link loop-back test over the 60GHz channel . . 50

A.1 High-speed digital modulation system design . . . 59

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Notation

Abbreviations

Notation Meaning

ADC Analog to Digital Converter AWGN Additive White Gaussian Noise

BER Bit Error Rate

BPSK Binary Phase Shift Keying

CERN "Centre Européen pour la Recherche Nucléaire" also known as the European Organization for Nuclear Re-search

dB Decibel

DSP Digital Signal Processing FPGA Field-Programmable Gate Array

HDL Hardware Description Language

I In-phase

ISI Inter-Symbol Interference

ISO International Standards Organization ITU International Telecommunication Union LHC Large Hadron Collider

LSB Least Significant Bits MSB Most Significant Bits

OFDM Orthogonal Frequency Division Multiplexing OOK On-Off Keying

OSI Open System Interconnection PCB Printed circuit board

PRBS Pseudo-Random Binary Sequence

Q Quadrature

QAM Quadrature Amplitude Modulation QPSK Quadrature Phase Shift Keying

RF Radio Frequency SDR Software Defined Radio SNR Signal to Noise Ratio

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1

Introduction

The demand for high speed multimedia and services has been and still exponen-tially on the rise reflecting by consequence the need for efficient solutions in cre-ating communication systems that guarantee a high throughput and quality. For that reason, more advanced methods to send more data is required. The work in this master thesis has been done in a research project at Uppsala University in Ångströmlaboratoriet involving Senior Fellow Leif Gustafsson, Dr. Dragos Dancila and Dr. Richard Brenner activity at CERN where the main task is to design and investigate different transmission protocols and systems in order to implement a high-speed transceiver wireless link at the state of the art 60GHz frequency band for the ATLAS sensors.

1.1 The fifth generation of cellular networks and

wireless systems (5G)

The fifth generation of cellular networks or wireless systems denoted as 5G is a futuristic standard made by the International Telecommunication Union (ITU) aiming for a higher capacity than the current cellular communication systems reaching multi Gb/s per cell. This standard has been under the scope of many telecommunication research groups in the academia and industry were many key technologies involved with its deployment has been defined. One of these in-volved main key technologies is the use of millimeter waves to include them in the Orthogonal Frequency Division Multiplexing (OFDM) system[21]. OFDM is a modulation technique method used to squeeze a large number of sub-carriers in an existing spectrum where their sidebands can overlap and each sub-carrier can still be received and demodulated correctly without interference between its neighboring sub-carriers and that happens because they are set to be orthogonal

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2 1 Introduction

to each other.

Figure 1.1:A sample structure of OFDMA [3]

1.2 Problem statement

The ATLAS detector built in the European Organization for Nuclear Research, known as CERN is a many-layered instrument designed to detect some of the smallest and most energetic particles generated by a Large Hadron Collider (LHC) accelerator as seen in figure 1.2. It is made up of six different detecting subsys-tems enclosed in layers around a collision point to record many data related to these particles for analysis and measurements.

Figure 1.2:The ATLAS particle detector in CERN [11]

The system currently uses optic-fibers to transfer data from the subsystems to the outside. However, creating a wireless communication system would reduce the manufacture cost and would make the system more robust by reducing the number of wires and connectors that lowers the interference from intermediate

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1.2 Problem statement 3

material in the detector. Due to the large amount of data the detector sends and receives, it is important to design a high-speed link. The goal of this project is to investigate different protocols of transmission using an analytic analysis, sim-ulations and actual hardware implementation to create a multi-gigabit link with a relatively low bit-error rate in the band around the 60GHz frequency using a Field-Programmable Gate Array (FPGA) based transceiver to send Radio Fre-quency (RF) waves that will go through a series of repeaters which is in reality one of the main reasons of choosing the 60 GHz frequency. These repeaters are used to have a successful transmission through the layers of a system which has a radioactive environment characteristics and needs to be robust as seen in fig-ure 1.3. The questions that this thesis strives to answer are:

1. How feasible is it to implement a communication link with the state of the art 60 GHz frequency using FPGA?

2. Is it possible to implement high order modulation schemes to be transmit-ted in this frequency band?

3. What are the solutions to reach the highest possible throughput in this en-vironment?

Figure 1.3:Schematic of a wireless data communication transfer using pas-sive repeaters [19]

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4 1 Introduction

Millimeter wave technology (mm-wave)

MM-wave technology has developed exponentially under the scope of researchers in the past years as it constitutes one of the main key technologies which will be used in the fifth Generation (5G) of cellular wireless networks due to the short-age of the currently used spectrum [2] and the need to explore the mm-wave spectrum between 30 and 300 GHz for small local cell structures. Furthermore, the demand for a high data rate is one of the main motivations for the usage of the unlicensed state of the art 60 GHz frequency spectrum which is mainly between 57 and 64GHz. Thanks to its large spectrum of 7 GHz, it can reach ideally up to 7 Gbps by using just BPSK which its symbols need just one bit per symbol time (Ex-plained in section 2.2.1). Furthermore, its small wavelength characteristics is mo-tivating and suitable for this project as it only requires small electronic chips and is definitely not space consuming. In addition, the unlicensed 60 GHz frequency band has advantage over its neighboring frequencies as it has a higher absorption characteristics compared to them[19]which is mainly due to the elevated oxygen molecules energy absorption at that frequency which weakens dramatically the signal energy in the far field propagation. The system uses repeaters to send signals through the detector layers. Therefore, the transmitted signals in the pre-vious layers should not escape and corrupt the data in the forwarded signals by the repeaters which makes the 60 GHz frequency band a perfect candidate for this short distance line of sight transmission application as its signals are easily blocked.

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1.2 Problem statement 5

State of the art 60GHz patch antenna

The type of antenna used in this project is a patch antenna as shown in figure 1.4a. It is a narrow-band and wide beam antenna as shown respectively in figure 1.4b and 1.4c. Furthermore, a patch antenna is a light weight antenna and has a small volume especially at the 60 GHz frequency. Furthermore, its manufactur-ing cost is low and its fabrication is simple and can be made in large quantities since it can be printed on a Printed Circuit Board (PCB).

(a) PCB of a 60GHz patch antenna

(b) Reflected power of a 60GHz patch an-tenna

(c) Far field radiation of a 60GHz patch antenna

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6 1 Introduction

Passive repeaters

As mentioned before, the system uses passive repeaters to reproduce the trans-mitted signals each time they hit a detector layer. And as shown in figure 1.5, as the transmitter (TX) sends an electromagnetic signal to a receiving patch an-tenna that collects the signal, forwards it using its micro strip line and then on the other side another patch antenna is connected to the same micro strip line and forwards it to the receiving antenna (RX). This design enable the possibility of putting them inside the detector layer where it can bend through the gap and continue the line of sight communication.

Figure 1.5:Schematic of one passive repeater [13]

1.3 Development Work flow

In this master thesis project, a complete investigation has been made based on a mathematical analysis, MATLAB simulation and Field-Programmable Gate Array based (FPGA) implementation and system optimization in a lab environment in order to find concrete solutions to establish a wireless communication link that can send data at a high speed. The work will be as follows:

1. Get familiar with the state of the art 60 GHz transceiver system from SIVER-SIMA [9], Cyclone V[4] FPGA device family its possible daughter board al-ternatives by reading and learning from their reference manual and user guide documents.

2. Read and understand the possible embedded system implementations with VHDL, Quartus software and its toolkits, platforms and interfaces[7]. 3. Investigate different communication transmission systems and protocols

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1.3 Development Work flow 7

4. Mathematical analysis, channel estimation, digital communication and al-gorithm design

5. MATLAB system simulation based on the mathematical models

6. FPGA-based implementation of the system designs and apply serial loop-back tests, physical loop loop-back tests and 60GHz transceiver loop loop-back test. 7. Measurements and comparison of the developed systems on different sets

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2

Theory and Mathematical Analysis

In this chapter, a theoretical overview is presented to provide a further under-standing of the problem and the strategy followed to tackle it. Furthermore, a rigorous mathematical analysis is made to ensure an efficient usage of the given resources in this thesis.

2.1 Open System Interconnection (OSI) model

The Open System Interconnection (OSI) model is hierarchical model made by the International Standards Organization (ISO) to divide the different form of layers used in telecommunications and networking into a seven layers model made. In order to transmit data, a process needs to start from the application layer (layer 7) till the physical layer (layer 1) and vice-versa. The work in this thesis are based on the first two layers as follows:

1. Physical (layer 1): This layer is responsible for the transmission of the dig-ital data bits to the the channel using different systems and protocols such as digital modulations. At this layer, data is transmitted using voltage pulses such as the ones used in coaxial cables, radio frequencies such as radios/Software-Defined-Radios or pulses of light such as optical fibers. 2. Data Link (layer 2): This layer is responsible for checking the received bits

from the physical transmission. Furthermore, it is responsible for packag-ing them. This layer is also responsible for encodpackag-ing and decodpackag-ing respec-tively the transmitted and received data in order to minimize the bit-error rate and ensure synchronization between the receiver and the transmitter.

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10 2 Theory and Mathematical Analysis

2.2 Digital modulations and channel capacity

To achieve high data rates, it is essential to study the available bandwidth and the potential capacity a channel in the 60GHz frequency can attain. In this master thesis, the digital modulation schemes that have been studied are BPSK, QPSK, 16-QAM, 32-QAM and 64-QAM. In all reality, the band around the 60 GHz fre-quency can reach up to 9 GHz. However to be on the safe side and have a con-sistent analysis that can be used in the hardware implementation, the spectrum used is only 7 GHz. In order to explore the channel capacity, an interesting anal-ysis is to find the channel capacity of a noiseless channel within the available spectrum of operation and the currently used channel.

2.2.1 Noiseless channel capacity

A noiseless channel capacity assumes that a channel does not have any noise factor and by consequence the Signal-to-Noise Ratio (SNR) goes to infinity.

[SNR]dB= ∞

Nyquist theorem proved that any signal with bandwidth B can be reconstructed with a sampling frequency fcof 2B. By consequence in order to find the maximum

capacity of a channel thus the capacity of a noiseless channel the formula below can be used [8] where B is the bandwidth and M is the number of symbols each modulation scheme uses (2bits).

C = 2B.log₂(M)

Applying this formula on all the modulation schemes provides all the maxi-mum throughput that can be achieved in the ideal case of a noiseless channel.

Table 2.1: Maximum throughput with different Modulation schemes in a noiseless channel

Modulation Schemes BPSK QPSK 16QAM 32QAM 64QAM

Capacity (Gbps) 14 28 56 70 84

However, a noiseless channel can never be practically implemented. However, the math behind computing such ideal channel capacity aids to go further with analysis and estimate the possible throughput the current channel can have (Ex-plained even further in section 2.2.2).

2.2.2 Noisy channel capacity

In practice, a noisy channel is inevitable since transmitted signals are subject to many forms of distortions. Before even transmitting a signal, it is possible that it may experience Inter-Symbol Interference (ISI) from the signal generator. Furthermore, as it propagates it experiences many forms of channel distortion

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2.2 Digital modulations and channel capacity 11

such as Additive White Gaussian Noise (AWGN). Moreover, the transmitted and received signal clocks may experience synchronization problems which lead the time delays, phase and frequency.

Inter-Symbol Interference

In communication systems, data is transmitted as ones and zeros which can be represented as rectangular pulse functions with a finite duration τ in time do-main where the highest amplitude is one, the lowest amplitude is zero and noth-ing in between. However, a rectangular pulse function in time domain is repre-sented as a sinc function with an infinite bandwidth in frequency domain where most of the energy is concentrated between −1/τ and 1/τ as seen in figure 2.1. Yet according to Nyquist criterion, any signal requires at-least twice its band-width for a correct reception which leads to the dilemma of how to acquire twice the bandwidth of a signal with an infinite bandwidth in a channel. The answer is none of the above as a rectangular pulse signal is not sent through the chan-nel. Since the energy of the signal is concentrated at zero, the signal does not need to be fully transmitted. Therefore, it goes through a root raised cosine filter that limits some of the harmonics ensuring a finite bandwidth thus Inter-Symbol Interference is avoided.

(a)Time domain (b)Frequency domain

Figure 2.1:Rectangular pulse in time and frequency domain

Additive White Gaussian Noise

When a channel is used for communication, a transmitted message is disturbed by the Additive White Gaussian Noise (AWGN) and a possible phase mismatch at the receiver side[14]. In the case of coherent detection, the received signal contains both the transmitted message and AWGN as seen in the equation below.

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Mathematical analysis

Mathematical models can insure that the channel with the highest possible ca-pacity is achieved. An interesting way to compute the maximum caca-pacity of a noisy channel is using Shannon – Hartley Equation which uses the bandwidth of a channel, the received signal power and the noise power as seen figure 2.2.

C = Blog2(1 + S/N )

Expanding it to be used for the digital modulation schemes, it gives the fol-lowing formula where Nbitsis the number of bits for each symbol:

C = Blog2(1 + NbitsPrx/Pnoise)

In order to compute the maximum throughput the noisy channel in this project can have, the maximum received signal power and noise power at one frequency has been used to compute to the most possible capacity without taking into con-sideration any other constraints and while assuming it to be the same for all the 7GHz bandwidth .

[Prx]dB= −60dB

[Pnoise]dB= −70dB

Figure 2.2: Received signal after passing through a passive repeater struc-ture [12]

Applying this formula on all the modulation schemes provides all the maxi-mum throughputs that can be achieved in the case of a noisy channel.

Table 2.2: Maximum throughput with different Modulation schemes in a noisy channel

Modulation Schemes BPSK QPSK 16QAM 32QAM 64QAM Capacity (Gbps) 5.55 8.13 11.10 12.11 12.95

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2.3 Pseudo-random Binary Sequence generation study 13

2.3 Pseudo-random Binary Sequence generation

study

As stated in the previous sections, digital modulations are an important goal in this master thesis as they are the key to reach higher modulations while shifting amplitudes and phases to reach higher throughputs. These modulations need a careful study since they are the basis of the next implementations of the digital radio system. Furthermore, in order to test these schemes Pseudo-Random Binary Sequences (PRBS) have been generated of different order such as PRBS7, PRBS15, PRBS23, and PRBS31 which will be explained in the next sub-section.

2.3.1 Pseudo-Random Binary Sequence Generation

Due to the fact FPGA boards do not have any embedded solution for generating random variables, Pseudo-Random Binary Sequences (PRBS) are a great solution to generate a random bit sequence and test the communication system functional-ity and robustness. It works using Linear Feedback Shift Registers (LFSR) which itself operates by left shifting all the states which results in outputting the first state in its registers and assigning a new state to its first register which is the re-sult of an XOR operation between specific registers as shown in figure 2.3. This operation has a default starting state of 1 in all its registers and occurs every ris-ing or fallris-ing edge in the internal clock of the FPGA which depends on the choice and perspective of designers.

Figure 2.3:A conventional 7th order Pseudo-Random Binary Sequence gen-erator [15]

As mentioned previously, different order such as PRBS7, PRBS15, PRBS23, and PRBS31 has been generated in order to test the robustness of the system. In all reality, the orders of PRBS do not affect the result of having a random bit generation. However, the lower the order the faster the pattern will be repeated which is in general of length 2n−_{1 as mentioned in the table 2.3.}

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Table 2.3:Different Pseudo-Random Binary Sequence orders [10]

Bits in the registers Feedback polynomial Length of the random sequence

7 P (x) = 1 + x6_{+ x}7 ₁₂₇

15 P (x) = 1 + x14+ x15 32 767 23 P (x) = 1 + x18+ x23 9 388 607 31 P (x) = 1 + x28+ x31 2 147 483 647

In order to use these sequences, the algorithm has been applied on Matlab to observe the generated patterns in a series of plots of PRBS-7, PRBS-15, PRBS-23 and PRBS-31 on 300 samples before integrating them with the rest of the system as seen in figure 2.4.

(a)PRBS-7 (b)PRBS-15

(c)PRBS-23 (d)PRBS-31

Figure 2.4: Different Pseudo-Random Binary Sequences simulated on Mat-lab over 300 samples interval

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2.4 Digital modulation schemes architecture 15

2.4 Digital modulation schemes architecture

The matlab simulation code is a proof of concept and algorithm used in the FPGA boards (Explained in chapter 3). The design is supposed to receive a pseudo-random binary sequences of bits of order 7, 15, 23, 31, from the binary pattern generator to illustrate what happens when a user or detector starts sending files. Once the sequence has been generated, it must go through a series-to-parallel converter that will create symbols with the appropriate number of bits that would match the type of modulation schemes as given in figure figure 2.5 and table 2.4.

Figure 2.5:Brief digital modulation flowchart followed in the Matlab algo-rithm

Table 2.4:Modulation schemes and the respective number bits needed Modulation Schemes BPSK QPSK 16QAM 32QAM 64QAM

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The digital modulation schemes provide a wireless system with a great use of the spectrum as it involves amplitude and phase shifts to give larger number of bits to a symbol. This technique is widely used and it is even applied in 4G/LTE systems and the futuristic 5G using the basis equations φ0(t), φ1(t) which are

used to create the actual symbol signals si,j(t) seen below [16].

φ0(t) = √ 2/T cos(2πfct), 0 ≤ t < T φ1(t) = √ 2/T sin(2πfct), 0 ≤ t < T si,j(t) = siφ0(t) + sjφ1(t), si, sj∈ {±A, ..., ±nA}

Afterwards, the generated sequences are transformed into one n-elements bi-nary array which constitutes the symbols that will be represented in the right position in the constellation diagram by assigning the appropriate in-phase and quadrature signals.

Binary Phase Shift Keying

Binary Phase Shift Keying (BPSK) is a digital modulation scheme that occurs by taking binary values of 0’s or 1’s in a message and representing that change of state by a 180° phase shift difference in the carrier signal as seen in figure 2.6 where the signal is in its base band state. This scheme results in two scenarios where binary value of the symbol is 1 when signal has a positive value or the symbol has a binary value of 0 if the signal is negative.

Figure 2.6:Pseudo-Random Binary Sequence of the 23rdorder generated on Matlab transmitted with BPSK digital modulation schemes

Quadrature Phase Shift Keying

Quadrature Phase Shift Keying (QPSK) is a digital modulation scheme that oc-curs by shifting the phase of a signal by 90 degrees phase as seen in figure 2.7. Since each each period contains four possible points with a 90 degrees phase shift multiplier, this process results in four possible symbols per sample time. It means each symbol contains two bits at a time.

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2.4 Digital modulation schemes architecture 17

Figure 2.7:Pseudo-Random Binary Sequence of the 23rd_{order generated on}

Matlab transmitted with QPSK digital modulation scheme

16-Quadrature Modulation

16-Quadrature Amplitude Modulation (16-QAM) is a digital modulation scheme that occurs by shifting the phase and amplitude of a signal resulting in 16 differ-ent possible symbols per sample time as seen in figure 2.8. It means each symbol contains 4 bits at a time.

Figure 2.8:Pseudo-Random Binary Sequence of the 23rdorder generated on Matlab transmitted with 16-QAM digital modulation scheme

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64-Quadrature Modulation

64-Quadrature Modulation (64-QAM) is a digital modulation scheme that occurs by shifting the phase and amplitude of a signal resulting in 64 different possible symbols per sample time as seen in figure 2.9. It means each symbol contains six bits at a time.

Figure 2.9:Pseudo-Random Binary Sequence of the 23rdorder generated on Matlab transmitted with 16-QAM digital modulation scheme

2.5 Maximum likelihood detection

Maximum likelihood detection is a statistical procedure used to detect received messages. Channels in real-life applications affect the transmitted signals by causing several types of disturbances such as attenuations caused by the path loss and noise generated by different reasons such as interferences with other RF sources. These disturbances directly affect the previously mentioned constella-tion diagrams and distorts them since they are primarily built by the principle of amplitude and phase shifts. Therefore, the received symbols lose their positions in the diagram. To fix this abnormality, the maximum likelihood detection proce-dure solves this problem by providing the set of transmitted symbols with equal areas in the diagram assuming that the transmitted symbols are equally probable to occur as seen in figure 2.10 where the red dots represent the distorted received signals and the green lines represent the borders of the regions of detection.

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2.6 Channel attenuation estimation 19

(a)BPSK (b)QPSK

(c)16-QAM (d)64-QAM

Figure 2.10: Simulated received signal over an Additive White Gaussian Noise channel with different modulation schemes

2.6 Channel attenuation estimation

In wireless communication, it is important to have a time invariant channel to transmit data where a channel does not change its properties while transmission is in progress. But in practice, a channel has a limited time where it does not change its properties due to different interferences and disturbances in the envi-ronment of transmission and the actual properties of the transmission band in use. One method of overcoming this issue is by sending pilot signals in which both transmitter and receiver have knowledge about where the actual received signal can be formulated with the following equation where α stands for the at-tenuation factor, x the transmitted message and N the noise.

Yp = αXp+ N

Since the receiver is a aware of the value of the pilot signal, α can be approxi-mated while neglecting the effect of the noise in this operation. This operation

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is very important since the decision regions in a Maximum Likelihood detector can be affected and cause erroneous detection as shown in figure 2.11 where the regions are not adapted to the channel.

Figure 2.11:Maximum Likelihood detection of a 16-QAM digital modulated received signal without estimating the signal attenuation

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3

System Design and Methods

The system mainly contains a host PC, a Field-Programmable Gate Array (FPGA) and 60GHz transceiver. The host PC uses Intel Quartus Prime [7] to program and communicate with the FPGA. The FPGA is programmed to generate the PRBS and transform them to symbols and output them as In-Phase and Quadrature signals. The transmitter board is designed to take the inputted signals and put them through a mixer that mixes them with the 60GHz local oscillator to output one 60GHz RF signal. The transmitted RF signal travels through its channel to reach its destination at the receiver board. The receiver demodulates the signal and takes it back to base band which itself gets demodulated at the FPGA to find the exact sent bits as shown in figure 3.1.

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22 3 System Design and Methods

Figure 3.1:General system overview

3.1 Field-Programmable Gate Array (FPGA)

Field-programmable gate array is an integrated circuit (IC) that can be programmed to solve diverse engineering problems related to embedded systems. Its robust and customizable interface had an important influence in choosing it to be used in this master thesis design to generate a high-speed link. Furthermore, its rela-tively high processing power made the implementation of different modulation schemes and different throughputs possible. In this master thesis, the Altera Cy-clone V GX Starter Kit was used to implement high order modulations with a digital to analog converter card from BPSK to 64-QAM. Furthermore, the same board was also used thanks to its high-speed serial ports that can reach to multi-gigabit per one lane in the second system design used in this master thesis.

3.2 FPGA-based System designs

In this master thesis, two FPGA designs were used to the purpose of finding the best fitting design and the best method of implementation of the communication link.

3.2.1 Altera Cyclone V GX Starter Kit Board

The Cyclone V Starter Kit presents a robust hardware built around the Cyclone V GX 5CGXFC5C6F27C7 FPGA as shown in figure 3.2. This board was chosen thanks to low-cost and power need compared to other FPGA based board. Yet, it is fully equipped and capable to withstand the aimed application. Furthermore,

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3.2 FPGA-based System designs 23

its high-speed mezzanine card (HSMC) connectors are extremely helpful for this master thesis as it offers a wide range of system design expansions and solutions.

Table 3.1:Cyclone V GX FPGA resource distribution

Resource 5CGXFC5C6F27C7

Programmable Logic Elements 77K

Embedded memory 4884K bits

PLL 6

Hard Memory Controllers 2

Transceivers six lanes of 3.125G

Figure 3.2:Cyclone V GX Starter Kit

Clocking

The Cyclone V GX contains many on-board oscillators generated by two indepen-dent clock sources that are fundamental for data transmission and provide a flex-ibility in the design in choosing different clocking sources and ease its portability.

HSMC

The Cyclone V GX contains an HSMC port with many single-ended high-speed serial ports on most pins capable of achieving high data rates beside its multi-gigabits differential signals that can reach up to 3.1 Gbps. Furthermore, these HSMC I/O pins can be arranged and programmed as shown in figure 3.3.

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Table 3.2:Cyclone V GX clock sources Source I/O Frequency

X2 3.3v 50MH z

U20 2.5v 50MH z

U20 LVDS 125MH z

U20 1.5-PCML 125MH z U20 1.5-PCML 156MH z

(a)Serial pins (b)Serial pins

(c)Multi-Gigabits pins

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Transistor-to-Transistor Logic (TTL)

Transistor-to-Transistor Logic (TTL) is a single ended standard of signaling where the output of a TTL port is between 3.3-5V and referenced to ground. This single ended characteristic of TTL makes it subject to interferences and disturbance that lead to signal distortion and errors at the receiver side.

Low Voltage Differential Signaling (LVDS)

Low Voltage Differential Signaling (LVDS) is a relatively new technology used to send signals at high speed. LVDS is different than TTL where it sends its signals in a differential pair of lines. As shown in figure 3.4, the receiver needs to subtract the voltage value of the positive port from the negative port because the difference between the two determines whether the actual value of the data that was being sent is a ’1’ or a ’0’. Switching the logic state from zero to one or vice-versa is done by changing current flow across at the terminal resistor at the receiver side. This dual port feature of the LVDS standard is great for data transfer applications since the noise induced by the transmission environment in one of the ports is induced in the second one which is canceled at the receiver side since it has to perform the subtraction operation.

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3.2.2 AD/DA card

In order to generate a different modulation schemes and implement a high-speed data link, the Cyclone V Board can be connected through its HSMC port to an Analog to Digital and Digital to Analog (AD/DA) Data Conversion Card as shown in figure 3.5. It is used to output the modulated symbols. However, one disadvan-tage to this daughter card is that it has a limited sample rate of 150MSPS. Nev-ertheless, the daughter board fulfills the aim of the master thesis of comparing the behavior of the channel with high modulation orders thanks to its two SMA RF transmitting ports and two receiving ports which can signify the In-phase and Quadrature phase channels. Furthermore, there are faster AD/DA converter boards that can achieve multi-gigabit communication links. However, the pur-pose of using this particular board is a proof of concept of the possibility of using similar algorithms on the 60GHz channel.

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3.2.3 XTS-HSMC Card

This design is also made to generate a serial sequence and to implement a multi-Gigabit data link. The Altera Cyclone V GX FPGA Board has extra LVDS transceivers that can create a multi-Gigabit link which ensures a high data rate through its pins at the HSMC port which is connected through it to a XTS-HSMC[1] daugh-ter board as shown in figure 3.6.

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3.3 SIVERSIMA 60GHz transceiver

The SIVERSIMA 60GHz transceiver is an up and down converter platform which has a local oscillator which functions at a large spectrum operating between 58 and 63 GHz as shown in figure 3.7. It is best suited for V-band application which has a frequency band between 57 and 66 GHz. This transceiver has mainly two inputs and two outputs of interest: In-phase and Quadrature-phase input and output signals (I/Q). Furthermore, it outputs a modulated RF signal though its monopole antenna as an electromagnetic signal oscillating at the state of the art 60GHz frequency. At the receiver side, it has a receiving monopole antenna which converts it back base band and outputs the In-phase and Quadrature-phase output signals through its I/Q ports as shown in figure 3.8.

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3.3 SIVERSIMA 60GHz transceiver 29

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3.4 Digital modulation system design

In order to implement a communication link with an advanced digital modu-lation schemes, the Altera Cyclone V GX Starter Kit FPGA Board and AD/DA daughter card was connected. Furthermore, the design was implemented using VHDL code and methods of integrating different modules to create the commu-nication system.

Figure 3.9:High-speed Serial link generation hardware design

3.4.1 Phase Locked Loop (PLL)

The phase locked loop (PLL) is a very important and commonly used circuit in radio and embedded systems applications. It is a feedback system combining a voltage controlled oscillator (VCO) and a Frequency Phase Detecor (PFD). As shown in figure 3.10, the PFD detects the difference between the Reference fre-quency and phase with the frefre-quency and phase of the feedback signal which based on them it controls the charge pump, loop filter and VCO. The VCO is outputs a higher or lower frequency signal based on the control voltage coming from the PFD. After a number of iteration, the reference signal and the feedback signal get synchronized and their phase and frequency become the same. At this state, the PLL is said to be phase locked. The value of M is a multiplication fac-tor leading FV CO to oscilate M times FREF. However, the value of N does the

opposite operation where FREF oscilates N times less than FI N. The result of

these operations is the frequency of VCO being equal fI N ∗M/N . K and V are

post-dividers used to have different frequency signal at the output which means: fOU T 1= (fI N ∗M)/(N ∗ K).

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3.4 Digital modulation system design 31

Figure 3.10:Phase Locked Loop (PLL)

3.4.2 Synchronization

In practice, different interferences in the channel cause many disturbances in the transmission such as a varying time delay. Retrieving data from a modulated signal that has gone through a channel is challenging where data can unsynchro-nized leading to data being lost and undetected. However, retrieving data from the two signals I and Q is a greater challenge because together they construct a symbol every sample time. So, a coherent detection must be achieved to retrieve the data. The transmitter initiates the transmission by sending the same Byte on I and Q channels and waits for acknowledgment from the receiver. Once an acknowledgment is received the transmitter sends a buffer contains a start Byte, an end Byte and in between the content of the message as shown in figure 3.11. Both Start and End Byte are agreed upon between both parties which insures a synchronized channel. This procedure continues to occur until data is completely transmitted.

Figure 3.11:Time delay between the transmitter and receiver

3.4.3 Bit Error Rate

The Bit Error Rate (BER) is a mathematical quality measure performed to esti-mate the error probability of a channel in a sense where it is possible to estiesti-mate

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how many bits over a set of bits will be erroneous once put into a system. In gen-eral, it is done by taking the ratio of erroneous bits count over a finite sequence of transmitted bits.

BER = Erroneous bit count T otal number of transmitted bits

In order to detect the sent information, the receiver system needs to detect the Start Byte and then directly start computing the erroneous bit count using a com-parison between the transmitted and the received bit. Once a mismatch occurs, the erroneous bit count increases by one while the number of transmitted bits always increases by one when a bit is received.

3.4.4 Modulator

To generate high order modulation schemes in the system, the digital to analog card was used. The FPGA board generates only digital signals with high and low levels. However, digital modulation schemes require different signal amplitudes to represent its symbols. The Altera AD/DA daughter board receives 14 digital signals from the main FPGA, and then converts them into one signal with an amplitude varying from -1 to 1 V as shown in table 3.3 where A is the maximum amplitude the AD/DA can achieve.

Table 3.3: Hardware implementation of different modulation schemes am-plitude for the In-phase axis of the constellation diagram

Modulation

In-phase Amplitude

Quadrature phase Amplitude

BPSK

±

_A

QPSK

±

_A

±

_A

16QAM

±

_{0.33A , A}

±

_{0.33A, A}

64QAM

±

_{0.14A, 0.43A, 0.72A, A}

±

_{0.14A, 0.43A, 0.72A, A}

A 14-bit digital to analog converter converts the symbol that needs to be trans-mitted to a distinctive numerical value. A 14-bit converter gives its highest am-plitude when all its bits are high and vice-versa. However, in this application a signed decimal is converted to a signed binary number. By consequence means that the highest possible amplitude happens when 13-bits are high and the least significant bit signifies the sign of the number. It results on the maximum ampli-tude denoted as "A" being equal to 8191.

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3.4 Digital modulation system design 33

3.4.5 Demodulator

As mentioned in section 2.4, Maximum likelihood procedure is implemented to detect the right symbols in the receiver side. The borders of detection are calcu-lated to match equal regions of detection following the assumption of an equally probable symbols generation as shown in table 3.4 and figure 3.12. Furthermore, the amplitude of the transmitted signal gets attenuated as it travels through the channel which causes the amplitude "A" at the receiver side to be not equal to the one used to modulate the signal that was transmitted. For that reason, the maximum amplitude is estimated by a sequence of maximum amplitudes before starting to demodulate.

Table 3.4:Hardware implementation of different demodulation schemes re-gion borders of detection on the constellation diagram

Modulation In-phase Region borders Quadrature phase Region borders

BPSK ±₀

QPSK ±₀ ±₀

16QPSK ±_{0, 0.67A} ±_{0, 0.67A}

64QAM ±_{0, 0.29A, 0.58A, 0.87A} ±_{0, 0.29A, 0.58A, 0.87A}

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3.5 High-speed serial link implementation

High-speed serial link is a growing technology recently heavily researched which uses the very simple On-Off Keying (OOK) modulation. Thanks to its simplicity and efficiency, it can create multi-Gigabit links while reducing devices footprint which means the reduction of the processing power the devices occupy. Further-more, its structure eliminates the need for analog to digital and digital to analog converters to generate high-speed data rates which reduces the high digital sig-nal processing power need and makes it easier to recover the transmitting clock. In addition, it makes encoding and decoding between transmitter and receiver simpler since it reduce synchronization issues.

In order to implement a serial communication link, the Altera Cyclone V GX starter kit board and the XTS-HSMC daughter card have been connected together to make use of the high speed serial transceiver channels. The system is con-trolled using a NIOS II controller that uses an Avalon Master to control the packet generation and packet checker. The packet generator is responsible for generat-ing the data such as PRBS-7, PRBS-15, PRBS23 and PRBS-31 that will be sent to a Custom PHY 1 lane block that is used to encode the transmitted bits and decode the received ones using 8B/10B encoding/decoding technique. Further-more, the Custom PHY block is also responsible for synchronizing the transmit-ter and receiver side using the word alignment automatic synchronization state machine technique as shown in figure 3.10. The design was implemented using the recently developed QSYS Altera system integration platform of Intel Quartus Prime standard software.

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3.5 High-speed serial link implementation 35

3.5.1 Transceiver Toolkit

Transceiver toolkit is a platform made by Altera that uses system console to con-trol different sides of a QSYS system to validate a transceiver link. Furthermore, it gives the ability to change certain block parameters and conditions of trans-mission in real time. In addition, it is important to note that it also displays the bit-error rate in real time which is important to validate the communication system.

3.5.2 Nios II processor

A Nios II processor system in an Altera device is a system similar to a micro-controller. It is made of a Nios II processor core, a set of on-chip peripherals, on-chip memory, and interfaces to off-chip memory. Furthermore, it is possible with it to design efficiently using an Altera development kit such as the Cyclone V GX Starter kit board used in this thesis. Similar to a microcontroller, it uses its own set of guidelines and tools and its tool flows are built on the GNU C/C++ compiler which gives an acquainted environment for software development[18].

3.5.3 Altera Custom PHY block IP core

The Custom PHY block is an IP core in the Quartus Prime software that targets an Altera device and maximize its performance. Furthermore, it can be connected to MAC layer of a developed application to create a transceiver link from 0.611 to 3.125 Gbps per one lane for the Cyclone V GX board. With this ip core, it is possible to implement 8b/10b encode and decode, word alignment automatic synchronization state machine and Rate matching.

8b/10b encoding technique

8b/10b encoding technique is an algorithm developed by IBM used to ensure a solid data transmission that is less susceptible to errors in the receiver side. This algorithm takes an 8-bit code and transforms it into a 10-bit code where it cuts each original 8-bit code into two groups: a three most significant bits (MSB) and five least significant bits (LSB). Each group gets embedded into a new code group with an extra bit. The extra bits depends on a running disparity checker block which calculates the number of zeros and ones in each group provides and assign the extra bits with a binary value that equals with the lesser bits in the group. Furthermore, the two groups do not return to their original position but they take the original position of each other[20].

Word alignment automatic synchronization state machine

The automatic synchronization state machine is a way to synchronize the mitter and receiver to initiate the communication link thus start the data trans-fer. In order for the receiver to know at what exact sample time to start signal processing the received serial signal and save the acquired data, there must be

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a convened message that notifies the receiver which initiates a handshake with the transmitter. Furthermore, the automatic synchronization machine protocol checks the consecutive erroneous bits. When they reach the threshold set by the user or designer, the communication link erupts and a new handshake must be established for a new data transfer to start as shown figure 3.11.

Figure 3.14:Word alignment automatic synchronization state machine

Rate matching

High speed systems usually depend on on several clocks. A receiver usually has two clocks: an internal clock and a receive clock. Rate matching is a technique utilized to fix synchronization between the two clocks which if not fixed causes information loss. Furthermore, several protocols suggest to merge transmitted data with space or idle characters to help rate matching process.

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4

Implementation and Results

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38 4 Implementation and Results

In this chapter, different implementations of the 60GHz communication link is shown. Furthermore, the results and measurements of these implementations are presented below.

4.1 60GHz SIVERSIMA transceiver platform

The 60GHz SIVERSIMA is controlled using a Labview [6] platform as shown in figure 4.1 where it up converts any received within the range of operation to the carrier frequency of 60GHz at the transmitter side. Furthermore, it also down converts the received signal to the baseband range as shown in figure 4.2 where a sinusoidal signal oscillating at a frequency of 1GHz is transmitted and received successfully with the 60GHz SIVERSIMA transceiver.

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4.1 60GHz SIVERSIMA transceiver platform 39

Figure 4.2: Transmitted and received sinusoidal signal up-converted and down-converted with the 60GHz SIVERSIMA transceiver measured with RTO-1024 R& S oscilloscope

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4.2 Digital modulation schemes implementation

results

As mentioned previously, this system was designed to transmit data using dig-ital modulation techniques such as BPSK, QPSK, 16-QAM and 64-QAM using the Altera Cyclone V GT starter kit and the AD/DA daughter board as shown in figure 4.3 where the first push button controls the modulation schemes, the sec-ond push button controls the pseudo-random binary sequence order an the third push button resets the system as shown in the table below.

Figure 4.3:High-speed Serial link generation hardware design

Table 4.1:Functions of the Pushbuttons KEY Description

KEY0 Next modulation order KEY1 Next PRBS order

KEY2 Reset

The pushbuttons are just boolean state keys where they can hold states of ’0’ or ’1’. Once, a pushbutton is not pressed, it is set to be ’1’ by default. Furthermore, the keys are used to increase to the next mode. A counter is used to increase by one every time a pushbutton is pressed changing its state to zero as shown in table 4.2 where the KEY states that correspond to the modulation schemes and PRBS order are presented. Furthermore, the modulation scheme and the PRBS order are shown on two 7-segment displays.

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4.2 Digital modulation schemes implementation results 41

Table 4.2:Functions of the Pushbuttons

KEY states 0 1 2 3 4

KEY0 BPSK QPSK 8-QAM 16-QAM 64-QAM

KEY1 PRBS-7 PRBS-15 PRBS-23 PRBS-31

KEY2 Reset system Do not rest system

Figure 4.4: Pseudo Random Binary Sequences implementation read using SignalTap II

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In order to make sure that the system is functional, the output from the board was measured using an oscilloscope as shown in figure 4.5 where the In-phase and the Quadrature phase channels are presented.

(a)BPSK (b)QPSK

(c)16QAM (d)64QAM

Figure 4.5:Different modulation schemes generated from the FPGA Cyclone V board before transmission obtained using a Rohde & Schwarz RTO 1024 oscilloscope[22]

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4.2.1 Internal loop-back test

The system was tested using a serial loop-back test where the transmitted signal is directly assigned to the received signal which ultimately led to a full success of the operating system with zero errors.

4.2.2 Loop-back test over an SMA cable

The system was tested using a physical loop-back test where the transmitted sig-nal leaves the board outputting an asig-nalog sigsig-nal, goes through an SMA cable and then returns to the board to go through an analog to digital conversion as shown in figure 4.6.

Figure 4.6:High-speed digital modulations loop-back test over an SMA ca-ble channel

The physical loop-back test was tested using a total of one Gbits of transmit-ted data as shown in the results table 4.1. The received data tends to get distortransmit-ted as the throughput and the modulation scheme order increases since higher mod-ulation schemes require more processing time and power to send a symbol that contains more bits.

Table 4.3: Bit-error rate relative to the digital modulation scheme and the chosen throughput

Throughput BPSK QPSK 16QAM

10 Mbps 0.00 0.00 N/A

25 Mbps 0.00 0.00 N/A

40 Mbps 0.43 0.68 N/A

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(a)BPSK

(b)QPSK

(c)16QAM

Figure 4.7: Different modulation schemes transmitted and received from and to the FPGA Cyclone V board in time domaine

4.2.3 Loop-back over the state of the art 60GHz channel

The system was tested over the 60GHz channel where the received signals are displayed using the R&S RTO-1024 oscilloscope and the constellation diagram was also built in the instrument as shown in figure 4.9 where the received signals experienced distortion and attenuation from the channel. The QPSK modulated signal has clearly experience minor deterioration. However, the constellation di-agram of received 16-QAM modulated signal has been affected after being trans-mitted through the 60GHz channel where it is hard to distinguish the modulation order from it.

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(a)QPSK

(b)16QAM

Figure 4.8: Different modulation schemes received from the SIVERSIMA transceiver to be sent to the FPGA Cyclone V board in time domain

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(a)QPSK

Figure 4.9: Received QPSK in the FPGA Cyclone V board from the SIVER-SIMA transceiver in time domain measured using MATLAB

4.3 High-speed serial link implementation results

In order to implement a serial communication link, the Altera Cyclone V GX starter kit FPGA board and the XTS-HSMC daughter card have been connected. Furthermore, the design was implemented using the recently developed QSYS Al-tera system integration platform of Intel Quartus Prime standard software. The point of this implementation is to test the robustness of a high-speed serial link and for that reason the XTS-HSMC daughter card was chosen thanks to its multi-gigabit transceivers that can send data at over 3 Gbps over one lane which fulfill the purpose.

4.3.1 Internal Loop-back test

Before performing the actual hardware implementation tests, it is important to test the functionality and correctness of the system and the followed algorithm by performing a serial loop-back test which in reality means that no signal leaves the board but it directly loops back inside the board. This test was a full success where the data had no bit-error at the receiver side.

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4.3 High-speed serial link implementation results 47

4.3.2 Loop-back test over an SMA cable channel

One step before sending the data to a 60GHz band up-converter is a loop-back test performed over an SMA cable channel where the serial data leaves the board goes through an SMA cable channel and returns to the board as shown in fig-ure 4.10. Note that two SMA cables are used because an LVDS I/O parameters provide much higher data rates and their use needs to use both positive and neg-ative pins for each lane.

Figure 4.10:High-speed Serial link loop-back test over an SMA cable chan-nel

This setup was tested over different data rates transmissions and types of pseudo-random binary sequences and the results are impeccable as no errors where found in the system as shown in figure 4.12 where over 1.4 Terabits of raw data were sent through the channel with zero bit-error rates.

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Figure 4.11:High-speed Serial link loop-back test over an SMA cable chan-nel

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4.3 High-speed serial link implementation results 49

4.3.3 Loop-back over the state of art 60GHz channel

Finally, the Cyclone V FPGA board and the XTS daughter card have been con-nected to the SIVERSIMA V-band converter to test the setup on the point-to-point radio application where the two LVDS ports of the XTS where connected on the I and Q ports of the SIVERSIMA as shown in figure 4.12. Since signals sent over the 60GHz band are subject to a high attenuation and distortion level, implement-ing this setup to send data though it was challengimplement-ing. However, it depended on the transmitter and receiver parameters such as the pre-emphasis order and dif-ferential output voltage (VOD) control value at the transmitter side and the DC

gain and Equalization control at the receiver side as shown in figure 4.13.

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Figure 4.13:High-speed Serial link loop-back test over the 60GHz channel This setup was also tested over different data rates transmissions, types of pseudo-random binary sequences and types of radio wave generators. And as shown in table 4.4, the bit error rate kept on increasing as the order of the pseudo-random binary sequence of the pattern generator increased. Furthermore, the pre-emphasis order and VOD had a big role in optimizing the communication

link.

Table 4.4:Bit-error rate relative to the data generation scheme at a through-put of 3Gbps

Low frequency High frequency PRBS7 PRBS15 PRBS23 PRBS31 BER 1.65E-3 1.12E-6 3.81E-3 4.31E-3 4.52E-3 4.47 E-3

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5

Conclusion and future work

In this chapter, the thesis results from both systems are discussed. Furthermore, the methods used in this thesis are evaluated. Both systems have been success-fully implemented with a generated random data such as 7, 15, PRBS-23 and PRBS-31 to represent a transmitted data by users and ensure its correct detection.

Digital modulation schemes implementation

The implementation of the digital modulation design on the Cyclone V GX starter kit FPGA-based board was successful with modulation schemes reaching up tp 64-QAM modulation order. However, the speed of transmission could not exceed 25 Mbps for BPSK and 50 Mbps for QPSK in order to have a coherent transmis-sion. This relatively slow data rate is expected since the maximum sampling frequency of the daugther board is 150 MSPS. Transmitting with higher digital modulation orders is a challenge with this daughter board as more delays and signal attenuations are introduced which affects the system performance. Trans-mitted data with higher modulation orders such as 16-QAM and 64QAM could not be retrieved again as their amplitude and phase shift were distorted during the transmission. Furthermore, it is important to note that the synchronization between the I and Q channels was also challenging during this work as each chan-nel introduces its own time delay which was rectified with the use of a buffer that saves the demodulated data and saves in it. The system also has a series of over-shoots when the transmitted symbol is changed making it even harder to detect signals after being transmitted through the state of the art 60GHz channel. This noise and overshoots are introduced because of many factors including the use of single ended ports that can introduce noise and interference from the lab.

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52 5 Conclusion and future work

High-speed serial link implementation

The implementation of the serial link on the same FPGA board was also success-ful. The serial data was transmitted from the serial port with a data rate reaching 3 Gbps. The use of LVDS ports had a great impact in acquiring this high data rate with zero bit error rate for the SMA cable test and a relatively low bit error rate of the order of 10−

3 for the 60GHz transceiver link. Furthermore, the noise from the positive and negative line are subtracted and eliminated at the receiver side which makes the system more robust and less vulnerable. It is important to note that use of serial transmission requires less processing power since it does not need a digital modulator nor demodulator and is directly transmitted through the pins of the HSMC port of the Cyclone board.

5.1 Conclusion

This thesis discusses different transmission systems algorithms simulations, im-plementations and their feasibility. The equipment used in this thesis is the Altera Cyclone V GX Starter Kit FPGA Board, AD/DA daughter card and XTS-HSMC daughter card. The AD/DA daughter card was used to convert 15-bits of data sent from the FPGA board to convert it to an analog signal. However, the XTS-HSMC daughter card was used to take advantage of the LVDS pins of this FPGA board to implement a high-speed data link. The algorithms were first tested on MATLAB to check their feasibility and accuracy with different scenar-ios before implementing them on the hardware. Furthermore, the systems were tested in a lab environment where the 60 GHz transceiver was installed. In addi-tion, PRBS-7, PRBS-15, PRBS-23 and PRBS-31 were used to test the transmission system which represent random data being transmitted by users where no se-quence is repeated for a known number of generated bits. Most of the transceiver results were as expected where digital modulation schemes and high speed serial data transmission were implemented. However, the received signal from the 60 GHz down-converter made it difficult to have a coherent detection with high mod-ulation schemes especially because the received signal had many spikes and was distorted. Nevertheless, the transmission schemes have been tested with single ended port and LVDS port which resulted on a better and more robust commu-nication system using the LVDS serial commucommu-nication on the 60GHz frequency band. This thesis concludes that the use of LVDS based serial communication link can be more rewarding and economic than the use of AD/DA converters to create advanced modulation schemes system for a line-of-sight short distance communication link on the 60 GHz frequency band.

Development of an FPGA-based High-Speed Wireless Communication System in the 60GHz Frequency Band For CERN facilities and 5G deployment

Master of Science Thesis in Communication Systems

Department of Electrical Engineering, Linköping University, 2018