A Comparison of EDMOS and Cascode Structures for PA Design in 65 nm CMOS Technology

Institutionen för systemteknik

Department of Electrical Engineering

Examensarbete

A Comparison of EDMOS and Cascode Structures

for PA Design in 65 nm CMOS Technology

Master thesis performed in Electronic Devices

by

Mahir Al-Taie

LiTH-ISY-EX--13/4715--SE

Linköping September 2013

TEKNISKA HÖGSKOLAN

LINKÖPINGS UNIVERSITET

Department of Electrical Engineering

A Comparison of EDMOS and Cascode Structures

for PA Design in 65 nm CMOS Technology

Master thesis

Performed in Electronic Devices

Department of Electrical Engineering

Linköping Institute of Technology

by

Mahir Al-Taie

LiTH-ISY-EX--13/4715--SE

Supervisor: Professor Atila Alvandpour

Examiner: Adjunct Professor Ted Johansson

Presentation Date

11-09-2013 _______________________

Publishing Date (Electronic version) 23-09-2013

Department and Division

Department of Electrical Engineering

Type of Publication Licentiate thesis X Degree thesis Thesis C-level Thesis D-level Report

Other (specify below)

Language

X English

Other (specify below)

Number of Pages 78

ISBN (Licentiate thesis)

ISRN: LiTH-ISY-EX--13/4715--SE Title of series (Licentiate thesis) Series number/ISSN (Licentiate thesis)

Abstract

This thesis addresses the potential of implementing watt-level class-AB Power Amplifier (PA) for WLAN in 65 nm CMOS technology, at 2.4 GHz frequency. In total, five PAs have been compared, where the examined parameters were output power (Pout), linearity, power added efficiency (PAE), and area consumption. Four PAs were implemented using conventional cascode topology with different combination of transistors sizes in 65nm CMOS, and one PA using a high-voltage Extended Drain MOS (EDMOS) device, implemented in the same 65 nm CMOS with no process or mask changes. All schematics were created using Cadence Virtuoso CAD tools. The test benches were created using the Agilent's Advance Design System ( ADS) and simulated with the ADS-Cadence dynamic link.

The simulation results show that the EDMOS PA (L=350 nm) has the smallest area, but has harder to reach the required Pout. Cascode no. 3 (L= 500,260 nm) has the best Pout (29.1 dBm) and PAE (49.5 %). Cascode no. 2 (L= 500,350 nm) has the best linearity (low EVM). Cascode no. 1 (L=500,500 nm) has low Pout (27.7 dBm). Cascode no.4 (L=500,60 nm) has very bad linearity.

The thesis also gives an overview for CMOS technology, discusses the most important aspects in RF PAs design, such as Pout, PAE, gain, and matching networks. Different PA classes are also discussed in this thesis.

Publication Title

A Comparison of EDMOS and Cascode Structures for PA Design in 65 nm CMOS Technology

Author

Mahir Jabbar Rashid Al-Taie

URL, Electronic Version

http://www.ep.liu.se

Keywords

To my country Iraq!

To my Lovely Parents!

Abstract

This thesis addresses the potential of implementing watt-level class-AB Power Amplifier (PA) for WLAN in 65 nm CMOS technology, at 2.4 GHz frequency. In total, five PAs have been compared, where the examined parameters were output power (Pout), linearity, power added efficiency (PAE), and area consumption. Four

PAs were implemented using conventional cascode topology with different combination of transistors sizes in 65nm CMOS, and one PA using a high-voltage Extended Drain MOS (EDMOS) device, implemented in the same 65 nm CMOS with no process or mask changes. All schematics were created using Cadence Virtuoso CAD tools. The test benches were created using the Agilent's Advance Design System (ADS) and simulated with the ADS-Cadence dynamic link.

The simulation results show that the EDMOS PA (L=350 nm) has the smallest area, but has harder to reach the required Pout. Cascode no. 3 (L= 500,260 nm) has the best Pout (29.1 dBm) and PAE (49.5 %). Cascode no.

2 (L= 500,350 nm) has the best linearity (low EVM). Cascode no. 1 (L=500,500 nm) has low Pout (27.7

dBm). Cascode no.4 (L=500,60 nm) has very bad linearity.

The thesis also gives an overview for CMOS technology, discusses the most important aspects in RF PAs design, such as Pout, PAE, gain, and matching networks. Different PA classes are also discussed in this thesis.

ACPR

Adjacent Channel Power Ratio

ADS

Advanced Design System

ASK

Amplitude Shift Keying

BV

Breakdown Voltage

CF

Crest Factor

CMOS

Complementary Metal-Oxide-Semiconductor

DC

Direct Current

EDMOS

Extended Drain Metal-Oxide-Semiconductor

ednfet

Extended Drain N-channel Metal-Oxide-Semiconductor

EVM

Error Vector Magnitude

FET

Field-Effect Transistor

FSK

Frequency Shift Keying

GC

Gain Compression

HB

Harmonic Balance

HV-MOS

High Voltage Metal-Oxide-Semiconductor

IEEE

The Institute of Electrical and Electronics Engineers

LDMOS

Laterally Diffused Metal-Oxide-Semiconductor

MOSFET

Metal-Oxide-Semiconductor Field Effect Transistor

NMOS

N-channel Metal-Oxide-Semiconductor

PA

Power Amplifier

PAPR

Peak-to-Average Power Ratio

PDK

process design kit

PEP

Peak Envelope output Power

PMOS

P-channel Metal-Oxide-Semiconductor Field-Effect Transistor

QAM

Quadrature amplitude modulation

QPSK

Quadrature Phase Shift Keying

RF

Radio Frequency

SoC

System-on-Chip

TDDB

Time Dependent Dielectric Breakdown

TX

Transmitter

UWB

Ultra-Wide Band

VLSI

Very-large-scale integration

W-LAN

Wireless Local Area Network

I would like to express my deepest appreciation to all the people who have helped me during the

conduction of this thesis work.

I would like to thank my examiner Adjunct Professor Ted Johansson for giving me the chance to

work in this field, and for his valuable ideas, guidance and help during this project. Thank you so

much for the experience.

I also would like to express my gratitude to my supervisor Professor Atila Alvandpour, for all his

insightful discussions and guidance which was given with the most passion and generosity in time

and knowledge.

I am also grateful for all the valuable help that I have received from Ph.D students, Fahad Qazi,

Amin Ojani, Ameya Bhide, Ali Fazli, Muhammad Irfan Kazim, and Daniel Svärd. I am also

thankful from all other researchers who have helped me during this project.

A big thank you goes to my parents and my Lovely wife Maya, for their unconditional love and

support. I am also thankful to all my friends, who have enriched my life with love and joy.

My acknowledgements to Linköping University, for providing all the resources that I needed to

learn and grow.

Mahir Jabbar Rashid Al-Taie

Linköping, 2013

Abstract

ix

Abbreviations

x

Acknowledgement

xii

List of Figures

xvii

List of Tables

xix

Chapter 1 Basic MOS Device Physics

1

1.1

Brief History

1

1.2

MOSFET Structure

1

1.3

MOS I/V Characteristic

4

1.3.1

Threshold Voltage

4

1.3.2

Operating Regions

6

1.3.2.1

The Deep Triode Region

8

1.3.2.2

The Saturation Region

9

1.4

Reliability issues in Power Amplifier Design

10

1.4.1

Drain-Bulk Breakdown

10

1.4.2

Hot Carrier Effect

10

1.4.3

Time Dependent dielectric Breakdown TDDB

10

1.4.4

Punch-through

10

Chapter 2 Important Aspects in Power Amplifier Design

11

2.1

Introduction

11

2.2

Digital Modulation

12

2.2.1

Bandwidth Efficiency

13

2.2.2

Signal Constellation

14

2.2.3

Error Vector Magnitude (EVM)

15

2.3

Power Amplifier Properties

17

2.3.1

Output Power

17

2.3.2

Power Gain

18

Factor

18

2.3.4

Efficiency

19

2.3.5

Linearity

19

2.3.5.1

Adjacent Channel Power Ratio

20

2.4

Matching Network

22

2.4.1

Load line theory

23

2.4.2

Load-pull

24

2.4.3

Passive Impedance Transformation

25

2.4.4

Quality factor

25

2.4.5

L-Match Network

26

2.4.5.1

High to Low Transformation

27

2.4.5.2

Inductor Loss and Efficiency

28

2.5 HV-MOS Devices

30

2.5.1

Extended Drain MOS Devices

30

Chapter 3 Power Amplifier Classification

32

3.1

Linear Power Amplifiers

32

3.1.1

Class-A Power Amplifier

33

3.1.2

Class-B Power Amplifier

34

3.1.3

Class-C Power Amplifier

36

3.1.4

Class-AB Power Amplifier

37

3.2

Switching Power Amplifiers

38

3.2.1

Class-D Power Amplifier

38

3.2.2

Class-E Power Amplifier

40

3.2.3

Class-F Power Amplifier

42

Chapter 4 Test Bench and Simulation Results

44

4.1

Introduction

44

4.2

Tools and Programs

45

4.3

Structure of Class-AB Power Amplifier

45

4.3.1

Cascode Power Amplifier

45

4.3.2

EDMOS Power Amplifier

47

4.4

Test Bench

48

4.5

Devices Parameters

50

4.6

Simulation and results

50

4.6.1

Simulation Results of Test Bench No.1

50

4.6.2

Simulation Results of Test Bench No.2

51

4.7

Discussion / Interpretation

51

4.7.1

Power Density (Pout / M)

51

4.7.2

Error Vector Magnitude (EVM) and Ppeak

52

4.7.3

Pout – Pin

52

4.7.6

Transformation Ratio ((Zsource / Zin) and (ZL / Zout))

53

Chapter 5 Conclusion and Future Work

54

5.1

Summary and Concentration

54

5.2

Future Works

55

List of Figures

Figure 1.1: (a) NMOS symbol, (b) structure of NMOS device . . . . . . . 2

Figure 1.2: (a) PMOS symbol, (b) structure of PMOS device . . . . 3

Figure 1.3: PMOS device in an n-well . . . 3

Figure 1.4: (a) A MOSFET driven by gate voltage, (b) formation of depletion region, (c) onset of

inversion, (d) formation of inversion layer . . . .. . . 4

Figure 1.5: Formation of inversion layer in a PFET. . . . 5

Figure 1.6: Channel charge with equal source and drain voltages. . . . 6

Figure 1.7: Channel charge with unequal source and drain voltages. . . . 6

Figure 1.8: Linear operation region in deep triode region . . . 8

Figure 1.9: MOSFET as a controlled resistor. . . . . . 8

Figure 1.10: Saturation of drain current. . . . . . 9

Figure 2.1: Direct-conversion transmitter. . . . . 11

Figure 2.2: Amplitude shift keying. . . .. . . 12

Figure 2.3: Phase-shift keying. . . . . . 12

Figure 2.4: Frequancy shift keying. . . .. . . 13

Figure 2.5: Signal constellation for: (a) ideal PSK signal, (b) Noisy received PSK signal. . . .. . . 14

Figure 2.6: Constellation of 16 QAM. . . 14

Figure 2.7: Constellation of 16 QAM (noisy received signal). . . 15

Figure 2.8: Illustration of EVM. . . 16

Figure 2.9: (a) Power amplifier connected to an antenna, (b) Antenna modeled by pure

resistance. . . . . . 17

Figure 2.10: Illustration of P

1dB

compression point. . . . . . . . . 20

Figure 2.11: An example of ACPR measurement . . . 21

Figure 2.12: Load line imposed on IV-curve. . . 23

Figure 2.13: (a) Load-pull test, (b) contours used in load-pull test, (c) input and output

matching networks . . . .. . . 24

transformation. . . 26

Figure 2.16: L-match impedance transformation network. . . .. . . 27

Figure 2.17: L-match impedance transformation network with series inductor loss. . . .. . . . 28

Figure 2.18: Relationship between the power enhancement and the efficiency of an L-match

network. . . . . . . . 29

Figure 2.19: A structures of (a) N-EDMOS, (b) P-EDMOS. . . . . . 31

Figure 3.1: Common source linear power amplifier . . . .. . . 32

Figure 3.2: Drain voltage and current for ideal class-A amplifier. . . .. . . 33

Figure 3.3: Drain voltage and current for ideal class-B amplifier. . . .. . . 35

Figure 3.4: Drain voltage and current for ideal class-C amplifier. . . .. . . 36

Figure 3.5: Class-D amplifier. . . .. . . 38

Figure 3.6: T2 drain voltage and current for ideal class-D amplifier. . . .. . . 38

Figure 3.7: M1 drain voltage and current for ideal class-D amplifier. . . 39

Figure 3.8: Inverter-based class-D amplifier. . . . . . . . . 39

Figure 3.9: Class-E amplifier. . . . . . . . . 40

Figure 3.10: Waveform for class-E amplifier. . . . . . 41

Figure 3.11: Class-F amplifier. . . 42

Figure 3.12: Drain voltage and current for ideal class-F amplifier. . . 43

Figure 4.1: Structure of cascode power amplifier. . . . . . 44

Figure 4.2: Power amplifier, core and matching networks. . . 45

Figure 4.3: Schematic of class AB, cascode power amplifier . . . 46

Figure 4.4: Cross-section of EDMOS device. . . . . . .. . . . . . 47

Figure 4.5: Schematic of class AB, EDMOS power amplifier. . . 47

Figure 4.6: Test bench no.1. . . 49

Figure 4.7: Test bench no.2. . . 49

List of Tables

Table 2.1 Bandwidth efficiency for different modulation schemes. . . 14

Table 2.2 Constellation error and EVM equivalent for IEEE 802.11a . . . 16

Table 4.1 Devices size and parameters. . . 50

Table 4.2 performances and results. . . … . . . 50

Table 4.3

Peak output power

measurements (estimation). . . 52

Chapter 1

Basic MOS Device Physics

1.1

Brief History

The theory of a metal-oxide-silicon field-effect transistors(MOSFETs) was known 20 years before the invention of the bipolar transistors. In 1930, the idea of creating a FET-like transistor was patented by J.E. Lilienfeld, but he could never construct a working device [1].

Due to fabrication limitations and lack of appropriate semiconductors, the development was very slow. In the early 1960s, MOS technologies became practical with several generations which contained only n-type transistors. It was in 1963 when the CMOS circuits was invented by Frank Wanlass [2]. Thus, circuits with both n-type and p-type transistors were introduced. These circuits are known as Complementary MOS, or CMOS circuits.

The availability of complementary enhancement NMOS and PMOS transistors had many benefits such as low power dissipation and low fabrication cost, which made the CMOS IC an attractive technology for the realization of digital circuits. Furthermore, the ease to scale down the dimensions of the MOS device lead to the integration of more and more dense and complex digital circuits. Device scaling also improved the speed of MOSFETs. That was the principal force of making CMOS technology the dominating technology also in the analog and RF market [3].

1.2

MOSFET Structure

There are many symbol can be used to represent NMOS transistor, one of these symbols is shown in Figure 1.1 (a). The MOSFET is a four terminal device: gate (G), source (S), drain (D), and substrate (B) which is also called bulk.

Figure 1.1 (b) shows the structure of NMOS device. The NMOS device consists of two heavily-doped n+

regions forming the source and drain terminals. These two regions are built on a p-type substrate. The gate is made of heavily doped poly-silicon isolated from the substrate by a layer of silicon oxide (SiO2). Note that

the drain and source are interchangeable because the MOS device is symmetric with respect to drain and source. The substrate is usually connected to the most negative supply in the system to insure a reverse bias for the drain-body and source-body junctions [3].

Chapter 1

Basic MOS Device Physics

________________________________________________________________________________________________________________________________________________________________

(a)

(b)

Figure 1.1: (a) NMOS symbol, (b) structure of NMOS device [3].

In CMOS technology, both NMOS and PMOS are available. The PMOS transistor consists of two heavily doped p+ _{fabricated on a n-type substrate. The gate and the oxide layer are the same as those for the NMOS}

transistor. To make sure the inverse bias of the drain-body and source-body junctions, the substrate is connected to the most positive supply in the system. Figure 1.2 (a) shows the symbol of the PMOS transistor, and Figure 1.2 (b) shows the structure of this device.

(a)

(b)

Figure 1.2: (a) PMOS symbol, (b) structure of PMOS device [3].

In practice, both NMOS and PMOS devices are fabricated on a single substrate. Thus, one device type has to be fabricated on a local substrate (also called well). Figure 1.3 shows a PMOS device placed in an n-well.

Chapter 1

Basic MOS Device Physics

________________________________________________________________________________________________________________________________________________________________

1.3

MOS I/V Characteristics

1.3.1 Threshold Voltage

Consider an NMOS transistor shown in Figure 1.4.

Figure 1.4: (a) A MOSFET driven by gate voltage, (b) formation of depletion region, (c) onset of inversion, (d) formation of inversion layer [3].

When the VG is 0, the drain and source are connected by back-to-back PN junctions. Thus, the transistor is

off and there is no current flowing between the source and drain. As the gate and substrate form a capacitor, if a positive voltage is applied at the gate, positive and negative charges will accumulate at the gate and substrate, respectively. Thus, the holes in the substrate are repelled and a depletion region is formed below the gate. The width of this depletion region can be defined as

W

_d

=

√

2 ε

si

ϕ

q N

_A

(1.1)

where φ is the potential across the depletion region, NA is the substrate doping and Ɛsi is the dielectric

constant of silicon.

The potential across the depletion region is directly proportional to VG. When the potential reaches a

critical value, a channel between the drain and the source is formed under the gate and the transistor

is turned on. This phenomenon is also called strong inversion. The value of VG at which the strong

inversion occurs is called threshold voltage V

TH

.

implemented for threshold adjustment and the source-bulk voltage VSB. It can be defined as

V

_TH

=

V

_TH0

+ γ(

_√

∣2 ϕ

_F

+

V

_SB

∣−

_√

∣2 ϕ

_F

∣)

(1.2)

where VTH0 is threshold voltage at VSB = 0, is the body-effect coefficient and φɤ F is the Fermi potential.

For PMOS devices, same arguments can be applied for the turn on phenomenon but with all of the polarities are reversed. Figure 1.5 shows the formation of inversion layer in PMOS. When the VG becomes sufficiently

negative, the strong inversion occurs and a channel between the drain and the source is formed.

Chapter 1

Basic MOS Device Physics

________________________________________________________________________________________________________________________________________________________________

1.3.2 Operation Regions

To understand the operation regions, the relationship between the drain current and terminals voltages are discussed.

Figure 1.6: Channel charge with equal source and drain voltages [3].

Figure 1.6 shows an NFET whose drain and source are connected to ground and gate is connected to VG. The

charge of the gate oxide capacitance is proportional to the effective voltage (VGS-VTH). For (VGS-VTH ≥ 0), the

induced channel charge per unit area can be written as

̄

Q

d

=

C

ox

(

V

GS

−

V

TH

)

(1.3)

and the charge per unit length is

Q

_d

=

W C

_ox

(

V

_GS

−

V

_TH

)

(1.4)

where W is the gate width.

Now suppose the drain voltage is positive, as shown in Figure 1.7.

Figure 1.7: Channel charge with unequal source and drain voltages [3].

The channel potential increases from zero at the source to VD at the drain. Thus, the local voltage difference

the point x is V(x), then the charge density at that point can be written as

Q

_d

(

x) = W C

_ox

[V

_GS

−

V ( x)−V

_th

] (1.5)

The ID can be defined as

I

_D

= −

Q

_d

(

x)⋅v (1.6)

Where v is the velocity of the electron in the channel, which is defined as

v = μ E = −μ

d V (x)

dx

(1.8)

Thus, the drain current can be written as

I

_D

= μ

_n

W C

_ox

[V

_GS

−

V (x)−V

_TH

]

d V (x)

dx

(1.9)

I

_D

dx = μ

_n

W C

_ox

[V

_GS

−

V (x)−V

_TH

] d V ( x) (1.10)

By setting the boundary of integration as

At x =0 => V ( x)=0 and at x= L => V ( x)=V

DS , the

above equation can be written as

∫

x=0 x=L

I

_D

dx =

∫

V (x)=0 V (x)=VDS

μ

_n

W C

_ox

[V

_GS

−

V ( x)−V

_TH

] d V (x) (1.11)

Finally, by assuming that µ and VTH are independent of x, VGS, and VDS, the drain current is defined as

I

_D

= μ

_n

C

_ox

W

L

[(

V

GS

−

V

TH

)

V

DS

−

1

2

V

DS 2

]

(1.12)

Chapter 1

Basic MOS Device Physics

________________________________________________________________________________________________________________________________________________________________

1.3.2.1 The Deep Triode Region

For VDS 2(V˂˂ GS-VTH), the drain current can be written as

I

_D

= μ

_n

C

_ox

W

L

[(

V

GS

−

V

TH

)

V

DS

]

(1.13)

Thus, if the VGS is constant, the drain current is a linear function of VDS. This is also shown in Figure 1.8. For

small VDS, each parabola can be approximated by a straight line.

Figure 1.8: Linear operation region in deep triode region [3].

At this region, the transistor can be modeled as a resistor (Ron), this is also shown in Figure 1.9. The value of

this resistor is controlled by VDS, and can be written as

R

_on

=

1

μ

_n

C

_ox

W

L

(

V

GS

−

V

TH

)

(1.14)

1.3.2.2 The Saturation Region

Recall from equation (1.5), that the charge density at point x is proportional to (VGS-VTH) - V(x). Thus, the

channel exists as long as (VGS-VTH ≥ V(x)).

As it has been mentioned previously, the potential voltage V(x) at the drain voltage reaches VDS.

At the drain side, the channel disappears if (VGS-VTH ≤ VDS). This is known as pinch-off phenomenon. When

this phenomenon occurs, the drain current becomes relatively constant and the NMOS transistor is said to be in saturation region. This is illustrated in Figure 1.10.

Figure 1.10: Saturation of drain current [3].

The drain current of an NMOS in saturation region is defined as

I

_D

=

1

2

μ

n

C

ox

W

L

(

V

GS

−

V

TH

)

2

_{. (1.15)}

The equation above approves that the drain current of an NMOS in saturation region does not depend on the VDS. Note that this transistor can be modeled as a current source whose current magnitude is in response to

Chapter 1

Basic MOS Device Physics

________________________________________________________________________________________________________________________________________________________________

1.4

Reliability issues in Power Amplifiers Design

In PA, amplification of electrical signal requires high voltage and current. So, both the voltage and current of the transistor are pushed to their limits. In CMOS technology, the limits of the voltage and current are determined by the following mechanisms [4].

1.4.1 Drain-Bulk Breakdown

The drain-bulk diode experiences a reverse bias. Usually, in standard CMOS process, the bulk is connected to a fix electrical potential. So the diode reverse bias is directly proportional to the drain voltage. This diode has a reverse breakdown voltage which in today's processes is relatively low. To avoid diode breakdown, the drain-bulk voltage is not allowed to reach this breakdown voltage.

1.4.2 Hot Carrier Effect

As complementary metal–oxide–semiconductor (CMOS) technologies are scaled down into the nanometer range, transistors may experience high lateral electric field if the voltage between the drain and source is large. High electrical field causes continual increase in the velocity and hence the kinetic energy of the carrier. Such a carrier is called Hot Carrier [ 3].

Hot carriers can leave the silicon and tunnel through the gate oxide but some of them get trapped in the oxide, thus changing the threshold voltage and the I-V characteristics of the MOS device [5]. As a consequence, hot carrier phenomenon can lead to a long-term degradation and the performance of the circuit might be out of the specification after long time [7].

1.4.3 Time Dependent Dielectric Breakdown TDDB

High voltage between the gate and the channel causes large stress on the gate oxide. Such stress can cause breakdown in gate oxide if it is applied for a long time. This type of gate oxide breakdown is called Time

Dependent Dielectric Breakdown [1]. This phenomenon causes a permanent damage in the device. But

before it occurs, there is no degradation in the device performances.

1.4.4 Punch-through

At high drain-source voltage, the drain space charge region expands over the channel. For high enough value of drain-source voltage, the drain can come in contact with the source depletion region. This effect, which is called punch-through, causes a large increase in the drain current which can lead to a permanent damage in the device [7].

Chapter 2

Important Aspects in PA Design

2.1

Introduction

In designing a PA for a wireless communication, it is very important to have good knowledge of the communication system itself and the signal that needs to be amplified. Therefore, this section will review some aspects that are important for PA [4].

Initially, the PA is considered in the context of a radio transmitter. There are many transmitter architectures, but the considered one in this section is “direct-conversion” transmitter. This topology, as shown in Figure 2.1, consists of Mixers, two local oscillator signals (phase-shifted by 90°), PA, and matching network. The mixer converts a base-band spectrum, which is a digital modulated signal, to the RF spectrum. The PA is the last active component in the transmitter. The sole purpose of PA is amplifying modulated signal and providing maximum power delivery to the antenna through the matching network. It is also known that the PA is the most power hungry component in the transmitter.

Thus, the most important properties of a PA designed for wireless system are output power, efficiency, gain, and linearity.

Chapter 2

Important Aspects in PA Design

________________________________________________________________________________________________________________________________________________________________

2.2

Digital Modulation

Modern communication systems utilize different digital modulation schemes such as Amplitude Shift Keying

ASK, Phase shift Keying PSK, and Frequency Shift Keying FSK. In all types of digital modulation, the

carrier signal is modulated by a digital base-band signal.

Figure 2.2: Amplitude shift keying.

In Binary ASK, the modulated signal toggles between zero and full amplitude. Such a modulation is called non-constant envelope modulation. In Binary PSK the phase of the modulated signal toggles between 00 _and

1800_{. In Binary FSK, the frequency of the modulated signal toggles between two different frequencies.}

Figure 2.2, 2.3, and 2.4 illustrate examples of these waveforms for binary base-band signal.

Figure 2.4: Frequency shift keying.

2.2.1 Bandwidth Efficiency

If B is the bandwidth occupied by a digital modulated signal, one can define spectral efficiency as

η =

R

b

B

bit / S / Hz (2.1)

where Rb is the bit rate of the transmission and is defined as

R

_b

=

Number of bit per symbol

symbol duration

=

log

₂

M

T

_S

(2.2)

Thus, the bandwidth efficiency can be increased by increasing the number of bits per each transmitted symbol. Other modulation schemes, such as Quadrature PSK (QPSK) and Quadrature Amplitude Modulation

QAM, have been introduced to save the bandwidth of the modulated signal. Bandwidth efficiency for

Chapter 2

Important Aspects in PA Design

________________________________________________________________________________________________________________________________________________________________

Modulation format Bandwidth efficiency (C/B)

16 PSK 4 16QAM 4 8PSK 3 4PSK 2 4QAM 2 BFSK 1 BPSK 1

Table 2.1 Bandwidth efficiency for different modulation schemes [23].

2.2.2 Signal Constellation

Signal constellation is a way to represent digital modulated signals and visualize the effect of nonidealities on them.

Figure 2.5 (a) shows a signal constellation for an ideal PSK signal and Figure 1.5 (b) shows a nosy received PSK signal. The receiver has to distinguish and decide whether the received bit is a ONE or ZERO. If the received signal is noisier, the two points come closer to each other making the detection more difficult and prone to error [10].

Figure 2.5: Signal constellation for: (a) ideal PSK signal, (b) noisy received PSK signal.

Figure 2.6 shows a constellation of 16 QAM. The points in this constellation are closer to one another than those in the PSK constellation, making the detection more sensitive to noise.

16 QAM modulation scheme, exhibits large envelope variations. Such a modulation scheme requires a highly – linear PA.

Figure 2.7: Constellation of 16 QAM (noisy received signal).

2.2.3 Error Vector Magnitude (EVM)

Error Vector Magnitude (EVM) is a powerful tool for analysing the effect of various nonidealities, such as Non-linearity in the PA, in the transceiver, and in the channel. EVM represents deviation of the constellation points from their ideal position. EVM can be obtained by constructing a constellation based on a large number of detected samples, as shown in Figure 2.8, a vector is drawn between each measured point and its ideal constellation position [10].

EVM is defined as

EVM =

1

P

_avg

1

N

∑

_j=1 N

e

2_j

_(2.3)

The maximum acceptable EVM is determined by the standard being employed. Table 2.2 shows the constellation error and EVM equivalent for IEEE 802.11a [11].

Chapter 2

Important Aspects in PA Design

________________________________________________________________________________________________________________________________________________________________

Figure 2.8: Illustration of EVM.

Data Rate (Mbps) Relative Constellation Error(dB) EVM(%RMS)

6 -5 56.2 9 -8 39.8 12 -10 31.6 18 -13 22.3 24 -16 15.8 36 -19 11.2 48 -22 7.9 54 -25 5.6

2.3

Power Amplifier Properties

The most important properties of a PA designed for wireless system are output power, efficiency, gain, and linearity. These properties are explained in this section.

2.3.1 Output Power

Consider the circuit of Figure 2.9 (a), which shows a PA connected to an antenna. Usually, the antenna impedance can be considered as pure resistance in the frequencies of interest . So the antenna can be modeled by a resistor RL, usually 50 Ohm, as shown in Figure 2.9 (b).

The output power is defined as the active power delivered by the PA into the antenna.

(a) (b)

Figure 2.9: (a) Power amplifier connected to an antenna, (b) Antenna modeled by pure resistance.

The instantaneous output power is defined as

P

₀

(t)=v

_0ut

(

t ).i

_out

(

t) (2.4)

and the total power is defined as

P

_o,tot

=

lim

T → ∞

(

1

T

)

₋

∫

_T 2 T 2

P

₀

(t ) dt (2.5)

Assuming that the output signal is a sine wave with frequency f C, the total power is defined as

P

_o,tot

=

1

T

_{c −}

∫

_T c 2 Tc 2

P

₀

(

t )dt (2.6)

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Important Aspects in PA Design

________________________________________________________________________________________________________________________________________________________________

Finally, assuming a pure resistive load, the output power is defined as

P

_o,tot

=

V

0,rms 2

R

_L

(2.7)

and

P

_o,tot

=

V

0 2

2 R

_L

(2.8)

where V0 is the supply voltage.

2.3.2 Power Gain

The power gain, usually expressed in dB, is defined as the ratio between the output power to the input power

G

_P,dB

=10 log

₁₀

(

P

0

P

_in

)

. (2.9)

2.3.3 Peak Output Power, Peak to Average Power Ratio and Crest Factor

As it has been mentioned above, different communication systems utilize different modulation schemes. For a constant envelope modulation schemes (with constant output power), one could define a fixed envelope

output power (P0(A)) as the average output power dissipated in the load as

P

₀

(

A)=

A

2

2 R

_L

(2.10)

where A, the amplitude of output signal, is constant.

On the other hand, for a non-constant envelope modulation schemes, the PA will operate at a relatively low output power but also deliver large power peaks for small fraction of time. Assuming that the PA operates at the maximum output power all the time, one can define a Peak Envelope output Power (PEP) as

PEP = Max { P

₀

(

A(t))} =

(max {A(t)})

2

2RL

=

A

2_max

2RL

(2.11)

The Peak Envelope output Power can be much higher than the average output power (P0). In this regard, one

can define a Peak to Average Power Ratio (PAPR) as

PAPR =

PEP

where P0 is define as

P

_o

=

V

0,rms

2

2R

_L

(2.13)

This can also be calculated based on voltages, which gives what is known as Crest Factor (CF)

CF =

V

0, max

V

_{0, rms}

(2.14)

2.3.4 Efficiency

As it has been mentioned above, the PA is the most hungry component of a transmitter so an important property is the efficiency. One of efficiency measurement is the drain efficiency ƞd which is defined as the

ratio between the average output power (P0) and the DC power consumption of the PA (PDC,PA)

η

_d

=

P

0

P

_{DC ,PA}

(2.15)

In some cases, when the PA has a relatively low power gain, the input power Pin becomes a considerable

value in efficiency measurement. This measurement is known as Power Added Efficiency (PAE). It is also useful when the PA is a multi-stage amplifier. The PAE is defined as

PAE=

P

0

−Pin

P

_{DC ,tot}

(2.16)

where the (PDC,tot) is the total DC power consumption by the PA and all other amplifier stages.

2.3.5 Linearity

As it has been mentioned previously, several communication systems utilize modulation schemes with non-constant envelope where information is contained in the amplitude of the modulated signal. Such a modulated signal needs to be amplified by a linear amplifier, which means that the gain of the PA is equal over a range of different input amplitude. Otherwise, the output waveform will have different shape from the input waveform and information will be corrupted.

All PAs experience a reduction of gain at high input amplitude. So, the output power will be lower than the expected, as illustrated in Figure 2.10. This effect can be quantified by the

P

1dB compression point. The

P

1dB compression point is defined as the point where the output power is 1 dB lower than the anticipated from the gain in the linear region [3].

Chapter 2

Important Aspects in PA Design

________________________________________________________________________________________________________________________________________________________________

Figure 2.10: Illustration of

P

1dB compression point.

There are two important metrics to express the nonlinearity of a PA, the Error Vector Magnitude (EVM), which already has been discussed, and the Adjacent Channel Power Ratio (ACPR).

2.3.5.1 Adjacent Channel Power Ratio

The nonlinearity of a PA causes a power leakage in the adjacent channels. If the leakage power reaches a predefined level, the adjacent channels may be disturbed. Therefore, the transmission should occur in a limited bandwidth. The traditional way for testing adjacent channel is called two tone test, where two in-channel tones is used to measure the out-of-in-channel distortion. However, this testing method is not good enough for the real applications of wide-bandwidth wireless systems. A better measurement is what called ACPR measurement which is defined as the ratio of the integrated signal power in an adjacent channel to the integrated signal power in the main channel [25].

It is also important to mention that reducing the power leakage leads to decrease the power consumption thus increasing the battery life for the mobile device. Figure 2.11 shows an example for ACPR measurements.

Chapter 2

Important Aspects in PA Design

________________________________________________________________________________________________________________________________________________________________

2.4

Matching Network

In RF and microwave, components such as antenna and antenna-filters have single ended input and output impedances of 50 ohm. Consider the circuit shown in Figure 2.9 (a), the PA is directly connected to the antenna. The antenna can be modeled as resistance (RL). This is shown in Figure 2.9 (b) and the output power delivered to

RL can be defined as

P

_out

=

V

DD 2

2 R

_L

(2.17)

As an example, if the supply voltage is 1.2 V, then the output power will be only 14.4 mW So, to achieve a sufficient out power, matching network is needed to transform RL to some lower resistance. Generally, in PA

design, the maximum power transfer theory is useless for two reasons. The first reason is that it is fuzzy and difficult to define impedance in large-signal, nonlinear system. The other reason is, in maximum power transfer theory, the efficiency would be only 50 % because equal amount of power will be dissipated on the source and load. For these reasons, the PA is designed to deliver a specified amount power with highest possible efficiency and with an acceptable gain [12]. Instead of matching to maximum power transfer, the input and output impedance of the PA are matched to achieve maximum gain and maximum output power respectively.

2.4.1 Load Line Theory

In PA design, the load line theory can help the designer to know if the transistor is working with the full power capability or not. This is done by studying the current and voltage waveforms. The load line theory can also help the designer to predict the optimum output resistance, ROL, that the transistor should see for

delivering the maximum linear output power.

Figure 2.12: Load line imposed on IV-curve.

Figure 2.12 shows three load lines for three different loads seen by the transistor, imposed on I-V curves. All lines are centred on the bias point of the transistor. The slope of each load line is equal to the susceptance of the corresponding load [29]. The minimum and maximum drain current is zero and ID,max, respectively. The

minimum and maximum drain to source voltage is Vknee and 2VDD-Vknee, respectively. The optimum load can

be defined as [30]

R

_LO

=

V

DS ,max

I

_{D , max}

(2.18)

For RL = RLO, the current swings fully between zero and ID,max and the voltage swings fully between Vknee and

2VDD-Vknee. Thus, the transistor is working with full power capability. For RL < RLO, the voltage swings

between V1 and and V2,thus the voltage is limiting the output power. For RL > RLO, the current swings

between I1 and I2, thus the current is limiting the output power.

V

2

I

1

I

2

V

1

Chapter 2

Important Aspects in PA Design

________________________________________________________________________________________________________________________________________________________________

2.4.2 Load-pull

In deep-submicron CMOS technologies, the voltage knee as high as 50 % of the supply voltage [30]. Thus, the load line concept may not be a good approach to determine the optimum load resistor for the MOS device as the transistor would not work with full power capability. A better approach to determine the optimum resistor is to use load-pull technique [3].

Consider the circuit shown in Figure 13 (a), where a passive matching network is used to present a complex load impedance, Z1, to the transistor M1. The real and the imaginary part of Z1 is varied in a way such that

the power delivered to the RL is constant and equal to P1. This yields the contour shown in Figure 13 (b).

Next step is to seek those values of Z1 that gives higher power, P2, yielding another contour. A high P2

corresponds to narrower rang of Re{Z1}and Im{Z1}, hence tighter contour. These “load-pull” measurements

can be iterated to increase the power level, until reaching an optimum impedance, Zopt, for the maximum

power level.

Figure 2.13: (a) Load-pull test, (b) contours used in load-pull test, (c) input and output matching networks.

Due to gate-drain capacitance of M1, varying Z1 may have some effect on the input impedance of the

transistor, Zin. Thus, the power delivered to the transistor varies with Z1, which could yield a variable power

gain. This effect can be eliminated by tuning the input matching network, shown in Figure 2.13 (c), to obtain the required power gain.

2.4.3 Passive Impedance Transformation

For operating frequency between 1 and 10 GHz, passive matching networks (consist of lumped inductors and capacitors) are used to transform impedance from high to low and vice versa. The drawback with passive matching network is that they suffer from losses especially if they are built on silicon chips because of the low substrate resistivity. Therefore, passive matching networks are not easy to integrate [13].

2.4.4 Quality Factor Q

To understand the limitation of passive matching network design, the quality factor of passive components are discussed here. Many different definitions can be found in literature for quality factor (Q). Generally, a Q for a device indicates how close to ideal this device stores energy. For example, a capacitor said to be ideal if it dissipates no energy. Such a capacitor exhibits an infinite Q. But in reality, passive elements are not ideal and they always dissipate energy. Loss due energy dissipation can be modeled by adding a resistance in series or in parallel.

Figure 2.14: Inductor with loss. (a) Series model and (b) parallel model [4].

Figure 2.14 (a) shows a circuit of an inductor with series resistance. The Q of this circuit can be defined as

Q

_S

=

X

S

R

_S

=

w L

_S

Chapter 2

Important Aspects in PA Design

________________________________________________________________________________________________________________________________________________________________

This series circuit can be converted to parallel network as shown in Figure 2.14 (b). The Q of this circuit can be defined as

Q

_p

=

R

p

X

_p

=

R

_p

w L

_p

(2.19)

Similar concepts can be applied to capacitors. The Q can be defined as

Q

_S

=

1

R

_S

w C

_S

(2.20)

and

Q

_p

=

R

p

X

_p

=

R

p

w C

p

(2.21)

2.4.5 L-Match Network

There are many types of matching networks topologies like L-match, T-match, pi-match, and Tapped Capacitor Resonator match.

An excellent candidate topology for CMOS integration is L-match topology, which is discussed in this section. An elaborate discussion on other topologies can be found in [12], [31]-[32] and will not be reported here.

A common situation in RF transmitter design is that an impedance must be transformed from high to low value (like the load resistance of a PA) using matching network circuit shown in Figure 2.15 (a) or from low to high (like the source impedance of a PA) using the circuit shown in Figure 2.15 (b).

2.4.5.1 High to Low Transformation

High to low transformation can be accomplished by the circuit shown in Figure 2.16 (a), where the load impedance is transformed from RL to a lower value Rin. The parallel circuit of CP and RL can be converted to a

series equivalent circuit of CS and R1 as shown in Figure 2.16 (b).

Figure 2.16: L-match impedance transformation network.

The value of CS and R1 can be calculated as

R

₁

=

R

L

1+Q

_C2

(2.22)

C

_S

=

C

_P

⋅(1+ 1

Q

_C2

)

(2.23)

where QC is

Q

_C

=

R

L

1/(w C

_P

)

(2.24)

The L1is designed to be in resonance with CS at the operating frequency ɷ0, which can be defined as

ω

₀

=

1

1/

_√

L

₁

C

_S

(2.25)

Thus, at resonance frequency ɷ0 , L1and CS provide a short circuit and the input impedance of the matching

network Rin is equal to R1. This is shown in Figure 2.16 (c).

The impedance transformation ratio (r) is defined as

r =

R

L

Chapter 2

Important Aspects in PA Design

________________________________________________________________________________________________________________________________________________________________

An important parameter in designing a matching network for PA is the power enhancement ratio, E, which is the ratio between the output power with the matching network (Pout) and the output power without the

matching network Pout,1 [4].

E=

P

out

P

_{out ,1}

(2.27)

If the above circuit is assumed to be loss-less, the power enhancement ratio is the same as the impedance transformation ratio r.

2.4.5.2 Inductor Loss and Efficiency

The overall loss of an L-match network is dominated by the inductor loss which can be modeled as a series resistance (Rlm) as shown in Figure 2.17 (a). At the resonance frequency, the equivalent circuit of the

matching network and RL is shown in Figure 2.17 (b).

Figure 2.17: L-match impedance transformation network with series inductor loss.

Thus, the input impedance of the matching network can be written as

R

_in

=

R

₁

+

R

_Lm

(2.28)

And the impedance transformation ratio is

r=

R

L

R

1

+

R

Lm

(2.29)

P

_out

=V

_DD2

R

1

2( R

₁

+R

_Lm

)

2

(2.30)

and the total input power to the matching network is

P

_in,L

=

V

DD

2

2( R

₁

+R

_Lm

)

(2.31)

Thus, the efficiency of the matching network can be calculated as

η

_L

=

P

out

P

_in,L

=

R

₁

R

₁

+R

_Lm

(2.32)

So, the efficiency of the matching network is inversely proportional to the parasitic resistance of the inductor. Figure 2.18 shows the relationship between the power enhancement and the efficiency of an L-match network for different values of inductor quality factor. At higher values of E, the efficiency will decrease.

Figure 2.18: Relationship between the power enhancement and the efficiency of an L-match network [4].

Recall the example which has been discussed above. For supply voltage of 1.2 V, the output power without using matching network was 14.4 mw. Now, assume that a matching network is used to convert the load impedance. Also assume the the quality factor of the used inductor is 15. From Figure 1.18, if the minimum acceptable efficiency of the matching network is 80 %, then the allowable power enhancement ratio is 10.

Chapter 2

Important Aspects in PA Design

________________________________________________________________________________________________________________________________________________________________

Thus the delivered power to the load is 144 mW. To achieve higher output power for a given power enhancement ratio, the supply voltage of the PA has to be increased and a reliable operation has to be maintain [4].

2.5

HV-MOS Devices

The rapid technology evolution of CMOS has largely improved the radio frequency performance of MOS devices, such as large RF gain, higher cut-off frequency (FT), and maximum oscillation frequency (Fmax).

This has made CMOS device technology the prime choice for RF system-on-chip (SoC) applications, such as WCDMA, W-LAN, and ultra-wide band (UWB) wireless communication. Nowadays, CMOS technologies represent an alternative to III-V technologies in RF PAs design. However, low drain break down voltage and other reliability issues of nanometer CMOS transistors reduce the maximum output power and efficiency for RF PAs. When the SoC design includes the PA, it is therefore challenging using a baseline CMOS logic process [14]-[16].

To overcome the reliability issues in PA design, one can use circuit solution that can handle higher voltage such as cascode configuration, where standard thick-oxide transistors are stacked in a cascode configuration to eliminate the effect of oxide breakdown voltage and to make use of a larger supply voltage. The other solution is to use high-voltage MOS, H-V MOS devices. Due to their ability to integrate with the low modules in MOS, HV-MOS devices have became an accessible solution for power integrated circuits. Today, HV-MOS devices are used in many applications, like switch-mode power supplies, motor drivers, and PAs [17]-[19].

Generally, HV-MOS devices are classified into two types, Extended Drain MOSFET devices (EDMOS) and Lateral double-Diffused MOSFET (LDMOS) devices. The LDMOS devices require extra process and that increases the process complexity and cost. Thus, LDMOS devices will not be reported here and eager readers can refer to [21], [33]-[36].

2.5.1 Extended Drain MOS Devices

The nominal voltages of modern digital VLSI circuits are at 1.8 V level and below. However, such circuits are often needs to be integrated with other circuits operating at 3.3/5.0 V or even higher. Example circuits are power management switches that regulate power from battery or system supplies, output analog drive functions for speakers, and RF PAs [19].

In analog system, reliability issues represent great challenge for the system designers. To handle 3.3 V, thick -oxide transistors are added into all processes. One solution to handle greater supply voltage is to use devices like Extended Drain MOS (EDMOS) transistors [26], [27]. They can cope with higher drain voltages without significant loss of performance and without added process complexity. Figure 2.19 shows the structures of N-EDMOS and P-EDMOS.

(a)

(b)

Figure 2.19: Structures of (a) N-EDMOS, (b) P-EDMOS [17].

This structure requires one extra mask and one implantation step to build the drain extension [17]. By extending the drain region, the electric field under the gate at the drain end of the transistor is reduced, thus, the breakdown voltage is increased.

Chapter 3

Power Amplifier Classification

________________________________________________________________________________________________________________________________________________________________

Chapter 3

Power Amplifier Classification

As the previous chapter covered some important concepts in PA design, this chapter describes the PA classification and the trade-off between linearity and efficiency.

Generally, PAs can be divided into two groups, linear amplifiers and switching amplifiers.

3.1

Linear Power Amplifiers

In linear amplifiers, the active device is used as current source. They are classified to class-A, B, C, and AB PA. All these classes may be understood by studying one single model shown in Figure 3.1. The only difference between these classes is the way of gate biasing of the transistor.

3.1.1 Class-A Power Amplifier

In class-A PA, the transistor is biased in a way so that it is always on and never turns off, which means that the conduction angle of the PA is 360°. To satisfy this condition, the transistor has to be kept in saturation region all the time.

Figure 3.2: Drain voltage and current for ideal class-A amplifier [12].

Figure 3.2 shows the drain voltage and the drain current waveforms. Since the input voltage is sinusoidal, the figure shows a linear relationship between the input voltage and the output current.

Even when there is no input signal, the transistor is always on and dissipates energy because of the bias current. So, class-A PA provides a linear signal but at the expense of efficiency.

The efficiency can be computed by, first, calculating the signal power delivered to RL as:

P

_rf

=

i

rf

2

_R

L

2

(3.1)

where (irf)2 is the amplitude of the the RF signal component of the drain current.

The second step is to calculate the DC power supplied to the amplifier as

P

_DC

=

I

_DC

V

_DD

(3.2)

To guarantee that the transistor never turns off, IDC should at least equal to irf, so

P

_DC

=

i

_rf

V

_DD

(3.3)

Finally, the drain efficiency is defined as

η =

P

rf

P

_DC

=

I

_rf2

₍

_R/2)

i

_rf

V

_DD

=

i

_rf

R

_L

2V

_DD

(3.4)

Chapter 3

Power Amplifier Classification

________________________________________________________________________________________________________________________________________________________________

Now, the maximum value of the product (irfRL = VDD), so the maximum efficiency can be defined as

η

_Max

=

V

DD

2V

_DD

=

50 % (3.5)

The above calculations show that maximum efficiency in class-A PA is 50 %. Different parameters, like variation in bias condition, non ideal drive amplitude and losses in the filter, cause the efficiency to drop below the 50 %. In practice, drain efficiencies of 30-35 % are not unusual.

An other important issue to be discussed is the stress on the transistor M1. In class A amplifiers, the transistor M1 experiences maximum drain-to-source voltage, VDS,max= 2VDD, while the peak drain current,

iD,max=2VDD/RL. The device has to be able to handle the stress resulted from these peaks of voltage and current

even though they do not occur simultaneously.

One common way to quantify this stress is to define what is called normalized power output capability PN

which is defined as

P

_N

=

actual output power

v

_{DS , max}

.i

_{D , max}

(3.6)

So, for class-A amplifiers, the normalized power output capability is

P

_N

=

V

DD 2

_{/(2 R}

L

)

(2V

_DD

)(

V

_DD

/

R

_L

)

=

1

8

(3.7)

3.1.2 Class-B Power Amplifier

The efficiency of a linear amplifier can be increased by decreasing power dissipation by forcing the waveform of either drain current or drain voltage to be non-sinusoidal, so that the product of drain current and drain voltage decreases. This can be done by lowering the input bias point, so the transistor is in non-conducting state for a part of time [28].

With this condition of conduction, one can expect large distortion at the output voltage. To get a fairly sinusoidal output signal, a high-Q tank is needed at the output of the PA [1].

In class-B PA, the transistor is bias in a way so that it is off half of every cycle, which means that the conduction angle of the PA is 180°.

Figure 3.3: Drain voltage and current for ideal class-B amplifier [12].

The drain current and drain voltage waveform are shown in Figure 2.3. To compute the efficiency, the fundamental component of the drain current should be calculated, which is defined as

i

_fund

=

2

T

∫

₀

T /2

i

_rf

(sin w

₀

t)(sin w

₀

t)dt =

i

rf

2

(3.8)

The output voltage is defined as

v

_out

=

i

rf

2

R

L

sin w

0

t (3.9)

Since the maximum possible value of vout is VDD, then the maximum value of irf is

i

_rf,max

=

2V

DD

2

R

L

(3.10)

The output power is calculated as

P

₀

=

v

0

2

2R

_L

(3.11)

where V0 is the amplitude of the signal across RL.

Given that the maximum value of v0 is VDD, the maximum output power is

P

_0,max

=

V

DD

2

2 R

_L

(3.12)