Design of Integrated Circuits with Low-Power Consumption

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Design of Integrated Circuits with Low-Power Consumption

Lecture By

Bengt Oelmann

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The First Example

• The mobile terminal

– Evolution of MIPS requirements in cellular

GSM GPRS 3G

Communication Application DSP MIPS

10000

1000

100

10

1

Power consumption is proportional to MIPS

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The Energy Gap

1 10 100 1000 10000 100000 1000000 10000000

Battery Capacity (i.e. Eveready’s Law) Algorithmic

Complexity 3G

Signal Processor Performance (~Moore’s Law)

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More Energy-Efficient Alternatives to Processors

Dedicated HW

Flexibility 1

10 100 1000

0.1

Reconfigurable processor Pleiades: 10-80 MIPS/mW

MIPS/mW

2V DSP: 3 MIPS/mW

ASIP / DSP

SA110

0.4 MIPS/mW

Embedded processors

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Reducing the Energy Gap

• Signal processing in digital mobile communication

– Implemented as a combination of Software, programmable DSPs, and dedicated hardware (ASIC) for the most demanding algorithms

– To meet the power requirements in 3G systems, no more than 10% of the algorithms can be implemented in software.

– Most of the algorithms must be implemented in dedicated hardware in ASICs

– Only ASICs is not really the solution:

• Very costly

• Inflexible: 20-30 standards should be covered, should be scalable with date-rates

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Reducing the Energy Gap

• Flexibility comes at an enormous cost (power)

• Specific hardware comes at an enormous cost (design effort)

• To achieve energy reduction and flexibility

– Research in efficient programmable processor architectures targeting low power consumption

– Research in efficient architectures for dedicated hardware that can be incorporated in programmable structures

– Careful analysis of what kind of flexibility is actually needed

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The Second Example

• Distributed Sensor Networks

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A Wireless Sensor Node

Solar Cell

Mirror Controller

Accelerometer

0.25µm CMOS – double poly, 5 metals

Photodiode

Receiver

Temperature Sensor

ADC

Charge Pump

Source: Smart Dust Project

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A Wireless Sensor Node

Source: Smart Dust Project

360µm

30 0 µ m

Photodiode

Pad to CCR

VddPad

GND Pad/

LFSR

Power-on Reset

Charge Pump

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Wireless Sensor Node – Design Constraints

• Low data-rates << 10kBit/s

• Self-configuring , maintenance-free, and robust

• Cost

– Very low-cost device – should be deployed everywhere

• Size

– Should not intrude on the environment it is deployed

• Power/Energy

– Operate in self-contained fashion for the life-time of the product – Energy must be ”picked-up” from the surroundings

– Electronics must consume extremely low levels of static and dynamic power

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Dynamic Power Consumption

• Reduce dynamic power consumption

– Obtain high MIPS/mW

– Dedicated processor architecture

• Low-level optimization

• Dynamic power management

– Make the sensor node reactive – wake it up on external events – Data/Instruction dependent activation of circuits

• Speed is not an issue

– Speed can be traded for low power

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Static Power Consumption

• A sensor node is idle most of the time

– Computation and communication < 1% of the time

• Also static power consumption must be reduced

– Power consumption when it is idle

• Reduce leakage currents in transistors

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Reduction of leakage

• Lower limit for the processor – leakage

Processor characteristics:

-Processor core: 15 000 transistors -102412bit Memory: 74 000 transistors -0.25m CMOS, v_t=0.55V

• Standby power reduction through substrate bias control

Core SRAM

6 nW 79 nW

0.35nW 6.4nW

|V_bs|=0.0V |V_bs|=0.5V

12-20 times reduction

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Power reduction for sensor nodes

• To achieve power reductions in digital circuits

– Known techniques to reduce dynamic power must be applied for low-level optimization on gate-, circuit-, and physical-levels

– Application specific processor and memory architectures must be designed – Static power dissipation dominates – Leakage currents must be controlled

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The Third Example

• Integration of complex systems on single chip

– System-on-Chip (SoC)

• Traditionally, one chip per function

– Memory

– Microprocessor, DSP, video- and audio processors – A/D D/A converters

– RF – Etc.

• SoC is the technology integrating all functions on

one chip

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CMOS IC technology enables SoC

400480088080 8085 8086

286386

486 PentiumP6

0.001 0.01 0.1 1 10 100 1000

1970 1980 1990 2000 2010

Transistors (MT)

2X growth in 1.96 years!

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Power Density

4004 8008

8080

8085 8086

286 386

486 PentiumP6 1

10 100 1000 10000

1970 1980 1990 2000 2010

Power Density (W/cm2)

Hot Plate

Rocket

Nozzle

Nuclear

Reactor

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Power Problems

• Power delivery

–Large voltage drops in the power supply distribution caused by large currents

• Electromigration

–High current densities may cause reliability problems

• High thermal dissipation in a single chip requires

–Advanced packaging technologies

–Expensive and bulky cooling devices like fans and heat-sinks

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Traditional IC Design

• One clock domain

clock

• One power supply voltage

• Global busses for communication

• One type of transistors

• One pMOS and one nMOS

• Homogenous technologies for homogenous functions

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SoC Requirements

• SoC characteristics

– Function units with very different requirements on the IC technology are integrated on the same chip

– Fully synchronous designs result in clock distribution networks that consumes approx. 50% if the total power

– Global busses will be slow and power hungry

• SoC is heterogeneous

– Requires a technology that matches the computational model

 there is a need for a ”heterogeneous” technology – Novel architectures

• Communication-based design

• Reconfigurable hardware

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CMOS Technology

• Application-specific MOS devices

High Voltage Low Leakage

High Speed

Ultra High

Speed EEPro

m

MRa

m

RF

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Global communication and synchronization

• Advantages

– Global Clock eliminated – Local clock

– Less stringent skew bounds – Lower Peak current

• Disadvantages

– Local clock generation – Synchronization problems – No established design

methodology

Data Control

Asynchronous communication

Different speed/power supply voltage Synchronous islands

SB

₁

SB

₂

SB

₃

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SoC summary

• Integration of heterogeneous functions on a single chip requires new solutions

• Novel architectures

– Power awareness in processor architectures and configurable hardware

• Novel circuit solutions

– Power supply voltage as a design parameter

• Novel design methods

– Communication-based design

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Summary on power

• Power and/or energy have become dominant drivers

– Limiting factor for performance and reliability in wall-plugged applications

– Enabler for wide-spread use of distributed computing and data access

• Large energy reduction require a joint optimization

process between application and implementation

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Projects in Low-power

• Techniques for building event-driven designs using asynchronous circuits

• Dynamic power management for controller design

• Construction of Variable-Length Codes and their CODECs for high speed and low power

• Low-Power Circuit Design for photon-counting pixel array detectors

• Digital circuits for low-noise/low-power in mixed

analog/digital designs

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Techniques for building event- driven designs using

asynchronous circuits

• General model for fully asynchronous circuits

clk

Asynchronous model:

Synchronous model:

• Project includes

– Development of re-usable basic structures

– System-level model for performance evaluation

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Asynchronous IC

• DSP for a spread-spectrum digital radio receiver

Design objective: verify the usefulness of proposed structures for “structured” design.

The design provide data for system-level modeling of complex asynchronous circuits.

Idea: Data-flow approach supporting local interconnections and with data rates adapting

to the actual speed needed.

Speed: 49 MHz

Power: 600 mW at 5V

Complexity: 100.000 transistors IC technology: 0.8 m CMOS

[Oelmann, Tenhunen]

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Dynamic power management for controller design

S0

S1

S2 S3

S4

0.6

0.2

0.005 0.005

0.01 0.04

0.04

0.1

FSM specification

 S



X Y

FSM implementation

clk

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LIFS – the CAD-tool

S4 ^S0T

S2

S1

S2T S3T

FSM #1 FSM #2

S4

S3

S2

S0

S1

Partitioner State probability

computation

Local FSM transformation

Input switching probabilities

Technology information User

constraints State-transition graph

CAD-tool for power optimization

In the 8051 C, the controller consumes

50% of the total power

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The Future of LIFS

• LIFS today

– Optimization procedures implemented in a tool written in JAVA – Optimization results: average of 45% power reduction over a set

of standard benchmarks

– Area penalty is a bit too high

• LIFS 2

– New approach that introduces a mixed synchronous/asynchronous state-memory – New optimization procedures

• Partitioning

• State-clustering

• State-encoding

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Construction of Variable-Length Codes and their CODECs

• Algorithm-level optimization

– High performance – low-power CODECs for VLCs – Focus on VLCs developed for image and video data

• Golomb-Rice

• Universal VLC

power

w/o suffix 1b suffix 2b suffix VLC decoder

GR-VLC decoder

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Low-Power Circuit Design for photon- counting pixel array detectors

• Pixel-arrays

– Consists of a large amount of pixels

• Photon-counting

– Each pixel contains several hundreds of transistors – Large power consumption – Mixed signal problems

• Asynchronous circuits

– Used for detecting events – Reduces power consumption

four times

Discriminator

Counter Output logic Pre-amplifier

Pulse shaper

Detector Comparators

Analog

Digital

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Digital circuits for low-noise/low- power in mixed analog/digital

designs

• A project starting up

• Objectives:

– Develop design techniques for digital circuits that induce low levels of noise in a mixed signal environment

– Develop on-chip measurement of digital noise

• The project involves:

– Characterization of sub-threshold and current-mode techniques – Architectural speed optimization

– Design automation aspects

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Conclusions

• Three different scenarios have been used to

illustrate the importance of low-power IC design

– Mobile wireless terminal (flexibility – power trade-off)

– ”power-less” sensor nodes (the ultimate low-power application) – System-on-chip (Power defines performance, system cost, and

reliability)

• Projects at the Electronics Design Division, MH

– Generic research

• Asynchronous design methods

• Low-power FSM design

– Application-specific

• VLC CODECS

Design of Integrated Circuits with Low-Power Consumption