Electronics System Design

Electronics System Design

Mattias O’Nils, Bengt Oelmann, Munir Abdalla Trond Ytterdal*, Tang Lei*

Benny Thörnberg, Håkan Norell, Shang Xue,

Jan Lundgren, Cao Cao*, Jon Alfredsson*

Activities

Electronics system design

Low-power design

Mixed-signal design Real-time image

processning Mattias O’Nils Bengt Oelmann Shang Xue

Håkan Norell

Benny Thörnberg Tang Lei*

Mattias O’Nils Bengt Oelmann Cao Cao*

Jon Alfredsson*

Mattias O’Nils Bengt Oelmann Munir Abdalla Jan Lundgren Trond Ytterdal*

Simulation Sensor

Electronics design division (Prof. Hans-Erik Nilsson)

Fibre

RFID

Bengt Oelmann Johan Sidén Peter Jonsson Torbjörn Olsson

Analog and Mixed-signal

• Readout electronics for X-ray imaging

– Integrating pixel read-out

– Photon-counting radiation detection (Colour X-ray imaging)

• Behavioural model of photon-counting pixel

• Behavioural noise coupling simulation

Analog and Mixed-signal

X-ray pixel detectors and readout

M2

M3 Reset M1

Ci D1

Col A

From upper pixel Shutter

Pulse shaper Threshold

adjust (3 bits) Preamp

Latched Comparator

Clkout Analog

Reset Test

input

To lower pixel Reset

Det input

Cfb

Ctest

Test (1 bit)

0 1

1 0

Mux Sel Mask

(1 bit)

Data Clk

Shift Reg Sel

Mux

Pixelated detector structures

Integration read-out

Photon counting read-out

Together with the

Medipix project

Analog and Mixed-signal

Behavioural modelling

HP LP

X-ray

source Filter Detector Charge

integrator Discriminator Clock

generator

Event counter Pulse shaping

Modelled in SystemC as synchronous data flow

Analog and Mixed-signal

Noise coupling simulation

A. Behavioural mixed-signal simulation

Block 1 Digital or analog

Y1=f(X1)

Block 2 Digital or analog

Y2=f(X2)

Block 3 Digital or analog

Y3=f(X3)

Block 4 Digital or analog

Y4=f(X4)

Model of power line and/or substrate interconnection between blocks

i3 i1 i2 i4

Y₃ X3

Y1

X1

Y₄ X4

Y2

X2

Interconnect

B. Simulation of noise coupling Proposed in this paper

Analog and Mixed-signal

Noise coupling simulation

// cnt16.h

#include "systemc.h"

#include "ncmod.h"

SC_MODULE(cnt16) { sc_in<sc_logic> rst;

sc_in<bool> clock;

sc_out<sc_lv<16> > cnt;

sc_uint<16> temp;

NC_SIM_PORTS;

void count();

SC_CTOR(cnt16) {

SC_METHOD(count);

sensitive << rst;

sensitive_pos << clock;

NC_CURRENT_SOURCE;

sensitive << clock;

temp = 0;

} };

cnt16

clk rst

vvdd ivdd ignd

q(15:0) Noise coupling simulation wrapper

im

ii

io R

C

vi vo

io ii

im Configurations:

R, C, time-step

a-clk

Low-power design

• Low-power FSM implementation

• Low-power floating-gate

Low-power design

Low-power finite-state machine design

S4

S3

S2

S0

S1

S4 ^S0T

S2

S1

S2T S3T

FSM #1 FSM #2

Partitioner Statistics collection

(FSM simulator)

Local FSM transformation

Input switching probabilities

Technology information User

constraints

VHDL code for logic synthesis State-transition graph

CAD-tool for power optimization

In the 8051 C, the controller consumes

50% of the total power

Low-power design

Low-power low-voltage floating-gate CMOS

V_dd

V_ss

a

b a b

z

UV-programmable 2-input gate

FG

FG

Sub-threshold technique for digital and analog functions

• Basic digital gates + Flip/flops

• Analog cells: current mirrors, multipliers etc.

Performance:

• Process: 0.8m CMOS

• Vdd=0.2V

• Energy: Full-adder 0.6fJ

• 2500 times lower power consumption than standard-cell

Programmability:

• Post-processing UV-programming

• Power-speed trade-offs made in the post- processing step

Real-time image processing

• Interface and memory architecture refinement

– Behavioural modelling and design analysis – Low-power optimisations

• Algorithm improvement

– Rapid prototyping – Video coding

– Image enhancement

• Video enhancement

• Angiography X-ray image enhancement

– Dental panoramic X-ray image reconstruction

Real-time image processing

IMEM

Pixel(frame=2,pixr=1,pixc=1)

Pixel(0,-1,1) row

column frame Body model

IMOD 1 OPERATION 1

IMOD 2 OPERATION 2

OUTPUT STREAM 1

OUTPUT STREAM 2 INPUT

STREAM 1

Functional mapping

Spatio-temporal mapping

IMEM Conceptual Modelling Simulation

Input Stimuli

Functional Simulation Data

Output 1

2

3

4

5

6

7

8

Design Refinement

Architecture Implementation

Database/

Constraints

Implementation Architecture Early Design Space Exploration

HW RTL-descriptions SW-code for processors

Co-simulation/

verification HW-synthesis

Early Power and Area Estimation

Data

SW-code optimization Interface and

Memory Model Functional mapping of algorithm

Real-time image processing

RIPA

In stream FPGA FPGA Out stream

B uf fe r B uf fe r

Memory Memory

Interfaces ^{Store all}

active frames

Communication speed

(PAL:30 Mbyts/s)

Real-time image processing

Design of robust VLC Codecs

VLC

Coder Channel VLC

Decoder

Data packet

Bit error

Lost data

symbol symbol

Video transmission over a noisy channel

Real-time image processing

Video filter

Input sequence: 5% Contamination

Processed sequence

) ( , ) (nYn B

) 1 ( , ) 1 (n Yn B

) 2 ( , ) 2 (n Yn B

) 3 ( , ) 3 (n Yn B

) 3 ( , ) 3 (n Yn B

) 2 ( , ) 2 (n Yn B

) 1 ( , ) 1 (n Yn B

Sc en e ch an ge in di cat io Median n

filter

0

M U X

Output Pixel

TY T ,B Thresholds

n~

Real-time image processing

Angiography image enhancement

Real-time image processing

Panoramic image reconstruction

Image Reconstruction

Algorithm

Reconstructed Image Pre-

processing 1. Image acquisition

3. Image reconstruction (Post-processing) 2. Image pre-processing

Patient

X-ray image sensor

X-ray tube

Communication channel

RFID-tag

7.5 mm 49 mm

1 mm

No internal power supply

Research topics at MH

•Robust antenna design

•RFID Application surroundings

•Fractal antenna design