Implementation of an Active Pixel Sensor with Shutter and Analog Summing in a 0.35um Process

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Implementation of an Active Pixel

Sensor with Shutter and Analog

Summing in a 0.35 µm Process

Robert Johansson

LITH-ISY-EX-3473-2003 Linköping 2003

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Implementation of an Active Pixel

Sensor with Shutter and Analog

Summing in a 0

.35 µm Process

Master Thesis

Division of Electronic Devices Department of Electrical Engineering

Linköping University, Sweden by

Robert Johansson

LITH-ISY-EX-3473-2003

Supervisor: Johan Melander (IVP AB) Examiner: Professor Atila Alvandpour

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Avdelning, Institution Division, Department

Institutionen för Systemteknik

581 83 LINKÖPING

Datum Date 2003-09-02 Språk Language Rapporttyp Report category ISBN Svenska/Swedish X Engelska/English Licentiatavhandling

X Examensarbete ISRN LITH-ISY-EX-3473-2003

C-uppsats

D-uppsats Serietitel och serienummer_{Title of series, numbering} ISSN Övrig rapport

____

URL för elektronisk version

http://www.ep.liu.se/exjobb/isy/2003/3473/

Titel Title

Implementation av en ljussensor med aktiva pixlar, elektronisk slutare och analogsummering i en 0.35um process.

Implementation of an Active Pixel Sensor with Shutter and Analog Summing in a 0.35um Process Författare Author Robert Johansson Sammanfattning Abstract

An integrated circuit for evaluation of APS technology has been implemented in a 0.35 um process. The APS features snapshot operation and the readout circuitry can carry out: CDS, DS, and analog summing all in one circuit that is fully programmable. The output from the chip is a differential analog signal, intended to be connected to a high-speed ADC on an evaluation board. The sensor is fully compatible with current IVP camera systems, hence, the evaluation board should be easy to design.

Several small code snippets that illustrate different modes of readout have been outlined, to aid the evaluation of the chip. It should be fairly straightforward to convert these code snippets into actual camera code. Furthermore, some code to illustrate a possible application and a faster mode of CDS have been indicated.

Six types of APs have been implemented. They differ regarding diode type and implementation of the sampling capacitor. Design instructions and models for hand calculation have been

described. The models have in most cases been validated by simulations and it has been shown that a readout speed of 8 MHz is possible to obtain, even for a larger sensor than this test chip. The desired resolution of 8 bits cannot be obtained for high levels of illumination. However, for low levels of illumination a resolution as high as 10 bits is possible.

The chip layout has been validated to a large extent and should result in a fully functional chip, if manufactured. However, in the eventuality that IVP decides to manufacture this chip it is recommended to use the newer CAD tools, not available to the author at the time of

implementation, to check the chip design for DRC and LVS errors. Nyckelord

Keyword

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Abstract

An integrated circuit for evaluation of APS technology has been implemented in a 0.35 µm process. The APS features snapshot operation and the readout circuitry can carry out: CDS, DS, and analog summing all in one circuit that is fully programmable. The output from the chip is a differential analog signal, intended to be connected to a high-speed ADC on an evaluation board. The sensor is fully compatible with current IVP camera systems, hence, the evaluation board should be easy to design.

Several small code snippets that illustrate different modes of readout have been outlined, to aid the evaluation of the chip. It should be fairly straightforward to convert these code snippets into actual camera code. Furthermore, some code to illustrate a possible application and a faster mode of CDS have been indicated.

Six types of APs have been implemented. They differ regarding diode type and implementation of the sampling capacitor. Design instructions and models for hand calculation have been described. The models have in most cases been validated by simulations and it has been shown that a readout speed of 8 MHz is possible to obtain, even for a larger sensor than this test chip. The desired resolution of 8 bits cannot be obtained for high levels of illumination. However, for low levels of illumination a resolution as high as 10 bits is possible.

The chip layout has been validated to a large extent and should result in a fully functional chip, if manufactured. However, in the eventuality that IVP decides to manufacture this chip it is recommended to use the newer CAD tools, not available to the author at the time of implementation, to check the chip design for DRC and LVS errors.

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Acknowledgement

I would especially like to thank my supervisor, the former head of the ASIC de-partment at IVP, Johan Melander for all the help and support with this thesis. Furthermore, I would like to acknowledge my sincere gratitude to my former col-leagues at IVP: Leif Lindgren, Björn Möller, and Annika Rantzer for contributing with helpful pieces of advice, knowledge, and literature sources. Many are those fun and interesting discussions that, in one way or another, made it into this thesis. All the employees at IVP should take credit for making it a company I did enjoy carrying out this thesis on behalf of and for many years working for.

I would also like to thank my examiner Professor Atila Alvandpour for all the useful comments and discussions upon the contents of this thesis. I am very grateful to Anders Johansson for reading through this thesis, correcting errors, and pointing out aspects I had not thought of. I would also like to thank Krister Sjögren for the initial help with LATEX.

Finally, I would like to thank my parents Hans and Ellen Johansson. Without their help and encoragement throughout my school-days this thesis would never have been written.

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Abbreviations

ABBREVIATIONS 3D 3-Dimensional

A/D Analog to Digital AC Alternating Current ACF Auto Correlation Function ADC Analog to Digital Converter AS Analog Summing

AP Active Pixel

APS Active Pixel Sensor

CMOS Complementary Metal Oxide Semiconductor CCD Charged Coupled Device

CCI Channel-Charge Injection CDS Correlated Double Sampling CFT Clock Feedthrough

CMF Common Mode Feedback CAD Computer Aided Design DAC Digital to Analog Converter DS Double Sampling

DRC Design Rule Check EHP Electron Hole Pair EPI Epitaxial

FF Fill Factor

FPN Fixed Pattern Noise IC Integrated Circuit

IVP Integrated Vision Products AB LSB Least Significant Bit

LVS Layout Versus Schematic MPW Multi Project Wafer

MOS Metal Oxide Semiconductor

MOSFET Metal Oxide Semiconductor Field Effect Transistor

see next page

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from previous page

MSB Most Significant Bit NDIFF n-type Diffusion

NMOS n-type channel Metal Oxide Semiconductor NWELL n-type Well

OP Operational Amplifier

OTA Operational Transconductance Amplifier PDIFF p-type Diffusion

PMOS p-type channel Metal Oxide Semiconductor PWELL p-type Well

POLY Polycrystalline PPS Passive Pixel Sensor PSD Power Spectral Density PSRR Power Supply Rejection Ratio QE Quantum Efficiency

S/N Signal to Noise ratio SC Switched Capacitor STD Standard Deviation

SIMD Single Instruction Multiple Data

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7.2.1 Overview . . . 83 7.2.2 Substrate Coupling . . . 83 7.3 Matching . . . 84 7.4 Validation . . . 86 7.4.1 Schematic Capture . . . 86 7.4.2 Layout . . . 87 7.4.3 DRC . . . 87 7.4.4 LVS . . . 87 7.4.5 Simulation . . . 88 8 Results 91 8.1 Improvements . . . 91 A Process Parameters 95 A.1 Doping Profile . . . 95

A.2 Diode Capacitance . . . 98

A.3 Optical Properties . . . 99

A.4 Miscellaneous Equations . . . 100

B FPN 103 B.1 Rolling Shutter Readout FPN . . . 103

B.2 Snapshot Readout FPN . . . 103

C Analog Schematics 107 C.1 Active Pixel . . . 107

C.2 Pixel Bias Circuit . . . 108

C.3 Folded Cascode OP . . . 109

C.4 OP Bias Circuit . . . 110

C.5 CMF Bias Circuit . . . 111

C.6 Common Mode Feedback . . . 112

C.7 Output Buffer . . . 113

C.8 Output Buffer Bias Circuit . . . 114

D Digital Schematics 115 D.1 Clock Generator . . . 115

D.2 Transmission Gate . . . 116

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D.4 Level Shifter . . . 117 D.5 Reset Buffer . . . 117 E Pad Listing 119 References 121 Index 125 Copyright 129

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List of Figures

1.1 Cross-section of a simplified CCD sensor. . . 3

2.1 NMOS and PMOS transistor symbols. . . 9

2.2 Small signal models. . . 11

2.3 Noise models. . . 14

3.1 Chip overview. . . 16

3.2 Schematic overview of the readout chain. . . 18

3.3 Timing diagram. . . 19

3.4 NOP. . . 20

3.5 SETR. . . 20

3.6 SETC. . . 20

3.7 SETS. . . 21

4.1 Schematic of the active pixel. . . 27

4.2 Sensor area vs maximal image. . . 30

4.3 Number of pixels in ˆx direction vs pitch. . . 31

4.4 FF vs Pitch. . . 32

4.5 ICOL vs T for 512 rows. . . 33

4.6 The two types of photo diodes. . . 34

4.7 JDC vs VD. . . 39 4.8 JDC vs T . . . 39 4.9 JOP T vs λ, NWELL/EPI. . . 42 4.10 JOP T vs λ, NWELL/EPI. . . 42 4.11 JOP T vs λ, NDIFF/PWELL. . . 43 4.12 JOP T vs λ, NDIFF/PWELL. . . 43 4.13 η(λ) vs λ. . . 44

4.14 Simplified model to calculate charge injection. . . 46

4.15 Maximum output swing of VCOL vs CS for different values of CD. . 48

4.16 Irradiance F0 (and P0 at 500 nm) vs CS, VS= 3.3 V, T = 300 K. . . 49

4.17 Equivalent small signal schematic of the pixel during readout. . . . 51 xvii

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4.18 Rolling Shutter readout. σVR−VS and σVS vs F0. . . 53

4.19 Snapshot readout. σVR−VS and σVS vs F0. . . 53

4.20 Equivalent small signal schematic to calculate source follower gain. 54 4.21 Small signal schematic to calculate reset noise. . . 55

4.22 Small signal schematic to calculate shotnoise. . . 56

4.23 Small signal schematic to calculate shutter noise. . . 57

4.24 Small signal schematic to calculate temporal noise during readout. 58 4.25 Small signal schematic to calculate temporal noise during readout. 58 4.26 Rolling Shutter readout. Temporal noise vs F0. . . 62

4.27 Snapshot readout. Temporal noise vs F0. . . 62

4.28 Signal to noise ratio vs F0. . . 63

4.29 Total noise vs F0. . . 64

4.30 Simulated DS signal vs F0. . . 64

5.1 The SC circuit implementation of the CDS/AS unit. . . 69

5.2 The different phases during for a column of the CDS/AS unit. . . . 70

6.1 The internal clock phases. . . 73

6.2 Instruction decoding. . . 74

6.3 Row Multiplexer. . . 75

6.4 Output Multiplexer. . . 76

6.5 Switch Signal Generator. . . 76

7.1 Pixel Layout. . . 80

7.2 Chip Layout. . . 82

A.1 Part of a wafer cross section. . . 96

A.2 Absorption Coefficient vs Wavelength. . . 100

C.1 Active Pixel and Column Load. . . 107

C.2 Pixel Bias. . . 108

C.3 Folded Cascode OP. . . 109

C.4 OP Bias Circuit. . . 110

C.5 CMF Bias Circuit. . . 111

C.6 Common Mode Feedback. . . 112

C.7 Output Buffer. . . 113

C.8 Output Buffer Bias Circuit. . . 114

D.1 The internal clock generator. . . 115

D.2 Implementation of a transmission gate. . . 116

D.3 Implementation of a d-latch. . . 116

D.4 Level shifting circuit. . . 117

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List of Tables

1 Abbreviations used in this thesis. . . xii

1.1 Clocking sequence for the CCD column. . . 3

2.1 Small signal parameters. . . 12

3.1 The symbolic names of the switches. . . 21

4.1 Dark current parameters NDIFF/PWELL diode. . . 37

4.2 Dark current parameters NWELL/EPI diode. . . 38

4.3 Dark current at 3.3 V and 300 K. . . 38

4.4 Possible digital resolution up to a certain value. Voltage swing 1 V. 65 4.5 Summary of pixel parameters. . . 65

A.1 Process parameters. . . 97

A.2 Doping profile parameters. . . 97

A.3 Process parameters. . . 98

A.4 Diode parameters. . . 99

B.1 FPN parameters rolling shutter readout. . . 104

B.2 FPN parameters snapshot readout. . . 105

E.1 Pad listing with short description. . . 120

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CHAPTER 1 Introduction

This master thesis has been carried out on behalf of the company Integrated Vi-sion Products AB (IVP) in Linköping. A company, founded in 1985, that offers products for high-speed 3D measurement. These products consists of some type of camera together with software and are used in machine vision applications in for example: wood, electronic, food, and defence industry. The core technology of these cameras is a so called smart vision sensor. An image sensors with not only the light sensitive pixel array integrated on-chip but also analog readout circuitry, A/D converters, image processors and memory. The result is an image sensor that can interpret and process image data at very high speed, all developed in-house at IVP. The high processing speed is due to the Single Instruction Multiple Data (SIMD) architecture as well as the high level of system integration in the sensor. For more information see [21], [35], and [36].

1.1 Definition and Goal

The objective of this master thesis is to design and implement (using full custom layout) an Active Pixel Sensor (APS) with accompanying readout circuitry in a 0.35 µm CMOS process. The APS should be capable of so called snapshot operation and the readout circuitry should carry out Correlated Double Sampling (CDS) in order to reduce Fixed Pattern Noise (FPN). Furthermore, should the readout circuitry have the ability to add consecutive analog pixel values.1

The goal with the implementation is that it should result in a manufactured chip to be used in the evaluation of APS technology.

• In order to make the evaluation fairly easy the chip should be adopted to current test equipment. This requires that the chip is designed for a standard IC package that is to be mounted on a custom made evaluation board that in turn is connected to an IVP camera system. For this to work some digital control logic will have to be implemented on-chip. Furthermore, to make it

1_{Referred to as analog summing or binning in this thesis.}

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easier for IVP to evaluate the chip, the structure of a test program should be outlined.

• For evaluation purposes the image sensor should, at least, contain pixels with two different types of photo diodes and two different types of sample capacitors. To be able to draw conclusions from the evaluation the array of pixels need to be fairly large in order to avoid edge phenomena. It is suitable for every type of pixel to build an array of 64 × 64 pixels.

• The targeted performance is to be able to clock the circuit at 8 MHz and achieve a resolution of 8 bits. To verify that this is possible some models need to be designed and simulations carried out. Design models for the pixels are more important than for the readout circuit and should be favoured if time does not permit both to be studied.

1.2 Background

In machine vision applications the features required of a measurement system are often: small size, low cost and high speed. However, the demands on image quality are often not that high. This relaxation in image quality is something that needs to be considered when an image sensor for machine vision is designed. The first decision to be made is which technology to use when converting the light into an image. There exist a large number of ways to do that even if the choice is narrowed to what can be implemented on silicon (see for example [10] and [37]). Then there is also the subject of patents that limit the number of technologies that can be chosen from.

An image sensor implemented in a standard CMOS process has the potential to realise a low cost, small size, and high speed measurement system since the process is cheap,2 _{available from many vendors, and offers the possibility to integrate many}

other digital and analog functions on-chip. Traditionally Charged Coupled Device (CCD) image sensors have been used in cameras for machine vision. However, a CCD requires a specialised process, thus, it is interesting to see how a CMOS sensor would compare to a CCD.

1.2.1 CMOS versus CCD

A CCD image sensor is basically an array of capacitors formed by polycrystalline silicon (POLY) wires over a p-type substrate. A simplified cross-section of a pixel in a CCD sensor can be seen in Figure 1.1. A pixel consists of the area bounded by the POLY wires Φ1 and Φ3 and the column isolators. If a positive pulse is

applied to Φ2 a depletion region will form under the gate and the surface potential

will increase considerably under the gate. In effect, the surface potential forms a potential well, which can be used to store electrons. In steady state this potential well will be filled up by thermally agitated electrons and the normal inversion

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1.2. Background 3

Φ1 Φ2 Φ3 Φ2

SiO2 Column isolator

p− p−

p+ _p+

ˆx y ˆ

Figure 1.1: Cross-section of a simplified CCD sensor.

condition will prevail. Since the POLY is transparent for visible light,3 _{the photons}

will generate electron-hole pairs (EHPs) in the substrate. Some of those electrons, generated in the depletion region or close enough to diffuse into it, will then be swept into the potential well and be stuck there. This provided that Φ2 is held

at a high potential (H) while Φ1 and Φ3 are held at a low potential. After the

light has been integrated the electron packages are shifted down the column by the sequence shown in Table 1.1. Then at the end of the column they are read into

−→ 1 2 3 4 5 6 Φ1 L L H H H L Φ2 H L L L H H Φ3 H H H L L L

Table 1.1: Clocking sequence for the CCD column.

an analog shift register and shifted along the row to be converted into a voltage by the readout amplifier.

The principles of converting light into charges are, more or less, the same in a CMOS sensor it is the readout that differs. EHPs generated within or close to the depletion region of a reverse biased pn diode will collect electrons at the cathode and holes at the anode, connected to the substrate. These electrons are then read out as either a voltage or as charges via a column bus to a row of readout circuits. The principles of operation, briefly described in this section, lead to the follow-ing pros and cons of usfollow-ing CCD and CMOS sensors:

CCD

+ High sensitivity due to process optimisation. + High image quality due to process optimisation.

+ Readout speed (pixels/s) does not need to decrease when the sensor size is increased.

− Specialised process that is more expensive and not as available as a standard CMOS process.

3_{For shorter wavelength, such as blue light, the sensitivity will be worse due to the POLY}

wires. However, the POLY wires of a CCD process are much thinner than in a comparable CMOS process.

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− Many different clock signals and voltage sources to distribute across the chip. Moreover, the clock signals need to drive large capacitive loads.

− Although it is not impossible to integrate clock drivers and image processing units on-chip it is not practical nor economically feasible.

− The previously mentioned cons lead to the use of several ICs and high power consumption.

− Random access of pixels is not possible.

CMOS

+ Processes are cheap and available from many different vendors. + Image processing units can be integrated on-chip.

+ The previously mentioned pros result in low prize, low total power consump-tion, and high image processing speed.

+ Random access of pixels.

− Medium sensitivity due to the lack of desired process optimisations. − Medium image quality due to the lack of desired process optimisations. − Smaller sensor array. The capacitive load of the column bus makes it difficult

to realize a sensor with as many rows as in the CCD case and maintain speed.4

This comparison makes it clear why CMOS sensors are more interesting to use in machine vision than CCD sensors. For more information on the topic of CMOS versus CCD see for example [22], [30], and [32]. A recent implementation of a CCD image sensor can be found in [33] and [34]. A recent implementation of a CMOS image sensor can be found in [35].

1.2.2 Active versus Passive Pixel

There are two basic types of CMOS sensors that differ in how the collected charges are read out. The Passive Pixel Sensor (PPS) has no amplification from the light sensitive device (photo diode, photo transistor and so on) to the column wire, which is common for all the pixels in that column. Thus, charges are read out and converted into a voltage in the readout circuit, not part of the pixel array. Whereas, the Active Pixel Sensor (APS) has an amplifier in every pixel that decouples the light sensitive device from the column wire. Thus, the charge to voltage conversion is done in the pixel. This difference gives rise to the following pros and cons for the passive and active pixel ([24] and IVP knowledge):

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1.2. Background 5

PPS

+ High fill factor. That is most of the area of the pixel is made up of the light sensitive component (photo diode or transistor).

+ Low FPN. + High linearity.

+ Easy to implement binning.

− Large amount of temporal5 _{noise for low illumination levels.}

− High column leakage. − Low PSRR.

− Difficult to make a sensor with many rows due to the high capacitance of the column bus. This because the readout amplifier becomes difficult to design due to the high feedback factor.

− The high capacitance of the column bus makes it difficult to reach high read-out speed when the sensor has many rows. This because the high feedback factor results in a readout amplifier with low bandwidth.

APS

+ Medium amount of temporal noise for low illumination levels.

+ Fairly easy to reach high readout speed for a sensor with many rows. + Medium PSRR.

− Medium fill factor. − High FPN.

− Medium linearity.

− Difficult to implement binning.

The active pixel has many benefits over the passive pixel especially when the pixel sensor has many rows. One major drawback, however, is the high levels of FPN. That is when the sensor is uniformly lit the image contains a fixed pattern of darker and lighter areas. This pattern is not dependent of time and remains the same from image to image. The FPN can be reduced to more tolerable levels by the use of a technic called Correlated Double Sampling (CDS) or just Double Sampling (DS) see Chapter 3.

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1.2.3 Snapshot Operation

A sensor capable of snapshot operation can deliver images where all pixels are sampled at the same instant in time. This requires that the sensor is equipped with an electric shutter.6 _{Something that seems as the natural thing to do, however,}

a very common way to operate a CMOS sensor, for machine vision, is to use a technique referred to as rolling shutter. In this mode the reset, light integration and readout are done on a row basis7 _{resulting in fast moving objects being deformed,}

a fact that cannot always be ignored or compensated for. The drawbacks of an electric shutter are: it requires an extra transistor in every pixel, power noise and propagation delays can be difficult issues when the entire sensor is operated on, and the temporal noise increases. However, a sensor with shutter can also be operated in the same way as a sensor only capable of rolling shutter operation.

1.2.4 Binning

Binning is a way to improve the Signal to Noise ratio (S/N) by amplifying the signal more than the noise. This selective amplification is done by adding pixel values together,8 _{thus, the improved S/N is obtained by trading away spatial resolution.}

The summing should be carried out as early as possible, in the readout chain, to be able to detect small signals. That is why the summing is done in the analog domain.

1.3 Reading Instructions

APS is sometimes discussed in a general sense in this thesis. In order to distinguish between a general APS and the sensor implemented the latter will be referred to as “MPW00.1”, whenever it is not obvious which sensor that is concerned. MPW is an abbreviation of Multi Project Wafer, 00 is the year the sensor was implemented, and 1 is just a number. The rest of this section provides a short description of the topics in the various chapters.

Chapter 2 page 9

is devoted to basic theory such as transistor models and the motivation of their usefulness, noise models and so on. This chapter can be skipped by the reader with previous knowledge in this area.

Chapter 3 page 15

provides the reader with an overview of the whole construction, and the parts it is built up from. Furthermore, an instruction set and example programs are presented. They should serve as a programming guide during the evaluation of the sensor.

6_{Often referred to as just shutter in this thesis.}

7_{In contrast to snapshot operation where the same is done for the entire image.} 8_{The resulting signal is given by X}

Stot =PM_k=1XSk whereas the noise is given by XN tot=

q PM

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1.3. Reading Instructions 7

Chapter 4 page 27

is the main chapter that describes the design of the APS the way it oper-ates, the photo diode, the sample capacitor, fixed pattern noise, temporal noise and so on. This chapter also presents design guidelines, models, and simulations to illustrate things to consider during the design.

Chapter 5 page 67

features a short description of the CDS and analog summing unit followed by an overview of the rest of the readout circuitry.

Chapter 6 page 73

presents an overview of the digital control logic.

Chapter 7 page 79

contains a discussion of the layout and the layout styles and concepts that have been used in order to minimise matching errors as well as to reach high performance. This chapter also provides a discussion on how the chip layout has been validated.

Chapter 8 page 91

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CHAPTER 2 Basic Theory

This chapter contains a short description of the MOS transistor theory that is taken for granted to be common knowledge in the following chapters. Also a motivation to what level of complexity to use in the MOS transistor models, when doing hand calculations, are presented. Furthermore, something on the topic of noise and the various noise sources in the MOS transistor are described. The theory presented in this chapter is in no way comprehensive enough to suffice as an introduction to CMOS digital or analog integrated circuits. So in the case of no previous knowledge it is probably necessary to consult some books on the topics for example: [1], [3], and [4].

2.1 The MOS Transistor

The symbols of NMOS and PMOS transistors used in this thesis can be seen in Figure 2.1. In digital circuits the simplified version found in Figure 2.1(c) and

G D S (a) Analog NMOS. G D S (b) Analog PMOS. G D S (c) Digital NMOS. G D S (d) Digital PMOS.

Figure 2.1: NMOS and PMOS transistor symbols.

Figure 2.1(d)are used instead. The bulk connection is assumed to be connected to the supply voltages (VDD for PMOS and GND for NMOS) unless otherwise indicated by explicitly showing the connection.

The equations used for hand calculations are presented in equation 2.1 (cutoff 9

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region), equation 2.2 (triode or linear region), and equation 2.3 (saturated region) ID ≈ 0 VGS< VT (2.1) ID = K W L (VGS− VT)VDS− V_DS2 2 VGS≥ VT, VDS < (VGS− VT) (2.2) ID = K 2 W L VGS− VT 2 1 + λVDS VGS≥ VT, VDS ≥ (VGS− VT) (2.3)

where K is the transconductance parameter,1 _{W and L are channel width and}

length, respectively, VT is the threshold voltage, and λ is the channel-length

mod-ulation parameter. Often λ is taken to be zero since it is rather small, which leads to a simplification of the equation in the saturation region shown in equation 2.4.

ID = K 2 W L VGS− VT 2 (2.4) The threshold voltage depends on the source-to-bulk voltage VSB and equation 2.5

is often used to calculate VT

VT = VT 0+ γ p|2ΦF + VSB| − q 2|ΦF| (2.5) where VT 0 is the threshold voltage at zero VSB, ΦF is the Fermi potential and γ

the substrate bias coefficient.

These equations presented here are valid for NMOS transistors but can also be used for PMOS transistors by, for example, taking the absolute value of the parameters in the formulas. However, these equations are not very accurate in the short-channel region (or rather high-field region). When the electric field E in silicon reaches 105_{− 10}6_{V/m the electron velocity starts to saturate, which leads}

to many effects that make the equations presented less useful. This is certainly the case in the 0.35 µm process that is used in this thesis. There are also other effects, due to the small dimensions, that further diverts the calculated values from those actually measured. The equations are used in hand calculations merely because they are fairly easy to use. The result obtained from them should be used as a guide in design or as a hint to which parameters a certain value depends on. Therefore, it is necessary to validate the function of a circuit with the use of SPICE simulations, for modern processes.

2.2 Small Signal Models

A small signal model is a linearization of the equations at a quiescent point of the device. This implies that the MOS transistor must have different models depending of which region of operation it is currently working within. The models shown in Figure 2.2 are often good enough and valid both for NMOS and PMOS transistors. Of course it is possible to add more to these models such as the resistance of the substrate and other parameters but considering their limited value

1_{K = µC}

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2.2. Small Signal Models 11 s b g d Csb Cgs Cdb Cgd (a) Cutoff. s b g d Csb Cgs Cdb Cgd rds (b) Triode. g s b d Cgs Cgd Csb Cdb rds gmvgs gsvsb (c) Saturation.

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of accuracy, due to short-channel effects, it is often not worth the trouble. The parameters used in these models: gm, gs, and rds are defined by equations 2.6, 2.7,

and 2.8 gm ≡ ∂ID ∂VGS (2.6) gs ≡ ∂ID ∂VSB (2.7) gds ≡ ∂ID ∂VDS = 1 rds (2.8) Applying these definitions on the equations 2.1, 2.2, and 2.3 result in the expres-sions in Table 2.1. The capacitances can be derived from geometrical properties of

Param. Cutoff Triode Saturated

gm 0 KW_LVDS KW_L (VGS− VT) (1 + λVDS) gs 0 gmγ 2√|2ΦF+VSB| gmγ 2√|2ΦF+VSB| gds 0 KWL (VGS− VT − VDS) K2 WL (VGS− VT) 2 λ Table 2.1: Small signal parameters.

the transistors but more accurate values are often provided by the process supplier as empirical formulas.

2.3 Noise

The noise signals are modelled as weakly stationary processes. That is the math-ematical expectation x(t) is constant. This condition establishes that the Auto Correlation Function (ACF) is given by equation 2.9, thus, only dependent on the time difference τ .

RX(t + τ, t) = RX(τ ) = x(t + τ ) x(t) (2.9)

The Power Spectral Density (PSD) SX(f ) is given by the Fourier transform of the

ACF. The total average noise power is then given by equation 2.10. x2 _{= R}

X(0) =

Z ∞

−∞

SX(f )df (2.10)

If y(t) is given by x(t) filtered by a liner filter with the transfer function H(f ) then equation 2.11 and 2.12 holds true for RY and SY.

RY(τ ) = ∞ Z Z −∞ h(τ1)h(τ2)RX(τ − τ1+ τ2)dτ1dτ2 (2.11) SY(f ) = |H(f)|2SX(f ) (2.12)

If several uncorrelated noise sources are present the total average noise power can be obtained by summing the contribution from the different noise sources x2_tot = x2₁+ . . . + x2

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2.3. Noise 13 There are several sources of noise in a MOS transistor or a diode of which only the most significant types will be presented in the following sections. Since the PSD is an even function only positive frequencies need to be taken into account if the PSD is doubled. This doubled PSD is referred to as single sided PSD and is always used in this thesis unless otherwise stated.

2.3.1 Thermal Noise

Originates from the random motion of agitated electrons giving rise to a current. The thermal noise in resistors, transistors, and so on is white meaning that the PSD is constant and independent of frequency.2 _{In a MOS transistor it is given}

by equation 2.13

SIn,th(f ) = 4kT γgds0 [A2/Hz] (2.13)

where according to [2] SIn,th is the drain current noise of the MOSFET, k is

the Boltzmann constant, T is the temperature, γ is a constant that is unity in the triode region and approaches 2/3 in the saturated region for a long-channel MOSFET,3 _{and g}

ds0 is the drain-source conductance at zero VDS. With the use

of the definitions of gm, gds, the simplified square-law behaviour in equation 2.4,

and equation 2.2 gds0 can be written as gm where gm is the transconductance of

the transistor in the saturated region.

The drain current noise results in voltage fluctuations in the channel of the MOS transistor. Thus, the voltage from the gate to an arbitrary point in the channel has a random component. This variation in voltage, in turn, results in an AC gate noise current due to the capacitance between the gate and the channel. Since this gate noise current originates from the drain noise current it is correlated to the same by a factor of 0.39 [4]. Fortunately, this gate noise current is not a significant noise source at all for lower frequencies and will not be further considered here.

2.3.2 Shotnoise

A necessary condition for a device to exhibit shotnoise is that a DC current flows through the device and that this current is subjected to a potential barrier.4

Shot-noise is due to the fact that the electron charge is a discrete bundle and the ran-domness of the arrival at the potential barrier is what makes the shotnoise white. It can be modelled by equation 2.14.

SIn,s(f ) = 2qIDC [A2/Hz] (2.14)

In a MOS transistor it is only the gate leakage current that generates shot noise and it is normally so small that it can be ignored. However, in the APS photo electron shotnoise is the dominant noise source at high levels of illumination (see Section 4.5), thus, this kind of noise need to be further considered in this thesis.

2_{The thermal noise of a resistor is white to about 80 THz [2], thus, can be considered white}

for most electrical circuits.

3_{Measurement shows that γ is quite large for a short-channel NMOS transistor in saturation.}

In the order of 2 − 3 but it can be considerably larger [2].

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2.3.3 Flicker Noise (1/f )

Flicker noise is a kind of noise that has a spectral density that is a function of the type K

fn. In electrical devices it is more prominent in devices that are sensitive to

trapping of charges, and other surface phenomena, so it is a major noise source in MOS transistors. Since flicker noise originates from the random trapping and releasing of charges it is a function of current. However, for a MOS transistor it is usually modelled according to equation 2.15 see for example [1] and [3].

SIn,f(f ) = K f g2 m W LCox [A2/Hz] (2.15) K is a device specific parameter that normally is much larger for NMOS transistors than PMOS transistors, W and L are gate width and length, respectively, of the transistor, and Cox is the unit capacitance of the gate.

2.3.4 Noise Summary

The main noise sources in MOS transistors are thermal noise and flicker noise. Thus, a MOS transistor can be modelled by a noiseless transistor with a noise source in parallel as shown in Figure 2.3(a) and a PSD given by equation 2.16. If the body effect is ignored the transfer function from a current source between

G

S D

Ind

(a) MOSFET noise model.

G

S D Vng

(b) MOSFET noise model for low and moderate fre-quencies.

Figure 2.3: Noise models.

the drain and source to a voltage source in series with the gate is 1

gm for low

frequencies. Thus, for low and moderate frequencies the model in Figure 2.3(b) can be used together with equation 2.17.

SInd,tot(f ) = 4kT γgm+ K f g_m2 W LCox [A2/Hz] (2.16) SV ng,tot(f ) = 4kT γ 1 gm +K f 1 W LCox [A2/Hz] (2.17) All noise sources presented in this section are time dependent in contrast to FPN that is dependent on the room coordinates (spatial noise). The time depen-dent noise is referred to as temporal noise in this thesis, a term common in machine vision literature.

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CHAPTER 3 Overview of the Chip

This chapter contains a top-level overview of the chip (MPW00.1) and a description of the different blocks at the top-level. Furthermore, there is a description of the instruction set and some example pseudo-code programs.

3.1 Building Blocks

A schematic overview of the whole chip can be seen in Figure 3.1. The chip consists of the following blocks:

Pixel Array _{is the light sensitive sensor built up from an array of 128 × 192} active pixels. Since there are six different types of APs the sensor is further divided into areas of 64 × 64 pixels, however, the function of all pixels is the same so from an operating point of view there is no difference between them. Each pixel has three control signals that are common for an entire row and they are: P ON that controls the switches that connect the output voltage from the pixels to the column bus, SHT that is used in order to perform the snapshot operation, and RST that is used to reset the pixels. All pixels in a column share a common wire that is connected to the CDS/AS unit and all the column wires put together make up the column bus. Thus, the pixel values are fed to the CDS/AS unit row by row. See Figure 3.2 and Section 4.1 for further details.

Correlated Double Sampling and Analog Summing Unit (CDS/AS) is a Switched Capacitor (SC) circuit that can perform CDS or DS on the pixel output signal and analog summing of different rows. See Figure 3.2 and Section 5.1 for information on how this unit is implemented.

Output Multiplexer is used to multiplex the 192 signals from the CDS/AS unit to one signal, since it would not be practical to have 192 signals out

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CLK I SRST SSHT SP ON VOU T 128 128 128 16 8 3 10 8 192 192 × 2 2 2 Pixel Array 128 × 192

Correlated Double Sampling and Analog Summing Unit Instruction Decoder Output Multiplexer Output Buffer Row Multiplexer

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3.2. Pixel Readout 17 from the chip to measure at.1 _{See Figure 3.2 and Section 6.4 for further}

details.

Output Bufferis used to drive the external pins of the chip. This because their capacitive loads are much higher than what is possible for the CDS/AS unit to drive. At least with the timing requirements put on the test chip. See Figure 3.2 and Section 5.3 for further details.

Row Multiplexer is used to select which row to feed to the CDS/AS unit in the same manner as the column multiplexer is used to select which column to feed to the output buffer. The row multiplexer, however, is somewhat more complicated since it is possible to perform reset as well as snapshot operations on the entire pixel array. See Section 6.3 for further details. Instruction Decoder is the unit that controls the operation of the whole chip.

On the positive edge of the clock signal CLK the instruction to the chip is read from the instruction port I and executed. The three most significant bits make up the instruction and the rest of the word is data. The instruction set for the chip consists of instructions to select which row to operate on, which column, which switches to open or close, and of course a no operation (NOP). Since most switches in the chip need to work in a non-overlapping way, that is they must open faster than they close, a change in the status of a switch is converted into a non-overlapping control signal that actually controls the switch. See Section 6.2 and 6.5 for further details.

3.2 Pixel Readout

A more detailed schematic of the readout chain, from light to the differential output voltage VOU T, can be seen in Figure 3.2. The four corner-pixels, of the pixel array,

have been drawn with their row and column addresses labelled beneath them. The bias current ICOLis generated by the current source to the right and then mirrored

to the bias transistors connected to VCOL0· · · VCOL191. Those transistors serve as

active loads for the source follower transistors in the row of pixels that is currently addressed. Further below are the left and right column of the CDS/AS unit. Each column consists of an SC circuit that produces the difference between the reset and signal value of the addressed pixel in that column. This SC circuit is offset compensated and can also be operated to perform binning (see Section 1.2.4). The signals that control the switches of the SC circuit are not drawn, to avoid cluttering the schematic, instead Section 5.1 should be consulted. The outputs from the CDS/AS unit are multiplexed, thus, the output of the currently addressed column is amplified by the unit gain Output Buffer to produce VOU T that can be

measured at the output pins of the chip. Even though this is a schematic view, of the analog part of the chip, it corresponds quite well to the physical layout. Thus, row 0 and column 0 of the pixel array are found in the upper left corner of the pixel array in the layout too.

1_{It would actually be necessary to use a package, for the chip, with more than 384 pins since}

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+ − VRST 127 VSHT 127 VP ON 127 VRST 0 VSHT 0 VP ON 0 VCOL0 VCOL191 ICOL . . . ... pixel(0, 0) pixel(127, 0) pixel(127, 191) pixel(0, 191) CDS/AS(0) CDS/AS(191) Output Multiplexer VOU T “column address” Output Buffer

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3.3. Instruction Set 19 To fully understand how the sensor operates the example programs in Sec-tion 3.4 should be consulted. However, a simplified timing diagram showing DS, with the use of the shutter (solid line) or without (dashed line), can be studied in Figure 3.3. This diagram shows the events after the row address has changed to row address m.2 _{The integration time ends when V}

RST goes high or if the shutter is

used when the shutter goes low (not shown in this timing diagram). At t = 125 ns the signal value at VCOL is sampled by the CCD/AS unit and at t = 250 ns the

reset value. The difference between them is available at the output of the CCD/AS unit at t = 375 ns. [V] [ns] VOU T n VCOLn VP ON m VSHT m VRST m 0 125 250 375 0.8 1.0 1.8 3.3 5.0 5.0

Figure 3.3: Timing diagram.

3.3 Instruction Set

The following instructions are available: NOP, SETR, SETC, and SETS. How the instructions are coded can be seen in Figure 3.4, 3.5, 3.6, and 3.7. The instruction word, with the individual bits called b0 − b15, is 16 bits wide. b15 is the Most Significant Bit (MSB) and b0 the Least Significant Bit (LSB). The three most significant bits are interpreted as the opcode and the rest of the instruction word as data. An ‘X’ indicates don’t care, ‘1’ a logical one, and ‘0’ a logical zero. There are only four instructions so two bits should have been sufficient to code all opcodes. However, only one bit was used to code the opcode SETS.

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3.3.1 NOP

The instruction NOP coded as in Figure 3.4 does not change the internal state of the sensor. The primary use for this instruction is to enforce delays in the program, fed to the sensor.

b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 0 0 X X X X X X X X X X X X X X

Figure 3.4: NOP.

3.3.2 SETR

The instruction SETR coded as in Figure 3.5 changes the state of the Row Multiplexer to enable the row given by the argument Row Address. This argument can take all values between 0 − 255 but only the addresses between 0 − 127 are occupied by the sensor. Any other address will enable no row at all.

b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 0 1 0 X X X X X Row Address

Figure 3.5: SETR.

3.3.3 SETC

The instruction SETC coded as in Figure 3.6 changes the state of the Output Multiplexer to enable the column given by the argument Column Address. This argument can take all values between 0 − 255 but only the addresses between 0 − 191 are occupied by the sensor. Any other address will enable no column at all.

b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 0 1 1 X X X X X Column Address

Figure 3.6: SETC.

3.3.4 SETS

The instruction SETS coded as in Figure 3.7 changes the state of the switches used in the pixel and readout circuits. The symbolic names of the switches and their position in the instruction word can be seen in Table 3.1.

3.4 Example Programs

This section shows a few example programs to illustrate how readout can be carried out. The syntax of the pseudo-code is C-like and it is assumed that the function cmd() sends a numerical argument to the instruction port I of the sensor. There

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3.4. Example Programs 21 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 1 S14 S13 S12 S11 S10 S9 S8 S7 S6 S5 S4 S3 S2 S1 S0 Figure 3.7: SETS. Switches 0 − 7 Switches 8 − 14 S0 SCM F _SAM P LE S8 SBU S_RST

S1 SCM F _ADJU ST S9 SEXT _REF

S2 SCDS_RST S10 SP IX_P ON

S3 SCDS_IN T S11 SP IX_SHT

S4 SCDS_ACM GN D S12 SP IX_RST

S5 SCDS_EV AL S13 SGLOBAL

S6 SEXT _SIG S14 SP AD_RST

S7 SBU S_SIG

Table 3.1: The symbolic names of the switches.

are no NOPs in the code, in order to make it shorter. This will probably be needed in a real application depending on the frequency of CLK in Figure 3.1. One thing to remember, when studying the programs, is that the switches controlled by the flags in Table 3.1 turn off faster than on. Thus, a flag changing from 1 → 0 will take place before another flag changing from 0 → 1.

3.4.1 Rolling Shutter DS

The integration time3 _{is given by the time it takes to readout offset number of}

rows. If the integration time requires an offset value larger than NO_OF_ROWS a timer need to be used. This is not illustrated in the code and the code only captures one image in order to make it easier to read.

1 #define NO_OF_ROWS 128 2 #define NO_OF_COLS 192 3

4 for(i=0; i<NO_OF_ROWS; i++)

5 {

6 // Reset row i + offset

7 cmd(SETR|((i+offset) & (NO_OF_ROWS-1)));

15 // Readout all columns 16 for(j=0; j=<NO_OF_COLS; j++)

17 {

18 // Increment column and measure the output buffer value 3_{Photons are collected during this time.}

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19 cmd(SETC|j);

20 }

21 // Measure offset voltage of output buffer

23 }

3.4.2 Row By Row CDS

In this example a true CDS4_{is performed without using the shutter. Thus, a rolling}

shutter readout is not possible.5 _{Instead a row by row readout is carried out, that}

is, the reset value is stored at the CCD/AS unit during the entire integration time.

5 {

6 // Reset row i 7 cmd(SETR|i);

10 delay(TINT); // Wait for TINT us

13 for(j=0; j=<NO_OF_COLS; j++)

14 {

15 // Increment column and measure the output buffer value 16 cmd(SETC|j);

17 }

20 }

3.4.3 Rolling Shutter CDS

In this example a true CDS is performed with the faster readout of rolling shutter. This requires the use of the shutter switch. The reset value is stored in the pixel by the code at line 10.

5 {

4_{The reset value used in the CDS is the reset value that started the integration before the}

signal value was read.

5_{If the reset value is stored at the CDS/AS unit it will be occupied until after the integration}

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18 {

21 }

24 }

3.4.4 Snapshot Operation DS

This example shows how the snapshot operation works. First the entire sensor is reset and the integration starts at the same time for all pixels. After the integration time has passed the signal values are stored in every pixel. Following that the readout of the image can take place. Line 18 of the code listing might seem to be unnecessary but its purpose is to compensate for the clock feedthrough of the shutter. This will probably improve the FPN figures.

4 // Integrate light

5 cmd(SETR|0); // The pixel bus need to be driven

8 delay(TINT); // Wait for TINT us

11 // Readout the image 12 for(i=0; i<NO_OF_ROWS; i++)

13 { 14 // Readout row 15 cmd(SETR|i); 16 cmd(SETS|SPIX_PON|SCDS_AGND|SCDS_RST|SBUS_SIG|SCMF_SAMPLE); 17 cmd(SETS|SPIX_RST|SPIX_SHT|SPIX_PON|SCDS_AGND|SCDS_RST|SBUS_RST|SCMF_SAMPLE); 18 cmd(SETS|SPIX_SHT|SPIX_PON|SCDS_AGND|SCDS_RST|SBUS_RST|SCMF_SAMPLE); 19 cmd(SETS|SPIX_PON|SCDS_AGND|SCDS_RST|SBUS_RST|SCMF_SAMPLE); 20 cmd(SETS|SPIX_PON|SCDS_EVAL|SCDS_INT|SCMF_ADJUST);

23 {

26 }

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3.4.5 Ambient Light Suppression

This code shows an application that uses a pulsed laser to suppress low-frequency ambient light. Due to non-linearities in the pixel diode capacitance the ambient light will not be completely removed but substantially suppressed. The application works according to this:

1. Reset the entire sensor, turn on the laser, and start to integrate light. 2. After the integration time T1 has passed turn off the shutter switch.

3. Turn off the laser, reset the sensor, and do a rolling shutter readout with the integration time T2 where first the stored value is readout and then the

combined value obtained by turning on the shutter.

With T2 chosen according to equation 3.1, where CD is the effective diode

capaci-tance and CS the effective value of the sampling capacitor, the ambient light can

be almost cancelled.

T2 =

CD

CD + CS

T1 (3.1)

The output is then proportional to the diode current induced by the laser IDl and

given by equation 3.2, thus, the efficiency is somewhat reduced since the term

CD

CD+CS is less than one.

VOU T = IDlTl CD+ CS CD CD+ CS (3.2) 1 #define NO_OF_ROWS 128 2 #define NO_OF_COLS 192 3 4 // Integrate light

5 laser(ON); // Turn on the laser

6 cmd(SETR|0); // The pixel bus need to be driven

9 delay(T1); // Wait for T1 s

12

14 {

26 {

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3.4. Example Programs 25

28 cmd(SETC|j);

29 }

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CHAPTER 4 The Pixel Array

This chapter describes the design of the pixel array and various topics related to the pixel. Topics such as the photo diode, clock feedthrough, noise and so forth.

4.1 Overview

A schematic of the pixel can be seen in Figure 4.1. This schematic is the same for all six types of active pixels since the only difference between them is in the way the photo diode D1 and the sample capacitor CS have been implemented.

Transistor MN1 is the reset transistor that is used to charge the node VD to 3.3 V,

MN1 MN2 MN3 MN4 MN5 D1 CS CCOL VRST VSHT VP ON VB VRST VD VCOL

Figure 4.1: Schematic of the active pixel.

the voltage of the power supply. MN2 is the shutter transistor that together with

the capacitor CS implement the snapshot functionality. MN3 operates as a source

follower together with the bias transistor MN5. MN4selects which pixel to connect

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to the node VCOLthat is common for an entire column of pixels. The signals VRST,

VSHT, and VP ON are logical signals, common for an entire row of pixels, and are

affected by the flags SP IX_RST, SP IX_SHT, and SP IX_P ON set by the instruction

SETS (see Section 3.3.4) if the current row is selected by the row address set by the instruction SETR (see Section 3.3.2). If the flag SGLOBAL is set all rows of

VRST and VSHT are affected by SP IX_RST and SP IX_SHT regardless if the row

is addressed or not. There is also a memory function in each row for VSHT that

holds the previously set value if the row is not addressed and SGLOBAL is low.

The pixel operates in the following manner:

• Reset: The photo diode voltage VD is reset to a high value by the reset

transistor MN1. To achieve a larger signal swing for VD the voltage VRST

is higher than the supply voltage (5 V instead of 3.3 V), thus, the voltage of VD will become very close to VDD after the reset. The shutter switch MN2

and the select switch MN4 are closed (VSHT is held at the same high voltage

as VRST and VP ON at 3.3 V). This is because the diffusion between MN4

and MN3 and the diffusion of MN2 connected to the gate of MN3 need to be

charged to known repeatable values before the integration of light. Otherwise parasitic capacitances will affect the readout values in a way that differs from pixel to pixel, thus, giving rise to noise.

• Integration: VRST is held at a low potential,1 while the light is integrated

on the photo diode, during the integration time TIN T. The diode current

iD consists of the dark current iDC (which is the current from the cathode

to the anode when the photo diode is not subjected to any light) and the optically generated current iOP T. The total current is given by iD = iDC+

iOP T. This diode current iD will give rise to a change in charge ∆Q, at the

cathode of the photo diode, and via the total capacitance seen at this node the voltage changes by ∆V . The state of VSHT and VP ON does not matter

during integration.

• Readout: When VP ON is held high (3.3 V) the voltage at VCOL will follow

the voltage at the gate of transistor MN3. If this voltage is the reset value

VDD the voltage at the node VCOL will be referred to as VR. And if the

voltage at the gate MN3 is the voltage after integration the resulting voltage

at VCOL will be referred to as VS. VCOL is connected to the CDS/AS unit

that will produce the result VR− VS that is proportional to the average

irradiance of the light the pixel was subjected to during the integration time TIN T.

4.1.1 Hard or Soft Reset

If the reset transistor MN1 remains in the saturated or triode region during the

entire reset period (VRST > VDD+VT) it is referred to as a hard reset. The benefits

of hard reset are: fast settling time, large voltage swing for VD, and no image lag.2

1_{Not 0 V but rather ≈ 2 V to avoid blooming see Section 4.2.5.} 2_{When the pattern of an image is visible in the next image read out.}

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4.1. Overview 29 The drawbacks, on the other hand, are that it requires a gate voltage larger than the power supply and results in more temporal noise than soft reset.

If the high value of the reset signal VRST is not large enough transistor MN1

will enter the subthreshold region3 _{and the final value of V}

D becomes strongly

dependent on the length of the reset period. How large part of the reset period that the reset transistor operates in the subthreshold region depends on the start value of VD. Thus, the final value of VD depends on the initial value of the same.

This results in one of the drawbacks of soft reset namely image lag. The other two are a low voltage swing of VD and that a very long reset period is required,

compared to hard reset. The benefits, on the other hand, are that no level shifting is needed for VRST and that temporal noise is at least a factor 2 less than for hard

reset [31]. The latter is because the settling time of VD is typically in the order of

several ms, whereas, the reset period is normally not longer than a few µs , with soft reset. An analysis, in the time domain, when steady state is not assumed gives the result. If no measures against image lag is taken correlation between the reset levels at different instants in time will also play a part.

For IVP soft reset is not an option since in a typical application a binary image4

generated with very short integration time is used. Thus, the readout must be very fast. Because of this IVP custom, hard reset has been used for MPW00.1 too.

4.1.2 DS or CDS

The difference between DS and CDS is which reset value that is used when VR−VS

is calculated. In CDS the reset value is the same as the reset value that started the integration. Thus, if only the temporal noise voltage from the reset transistor MN1 is considered CDS would, theoretically, remove it completely. However, with

DS a new reset is made to generate the reset value for the CDS/AS unit. This reset value is not correlated with the reset value that started the integration so the temporal reset noise voltage would become qV2

Rnoise1+ VRnoise22 . The main

reason for using DS/CDS is to reduce FPN and in that aspect there is no difference between DS or CDS they are equally effective.

However, CDS has one major drawback. For a pixel without a shutter it is not possible to perform a rolling shutter readout since when the reset value is stored at the CDS/AS the pixel bus is occupied during the entire integration time (often many ms) instead of the readout time (250 ns with an 8 MHz instruction clock). As indicated by the program in Section 3.4.3 there is a possibility to perform CDS and still use rolling shutter readout. However, the thermal noise will probably become somewhat higher than for the row by row CDS in Section 3.4.2. This increase is because the noise sampled in the pixel is not bandwidth limited by the source follower MN3 as would be the case when the noise is sampled at the

CDS/AS unit.

3_{A MOS transistor conducts small currents between drain and source even if V}

GS< VT and

the transition between the saturated and cutoff region is not distinct.

4_{A binary image is produced by comparing the image to a given threshold and assigning a}

logical one to all pixels that are equal to or greater than the threshold value and a logical zero to the rest of the pixels.

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4.1.3 Pitch

The term pitch in an APS is associated with the distance between two adjacent pixels. Since the pixels are squares the pitch is the same in both the ˆx and ˆy direction. Pitch is an important parameter that determines Fill Factor (FF) (see Section 4.1.4), Signal to Noise Ratio (S/N) (see Section 4.6), and the total number of pixels in the sensor.

The number of pixels in a sensor depends on the area of the same, which in turn is limited by the optics used (and of course the maximum size of the die). For the sensor designed in this thesis (MPW00.1) two alternatives are at hand 100

or 2/300 _{optics. This means that the lenses focus the light on the area of a circle}

with a maximum diameter of 1 inch or 2/3 inch.5 _{How this relates to the sensor}

area can be seen in Figure 4.2 where the area of the sensor is grey.

ˆ y ˆ x Sensor 100 or 2/300

Figure 4.2: Sensor area vs maximal image.

Since the resolution of MPW00.1 is 128×192 pixels the pitch can be quite large without being limited by lenses. This would not be a realistic pitch to use, for a commercial sensor, so how the pitch limits the number of pixels is calculated for a larger sensor and shown in Figure 4.3. The graphs show the number of pixels in the ˆx direction vs Pitch for 100 and 2/300 _{optics when the sensor is squared}

and when it is limited in the ˆy direction to 512 rows.6 _{MPW00.1 has a pitch of}

14 µm, which would give a maximum resolution of approximately 1282 × 1282 or 512 × 1740 for 100 _{optics and 855 × 855 or 512 × 1095 for 2/3}00 _optics.

There is also a lower bound put upon how small the pitch can be. This is decided by the resolution of the optics used and the required sensitivity and S/N of the sensor.

5_{The definition is somewhat different but this is approximately true. Furthermore, an inch is}

25_{.4 mm.}

6

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4.1. Overview 31 512 and 100 and 100 512 and 2/300 and 2/300 500 1000 1500 2000 2500 3000 3500 4000 4500 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 P ix el s (ˆx ) Pitch [µm]

Figure 4.3: Number of pixels in ˆx direction vs pitch.

4.1.4 Fill Factor

Fill Factor (FF) is defined as As/Atot where As is the light sensitive area of the

pixel and Atot is the total area of the pixel. The light sensitive area is calculated

by removing the area that is covered by metal and diffusions, not connected to the cathode of the diode. Calculations like this will become somewhat approximate since:

• Reflections in different layer boundaries can make light end up in the light sensitive area even though it first hit metal that is opaque.

• Diffusions do not collect all incident light. • Poly is opaque for short wavelengths.7

A large FF is desired since the light sensitivity of the sensor increases with an increase in FF.

Even though the pitch 14 µm was decided by IVP, and not a variable in the implementation of MPW00.1, it is still interesting to see how FF varies with the pitch. A test layout shows that the FF for a pitch of 14 µm is about 63 % for a pixel with the sampling capacitor (CS see Figure 4.1) implemented by metal.

Assuming that the non-light sensitive area is the same regardless of pitch8 _and

that only the wire area changes. FF as a function of pitch is given by Figure 4.4.

7_{If silicidation of the gates are used poly is probably opaque for longer wavelengths too.} 8_{Not entirely true for small values of the pitch since the transistors cannot be drawn in the}

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10 20 30 40 50 60 70 80 90 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 F F [% ] Pitch [µm] Figure 4.4: FF vs Pitch. 4.1.5 Transistor Sizes

The following guidelines are used to size the transistors in Figure 4.1:

• Do not make the transistors in the pixel (MN1to MN4) larger than necessary

since it affects FF.

• MN1 and MN2 should be minimum size in order to minimise channel-charge

injection (CCI) and clock feedthrough (CFT) (see Section 4.3.1). To use larger sizes or dummy transistors only make the matching between pixels worse. Since both CS and the capacitance of D1 are rather small there is no

need, from a speed point of view, to increase the transistor sizes.

• MN4 operates as a switch and should have minimum length L4 to minimise

rds4. Furthermore, since the minimum size of an NDIFF contact is wider

than the minimum transistor width the space occupied by MN4 is minimised

by making the width of MN4 W4 equal to the width of the NDIFF contact.

To increase the width further does decrease rds4but it is much more effective

to increase the width of MN3 to improve the speed of the source follower.

• To determine the sizes of MN3 and MN5 the bias current ICOL= ID5 should

first be decided. However, if MN4 is treated as an ideal switch and with the

aid of equation 2.4 the expression in equation 4.1 can be derived. VCS− VCOL=r W5

L5

/W3 L3

(53)

4.1. Overview 33 VB − VT 5 should be in the order of or larger than 0.3 V to obtain good

matching between the bias currents in the different columns [5]. To get a large output swing of the source follower equation 4.1 suggests that W3

L3 >

W5

L5.

This could be difficult to obtain but as a rule of thumb W3

L3 should at least

be as great as W5

L5.

• The bias current ICOL is determined from the time it takes to discharge the

node VCOL from the reset value VR to the maximum signal value VSmax.9

According to the specifications this should be less than 125 ns (8 MHz). As-suming that ICOL and the capacitive load CCOL are constant during the

discharge ICOL is given by equation 4.2.

ICOL=

CCOL(VR− VSmax)

T (4.2)

How large the difference between VR− VSmax can be depends on the current

ICOL. However, simulations show that the voltage swing is at least 1 V so

this value is used in calculations. CCOLis given by equation 4.3 where CM ET

is the extracted capacitance per pixel seen from the pixel wire, CDef f is the

effective diode capacitance calculated according to Section A.2, and N is the number of rows in the pixel array.

CCOL= N (CM ET + CDef f) (4.3)

The time it takes to discharge the pixel column bus as a function of the column current ICOLis shown in Figure 4.5. This has been calculated with

8 9 10 11 12 13 14 15 16 17 18 19 20 21 80 90 100 110 120 130 140 150 9 14 20 µm ICOL [µA] T [n s]

Figure 4.5: ICOLvs T for 512 rows.

9_{When V}

Implementation of an Active Pixel Sensor with Shutter and Analog Summing in a 0.35um Process

Implementation of an Active Pixel

Sensor with Shutter and Analog

Summing in a 0.35 µm Process

Robert Johansson

Implementation of an Active Pixel

Sensor with Shutter and Analog

Summing in a 0

.35 µm Process

Robert Johansson

Institutionen för Systemteknik

581 83 LINKÖPING

Abstract

Acknowledgement

Abbreviations

Table of Contents

List of Figures

List of Tables

CHAPTER 1

Introduction

1.1

Definition and Goal

1.2

Background

1.3

Reading Instructions

CHAPTER 2

Basic Theory

2.1

The MOS Transistor

2.2

Small Signal Models

2.3

Noise

CHAPTER 3

Overview of the Chip

3.1

Building Blocks

3.2

Pixel Readout

3.3

Instruction Set

3.4

Example Programs

CHAPTER 4

The Pixel Array

4.1

Overview