Applications of Si1

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monolithic 3D integration

KONSTANTINOS GARIDIS

Doctoral Thesis in Information and Communication Technology School of Electrical Engineering and Computer Science

KTH Royal Institute of Technology Stockholm, Sweden 2020

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TRITA-EECS-AVL-2020:5 ISBN 978-91-7873-465-8

KTH School of Electrical Engineering and Computer Science SE-164 40 Kista SWEDEN

Akademisk avhandling som med tillstånd av Kungliga Tekniska Högskolan fram- lägges till offentlig granskning för avläggande av doktorsexamen i informations- och kommunikationsteknologi fredagen den 3:e april 2020 kl. 13:00 i Sal C, Electrum, Kungliga Tekniska Högskolan, Kistagången 16, Kista.

Thesis for the degree of Doctor of Philosophy in Electrical Engineering and Com- puter Science at KTH Royal Institute of Technology, Stockholm, Sweden.

Tryck: Universitetsservice US AB

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As the semiconductor industry moves beyond the 10 nm node, power consumption constraints and reduction of the negative impact of parasitic elements become important. Silicon germanium (Si1−xGex) alloys have been used to amplify the performance of Si based devices and integrated circuits (ICs) for decades. Selective epitaxial growth of heavily doped Si and/or Si1−xGex is commonly employed to reduce the effect of parasitic resistance.

Reducing the supply voltage leads to lower dynamic power consumption in complementary metal-oxide-semiconductor (CMOS) technology. Monolithic three-dimensional integration (M3D) is a technology that employs vertical stacking of the device tiers. This approach reduces the wiring length, effec- tively reducing interconnect delay, load capacitance and ultimately reducing the power consumption. Among the integration challenges M3D is facing, one can distinguish the available thermal budget for fabrication, the crystalline quality of the device active layer and finally the actual device or circuit performance.

Germanium channel devices can benefit M3D integration. Germanium metal-oxide-semiconductor field-effect transistors (MOSFETs) can be fabricated at significantly lower temperatures than Si. In addition, they potentially can have higher performance compared to Si due to the superior electron and hole mobilities of Ge. Active layer transfer of crystalline quality layers is a key step in a M3D fabrication flow. Direct wafer bonding techniques offer the possibility to transfer a Ge layer on a patterned wafer.

This thesis studies the various applications of Si1−xGex films in M3D.

An initial implementation of an in situ doped Si1−xGex film on silicon-on- insulator and germanium substrates is first presented. A Si1−xGex film is grown selectively on silicon-on-insulator (SOI) substrates to be used as a con- tact electrode on Si nanowire biosensors. On Ge bulk substrates, in situ doped Si1−xGex is epitaxially grown to form p⁺/n junctions. The junction leakage current and the mechanisms at play are studied. The analysis of the junction performance provides insights on the junction leakage mecha- nisms, an important issue for the implementation of in situ doped Si1−xGex

in M3D. A low temperature germanium-on-insulator (GOI) fabrication flow based on room temperature wafer bonding and etch back is presented in this work. The method suggested in the thesis produces high quality, crystalline Ge device layers with excellent uniformity. The thesis also reports on the development and integration of Si1−xGex in the GOI fabrication as an etch stop layer, enabling the stability of the layer transfer process. Finally this thesis presents Ge p-channel field-effect transistor (PFET) devices fabricated on the previously developed GOI substrates.

The technologies presented in this thesis can be integrated in large scale Ge device fabrication flow. The low temperature GOI and Ge PFET fabrication methods are very well suited for sequential device fabrication. The processes and applications presented in this thesis meet the current thermal budget, device performance and active layer transfer demands for M3D technology.

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Keywords: Silicon, germanium, epitaxy, selective, pn junction, germanium on insulator, GOI, Ge PFET, bonding, monolithic, sequential, three dimensional, 3D, low temperature

Konstantinos Garidis, garidis@kth.se Department of Electronics

School of Electrical Engineering and Computer Science KTH Royal Institute of Technology, SE-164 40 Kista, Sweden

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Allt eftersom halvledarindustrin rör sig bortom 10 nm teknologin blir ef- fektförbrukning och minskning av den negativa inverkan av parastiska element allt mer betydande. Kisel germanium (Si1−xGex) har i årtionden använts för att förbättra prestandan hos Si baserade komponenter och integrerade kret- sar (IC). Selektiv epitaxiel tillväxt av högdopat Si och/eller Si1-xGex är ofta använt för att reducera inverkan av parasit resistanser. Genom att reducera matningsspänningen minskas den dynamiska effekt konsumtionen effektivt i komplementär metall-oxid-halvledare (CMOS) tekonologi. Ett lovande till- vägagångssätt för att hantera detta är monolitisk 3 dimensionell integration (M3D), en teknologi som vertikalt staplar komponenter i skikt. Bland integ- rationsutmaningarna som M3D ställs inför kan man urskilja den tillgängliga termiska budgeten, kristallina kvaliteten av komponentens aktiva lager och slutligen den faktiska komponentens eller kretsens prestanda.

Germaniumkanals transistorer kan möjligöra M3D integration. Germani- um metall-oxid-halvledar fälteffekttransistorer (MOSFETs) kan tillverkas vid betydligt lägre temperaturer än de gjorda av kisel. Dessutom kan de porenti- ellt ha prestanda jämfört med kisel tack vare högre elektron och hål mobilitet i Ge. Realisering av det aktiva lagret med kristallin kvalitet är centralt i M3D tillverkning. Direkt skivbondning är ett möjligt sätt att överföra Ge lager till mönstrade skivor.

Denna avhandling undersöker möjliga applikationerna av Si1−xGex fil- mer i M3D. En första implementation av en in situ dopad Si1−xGex film på kisel-på-isolator (SOI) och germanium substrat demonstreras. Si1−xGex fil- men växtes selektivt på mönstrade SOI skivor för att användas som kontakte- lektrod på Si nanotråds biosensorer. På Ge bulk skivor växtes in situ dopade Si1−xGex epitaxielt för att bilda p⁺/n övergångar. p⁺/n övergångens läck- ström undersöktes. Analysen av pn-övergångens prestanda bidrar med insikt för implementationen av in situ doped Si1−xGex i M3D. En lågtemperatur process för germanium-på-isolator (GOI) tillverkning baserad på rumstempe- ratur skivbondning och baksidesetsning presenteras i detta arbete. Metoden som föreslås i avhandlingen ger högkvalitativa, kristallina Ge komponentlager med utmärkt uniformitet. Avhandlingen rapporterar om utvecklingen och integrationen av ett Si1−xGex ets stopp lager i GOI tillverkningen. Slutligen presenterar avhandlingen Ge p-kanals fälteffekttransistor (PFET) komponenter tillverkade på de tidigare utvecklade GOI substraten.

Teknologierna som presenteras i denna avhandling kan integreras i stor- skalig Ge och Si komponenttillverkning. Lågtemperatur GOI och Ge PFET tillverkningsmetoderna passar väl för sekventiell komponenttillverkning. Pro- cesserna och tillämpningarna som presenteras i avhandlingen adresserar ut- maningar med M3D integration så som låg termiska budget, komponentpre- standan och formering av kristallina aktiva komponentlager.

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Nyckelord:Kisel, germanium, epitaxi, selektiv, pn-övergång, germanium på isolator, GOI, Ge PFET, bonding, monolitisk, sekventiell, tre dimensionell, 3D, lågtemperarad

Konstantinos Garidis, garidis@kth.se Avdelningen för Elektronik

Skolan för Elektroteknik och Datavetenskap,

Kungliga Tekniska Högskolan, SE-164 40 Kista, Sverige

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List of Publications

This thesis is based on the following papers in peer-reviewed interna- tional journals and reviewed conference proceedings:

I. ”Silicon nanowires integrated with CMOS circuits for biosensing application”

G. Jayakumar, A. Asadollahi, P.-E. Hellström, K. Garidis, M. Östling, Solid State Electronics, vol.98, pp.26-13, 2014.

II. ”Fabrication and characterization of silicon nanowires using STL for biosensing applications”

G. Jayakumar, K. Garidis, P.-E. Hellström, M. Östling,

2014 15th International Conference on Ultimate Integration on Silicon (ULIS), pp.109-112, 2014.

III. ”Selective epitaxial growth of in situ doped SiGe on bulk Ge substrates for p+/n junction formation”

K. Garidis, A. Abedin, A. Asadollahi, P.-E. Hellström, M. Östling, under review.

IV. ”Epitaxial Growth of Ge Strain Relaxed Buffer on Si with Low Threading Dislocation Density”

A. Abedin, A. Asadollahi, K. Garidis, P.-E. Hellström, M. Östling, ECS Transactions, vol. 75, issue 8, pp. 615-621, 2016.

V. ”Characterization of bonding surface and electrical insulation properties of inter layer dielectrics for 3D monolithic integration”

K. Garidis, G. Jayakumar ; A. Asadollahi ; E. Dentoni Litta ; P.-E. Hell- ström ; M. Östling,

EUROSOI-ULIS 2015, 26-28 Jan. 2015. Oral presentation.

VI. ”Growth of epitaxial SiGe alloys as etch-stop layers in germanium-on-insulator fabrication”

K. Garidis, A. Abedin, A. Asadollahi, P.-E. Hellström, M. Östling, under review.

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VII. ”Germanium on Insulator Fabrication for Monolithic 3-D Integration”

A. Abedin, L. Zurauskaite, A. Asadollahi, K. Garidis, G. Jayakumar, B. G.

Malm, P.-E. Hellström, M. Östling,

IEEE Journal of the Electron Devices Society, vol. 6, pp. 588-593, 2018.

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The contribution of Konstantinos Garidis to each publication, major ( r r r), partial ( r r), or minor ( r):

Design Fabrication Characterization Analysis Writing

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The work has also been presented at the following reviewed international conferences:

VIII. ”Fabrication and characterization of silicon nanowires using STL for biosensing applications”

G. Jayakumar, K. Garidis, P.-E. Hellström, M. Östling, in 2014 15th Inter- national Conference on Ultimate Integration on Silicon (ULIS), pp. 109-112, 2014. Poster presentation.

IX. ”Silicon nanowires integrated in a fully depleted CMOS process for charge based biosensing”

G. Jayakumar, A. Asadollahi, P.-E. Hellström, K. Garidis, M. Östling, in 2013 14th International Conference on Ultimate Integration on Silicon (ULIS), pp. 81-84, 2013. Oral presentation.

X. ”GOI fabrication for monolithic 3D integration”

A. Abedin, L. Zurauskaite, A. Asadollahi, K. Garidis, G. Jayakumar, B.

G. Malm, P.-E. Hellström, M. Östling, in 2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), pp. 81-84, 2017. Oral presentation by the author of this thesis.

Other reviewed international conference papers by the author, not in- cluded in this thesis:

XI. ”IR-Photodetector Fabrication on Suspended Gesn Thin Layers”

A. Abedin, K. Garidis, P.-E. Hellström, M. Ostlingb in ECS Meeting, MA2018- 02 1023, 2018.

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1.1 The exponential rise of design and verification costs versus device scaling in time scale as well as technology node. . . 2 1.2 Schematic of monolithic 3D integration. The 2^nd active layer is trans-

ferred on top of the already existing device layer. The fabrication of the rest (n^th) device layers continues in the same manner . . . 6 2.1 Steps of a CVD process: (a) reactant transport, (b) reactant diffusion,

(c) surface reactions, (d) desorption and (e) evacuation . . . 11 2.2 Thickness comparison of p⁺-SiGe layer grown on Si. The thickness was

measured with step height (SH), spectroscopic ellipsometry (SE) and estimated by wafer weight (W). . . 15 2.3 Schematic of the device under test (a). Wafer scale I-V characteristics

of the 1x, 2x and 6x nanowire arrays. Drain current was set to VDS=0.1 V and -5 V<VBS<5 V. SEM images of the (b) single, (c) double and (d) sextuple nanowire arrays. . . 16 2.4 (a) SIMS profile of the B doped Si0.73Ge0.27grown on Ge SRB. (b) XRD

profile of the same layer. . . 18 2.5 (a) Growth rate and Ge content plotted against increasing B2H6 flow.

The GeH4 flow was kept stable and was used as a reference. (b) Layer resistivity with increasing B2H6 flow as extracted from thickness and four point probe measurements on blanket depositions. . . 21 2.6 SIMS analysis of a SiGe layer grown on Ge SRB with SiH4, GeH4 and

B2H6. The very high B concentration resulting in very low resistivity value is confirmed. The Ge content difference between SIMS and SE (red dash line) is attributed to the high B concentration. . . 21 2.7 (a) SEM image of one cycle of 60 s deposition and 10 s etch. (b) SEM

image of a different sample with two cycles of 60 s deposition and 10 s etch. . . 22 2.8 (a) 20x20 µm² AFM image of one cycle of SiGe grown on the dummy

gate of a SOI MOSFET. (b) SEM image of the same sample showing mostly selective growth. In blue dash circles are nucleations that were not etched during the HCl etch step. . . 24

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List of Figures vii

3.1 Graphical representation of the various leakage mechanisms . . . 28 3.2 (a) A sketch of the fabricated diodes. Contact was made directly to the

substrate from the chuck of the measurement unit. (b) I-V characteristics of the various shaped square diodes. . . 31 3.3 Area (bulk) and perimeter (surface) dependent diode leakage current for

Ge and Si substrates. In the insert the two main leakage mechanisms are graphically depicted. . . 32 3.4 TEM image showing an unsuccessful SEG on a 1 µm MOSFET. The

epitaxial growth took place from the top left and right sides of gate where the poly-Si gate electrode was exposed. . . 34 4.1 A schematic of the GOI fabrication process flow. Note that layer thick-

nesses are not in aspect ratio. First a Al2O3/Ge(25 nm)/SiGe(10 nm)/Ge(3 µm) stack is deposited on a Si wafer. Room temperature wafer bonding and thermal annealing at 350 °C follows. To reach the c-Ge active layer, a combination of dry and wet etching steps is applied to remove the Si, Ge and SiGe layers. . . 38 4.2 SEM images of the Ge SRB layers after iodine etching to reveal threading

dislocations. In (a) the first layer was grown at 400 °C and in (b) the first layer was grown at <300 °C. . . 39 4.3 Room temperature bonding of 100 mm wafers using Al2O3 and three

different oxides as the handle wafer bonding layer : (a) the reference sample of 100 nm thermal SiO2 grown at 1000 °C, (b) 18 nm SiO2

deposited by ALD at 350 °C and (c) 20 nm PECVD SiO2 deposited at 400 °C. In (d) the bonding quality between two ALD SiO2 surfaces is shown. Red circles emphasize the position and density of the voids created during the bonding process. . . 40 4.4 (a) Cross section of the epitaxial stack to test the selectivity after 80 s of

diluted SC-1. The Ge layers are recessed by approximately 400 nm while the Si0.5Ge0.5 layers remain intact. (b) Etching of Si0.5Ge0.5 in SC-1.

The thicknesses of the formed SiO2 (TSiO₂) and the etched Si0.5Ge0.5

(TSi_0.5Ge_0.5) are measured by spectroscopic ellipsometry. As TSiO₂ is increased the etch rate of Si0.5Ge0.5 becomes insignificant. . . 41 4.5 (a) A 10x10 µm² AFM image of the Ge active layer with RMS surface

roughness <0.5 nm. (b) Thickness of the Ge active layer on a 100 mm GOI wafer by spectroscopic ellipsometry (10 mm edge exclusion). The thickness of the c-Ge layer is 22.5 ± 2.5 nm. . . 42 5.1 (a) TEM image of a0.8 µm PFET on GOI. On the right is a close up

image of the gate stack, spacer and channel regions of the device. (b) IDVG characteristics of the 0.8 µm PFET device shown in Fig.5.1(a).

The SS was extracted at VD = -0.1 V. . . 46

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2.1 Summary of the results from the layer analysis of the SiGe growth on Si layers. . . 15 2.2 Thickness and RMS roughness results of the SiGe layer after one and

after two deposition-etch cycles. Thickness was measured with spectroscopic ellipsometry and roughness with AFM. . . 22 2.3 Summary of the results from the layer analysis of the SiGe growth on

Si layers. . . 23 3.1 Leakage current density comparison for 10⁴µm²p-n junction diodes on

Ge. The reverse current values were graphically extracted at 1V. Key:

B: Boron, I/I: ion implantation, LA:laser anneal, RTA: rapid thermal anneal . . . 33 4.1 RMS surface roughness, thickness uniformity and thermal budget for

each of the oxides in Fig.4.3. . . 39 5.1 Comparison of gate length (LG), channel thickness (tGe), EOT, sub-

threshold slope (SS) and long channel mobility (µh) of GOI MOSFETs. 47

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List of Acronyms

3D three dimensional

ALD atomic layer deposition

BOX buried oxide

CDE cyclic deposition-etch

CMOS complementary metal oxide semiconductor

CV capacitance-voltage

CVD chemical vapor deposition

CVE chemical vapor etch

DCS Dichlorosilane

FET field effect transistor

FDSOI fully depleted silicon on insulator

IV current-voltage

LPCVD low pressure chemical vapor deposition M3D monolithic three dimensional (integration)

MOS metal oxide semiconductor

MOSFET metal oxide semiconductor field effect transistor

NW nanowire

PECVD plasma enhanced chemical vapor deposition PVD physical vapor deposition

RIE reactive ion etching

RPCVD reduced pressure chemical vapor deposition

RTA rapid thermal anneal

SEG selective epitaxial growth SEM scanning electron microscope SIMS secondary ion mass spectroscopy

SOI silicon on insulator

SS subthreshold slope

STL sidewall transfer lithography TEM transmission electron microscope TMAH tetra-methyl-ammonium-hydroxide

ULK ultra low k

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Chapter 1

Introduction

This chapter offers a short introduction to the main concepts that this work fo- cuses on. Complementary metal-oxide-semiconductor (CMOS) scaling challenges and some examples from the implementation of silicon germanium films in current technology are outlined. The shift towards Ge devices is discussed and monolithic 3D (M3D) integration with Ge is introduced as a future CMOS alternative. The re- search objectives of this doctoral dissertation are presented as a part of M3D specific integration challenges. Finally, the chapter structure of this thesis is outlined.

1.1 CMOS technology and scaling

Geometrical scaling [1] of metal-oxide-semiconductor field effect transistors (MOS- FETs) has traditionally been the approach for meeting the speed, power and cost requirements dictated by the famous Moore’s law in 1965 [2]. The prediction of the biannual doubling of device density, as chip cost remains roughly the same, is the main reason for the concern of the so-called "end of the roadmap" era [3]. Already since 2013, an increase in cost-per-transistor was reported in industrial conferences [4].

Industrial fabrication of CMOS circuits requires significant financial investments into processes that become increasingly more complex [5]. This trend is graphically depicted in Fig 1.1. The more or less linear increase of transistors per chip that Moore predicted, is accompanied by an exponential increase in the cost per device (factoring in design and verification costs). The term "equivalent scaling" is commonly used to describe components that show the predicted performance leap, while straying from the physical geometrical transistor scaling path.

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Figure 1.1: The exponential rise of design and verification costs versus device scaling in time scale as well as technology node. Reproduced from [5].

Silicon germanium alloys in CMOS technology

Silicon germanium alloys have been widely used in CMOS fabrication: in [6] the authors report on a sensitivity current improvement on a dielectrically modulated tunnel FET based biosensor. A poly-SiGe capacitive pressure sensor is fabricated above a Cu back end CMOS readout circuit at a low temperature in [7]. Vertically stacked gate-all-around Si nanowire MOSFETs are reported in [8]. In this study, SiGe layers are used as fins and boron doped SiGe as PMOS source/drain termi- nals. A promising integration of a SiGe PIN photodetector in a Si photonics flow is reported in [9]. Selective epitaxy of in situ boron doped SiGe films has been succesfully integrated in sub 70 nm CMOS in [10], showing very low resistivity contacts and leakage current amongst other results. Epitaxially grown SiGe layers as stressors have been successfully implemented in high volume manufacturing [11].

Reduction of the threshold voltage by using SiGe layers for band gap engineering is also possible. In [12] SiGe channel PFET devices show excellent reliability for high performance and low power applications.

The theoretical background and applications of the epitaxial growth of these films can be found in 2.1, where the results of this part of the thesis work are discussed.

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1.2. MONOLITHIC 3D INTEGRATION 3

The re-emergence of Ge devices

In 1947 the first transistor was demonstrated in Bell Labs: the point-contact germanium transistor was based on polycrystalline Ge and was used as an amplifier for speech [13, 14, 15]. The need for higher mobility channel materials has been a continuous challenge for the industry [16, 17] and germanium is a promising candidate for this application. Compared to silicon, germanium has lower band gap and higher hole and electron mobility. Further mobility enhancements can be achieved by strained Ge layers as shown in [18]. In addition, low contact resistance of Ge with metals can be expected by Fermi-level pinning of the metal interface at low thermal budget. Lately, research interest has been increased for Ge based devices as an alternative to Si channel devices [19, 20].

Germanium-on-insulator (GOI) substrates can further enhance device performance [21, 22, 23]. GOI substrates can be fabricated by various methods. Ge condensation as reported by Nakaharai et al in [24] is a method based on the ox- idation of SiGe films epitaxially grown on a silicon-on insulator (SOI) substrate.

Liquid phase epitaxy (LPE) can also be used for GOI fabrication [25], by sputter- ing Ge followed by a rapid thermal anneal (RTA) slightly higher than germanium’s melting point and taking advantage of the cool down to initiate the low pressure epitaxy process. The SmartCut^{T M} proprietary technology by SOITEC [26, 27, 28]

involves a proess similar to the well known SOI fabrication. Another way to fab- ricate GOI substrates is the direct bonding [29, 30] and etch back approach. This is the approach used in this thesis. In this method a sacrificial wafer is used and SiGe acts as an etch stop layer. The quality of the Ge layer is often based on the growth of a thick (1 µm and above) Ge relaxed layer [31, 32].

The integration of in situ doped epitaxially grown p⁺-Si1−xGex on Ge is discussed in 2.3 and 3.2. Fabrication of a GOI substrate is discussed in Chapter 4.

The fabrication and characterization of a GOI PFET wiht source/drain contacts formed by ion implantation is presented in 5.

1.2 Monolithic 3D integration

When considering the geometrical device scaling, one thinks of the planar approach in fabrication that has been used so far. However, this is not the only path towards large scale CMOS manufacturing. A promising candidate for bypassing the design hurdles of geometrical scaling is monolithic 3D integration (M3D) [3, 33, 34].

Monolithic 3D integration¹ is a design and fabrication concept that involves stacking of active device layers on top of one another. This approach readily increases

1Also referred to as 3D sequential integration

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the device packing density. In contrast to 3D packaging, the devices are not fabricated separately and then bonded on top of each other, instead each device layer is fabricated on top of an already existing one. The latter also offer benefits in terms of RC delay and coupling capacitance, since the interconnect wiring length is significantly reduced.

The earliest work on M3D can be traced back to late 1980s - early 1990s [35, 36]

when epitaxial seeding from the bulk has been applied to grow transistors over existing transistor layers albeit without any inter tier interconnects. More current reports have shown the full potential of this technology [37, 38, 39, 30, 40, 41, 42]

and have revealed some of its challenges.

These challenges are summarized in a 2018 report by Vandooreen et al at IMEC [42]. They range from the thermal stability of the metal interconnects (sheet resistance increase and thermal stability is degraded at temperatures higher than 500

°C for Cu interconnects), to layer transfer (large scale layer transfer at a low temperature), and device specific fabrication such as gate stack (thermal stability of bottom tier and good interface at the upper tiers without high temperature anneal) and contact formation (dopant activation at temperatures lower than 600 °C).

From the point of view of this thesis, the integration issues M3D is facing can be grouped into the following categories:

• Junction formation: The use of ion implantation to meet the required dopant profiles in Ge MOSFETs is challenging due to crystalline defect gen- eration during implantation. For Ge devices, a relatively high active p-type doping concentration of ≈2·10²⁰ cm⁻³ has been reported [43] using boron ion implantation in spite of the low solid solubility of B in Ge. It is more challenging to achieve a high n-type doping concentration in Ge and using annealing temperatures around 600 °C commonly achieves an active doping concentration ≈1-5·10¹⁹cm⁻³[44] although recently n-type dopant activation above 10²⁰ cm⁻³ has been reported using short time and high temperature anneals [45].

• Thermal budget: This is the major challenge M3D is facing. The total available thermal budget is dictated by the bottom tiers. Recent research [46]

shows that even though bottom tier fully depleted SOI (FDSOI) CMOS is not degraded after 2 hours at 500 °C, NiPt silicidation can occur. Further- more, the stability of inter tier metal interconnects is affected. Cu/ultra-low-k (ULK) dielectrics can provide better thermal stability up to 550 °C compared to W/ULK [47]. There exists therefore a temperature region with an empiri- cal upper limit of 600 °C for M3D integration.

• Active layer transfer: The aim is to develop a process that transfers thin (<25 nm) high quality crystalline Ge device layers for the 2^ndand upper tiers shown in Fig. 1.2. The layer transfer has to be completed within the allowed

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1.3. SCOPE, OBJECTIVES AND ACHIEVEMENTS 5

600 °C thermal budget. In addition, the device layer should offer a good front and back (towards the tier below) interface with low trap density. The successful fabrication of a GOI wafer will pave the way for the layer transfer process for the upper tiers of M3D. It is also expected that the layer transfer process can qualify for large scale fabrication.

Monolithic 3D integration with Ge

Monolithic 3D integration can be benefited by the incorporation of Ge as the channel material for the 2^nd and upper device tiers. A simplified schematic is shown in Fig. 1.2. The advantages of Ge devices have been discussed in section 1.1. In addition to them, Ge has the potential to enable low temperature processing in the upper device tiers (T<600 °C). This will meet the thermal budget constraints that arise for the bottom device tiers that are already present.

The results presented in the following chapters have the potential of addressing these two challenges. The selective epitaxial growth of in situ doped SiGe layers in sections 2.3, 2.4 and 3.2 can be used for forming the source/drain contacts for the 2^nd and upper device levels. The active Ge channel on these device tiers can be transferred with the process developed in section 4.1.

Intel has recently reported on a Ge PMOS stacked on top of a Si NMOS to form an inverter [48]. This study was presented at the 65^th International Electron Devices Meeting (IEDM) 2019 in San Francisco, USA and attracted much attention [49, 50] even before its publication. The authors present a fabrication process very similar to the one presented in this thesis in chapters 4 and 5, implemented on 300 mm wafers. The adoption of this research direction by one of the leaders in manufacturing is an additional strong point in the argument for monolithic 3D integration.

1.3 Scope, objectives and achievements

This thesis deals at a great extend with the application of Si1−xGexalloys for M3D with Ge devices. From fabrication of germanium-on-insulator (GOI) substrates to the formation of source/drain junctions, Si1−xGex films developed in this work provide a basis for the successful implementation of Ge in a M3D process flow.

This section presents the results and methodology followed in this thesis in order to address the challenges discussed in the previous section:

• Junction formation: Using in situ doped Si1−xGexlayers, selectively grown on the S/D regions, the need for highly doped junctions can be met. The abil-

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Figure 1.2: Schematic of monolithic 3D integration. The 2^ndactive layer is transferred on top of the already existing device layer. The fabrication of the rest (n^th) device layers continues in the same manner

.

ity to grow these layers selectively further simplifies the fabrication process.

Thermal budget constraints can also be met when using in situ epitaxially grown SiGe layers. Growth at temperatures < 600 °C has already been reported [51] (and references therein), adding to the potential of this approach as a replacement to ion implantation. In this thesis an in situ doped p⁺- Si0.73Ge0.27 was epitaxially grown on Ge bulk wafers. The growth was selective towards SiO2.

Selective epitaxy of in situ doped Si1−xGex has been integrated in Si MOS- FETs as channel stressor or as complimentary to the ion implanted source and drain contacts [52]. In the same way it can be integrated in a Ge process flow as shown in chapters 3 and 4. In addition, if the Ge devices are fabricated on GOI, the junction leakage discussed in section 3.2 is expected to be reduced.

• Thermal budget: The work presented in this thesis aims to develop a fabri- cation process flow for Ge devices with 600 °C as the maximum temperature.

The devices presented in Chapter 5 were fabricated with this thermal budget.

These devices were fabricated on a GOI substrate, the fabrication of which is based on room temperature wafer bonding and etch back. The device process

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1.4. THESIS ORGANIZATION 7

flow discussed in Chapter 5 and the GOI fabrication of Chapter 4 are ready for implementation in a Ge based M3D process flow in terms of temperature limitations.

• Active layer transfer: The layer transfer method developed in this thesis is based on room temperature wafer bonding, followed by a 450 °C anneal and a well controlled etchback process. The bonding is achieved via Al2O3

to SiO2 surface bonding. The etchback process is possible via a 10 nm thin Si0.5Ge0.5 etch stop layer also developed in this thesis.

The results show that ALD SiO2 can be used as bonding surface with excellent bonding yield. The ALD temperature is within the thermal budget of monolithic 3D integration with Ge. Thermal SiO2 can also be used albeit only for the first device tier due to the high process temperature. ALD SiO2

can successfully substitute thermal SiO2 in the Ge layer transfer process on top of a device tier. The same procedure for layer transfer can be followed for second and upper tiers in M3D.

• Ge device fabrication: Using the GOI substrates fabricated in this thesis, Ge PFETs with Lg≥1 µm are fabricated and characterized. The devices exhibit a threshold voltage of 0.18 V and 60% higher mobility than the SOI PFET reference devices. The 70 % device yield shows that the process is very close to larger scale production.

All the fabrication was completed in Electrum laboratory in Kista. The work was funded by Stiftelsen för Strategisk Forskning (SSF) and was supported by MyFab - The Swedish Research Infrastructure for Micro and Nano Fabrication.

With a crude estimation of 2 year intervals, the following research milestones were achieved: (a) design of a Si CMOS process flow and implementation of selective epitaxy, (b) proof of concept GOI fabrication with wafer bonding and etch back, (c) Ge device fabrication and characterization.

1.4 Thesis Organization

This thesis is organized in seven chapters as follows:

Chapter 1introduces the motivation of the work in this thesis from the scope of monolithic 3D integration with Ge as a channel material. An outline of the aims and achievements of this thesis is also presented.

Chapter 2 provides an overview of the theoretical background concerning se- lective epitaxial growth. The initial results of the in situ doped SiGe layers are implemented on a nanowire array as contacts for a proof-of-concept bionsensor.

The films are then grown and characterized on Si and Ge using two approaches:

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(a) one step and (b) two step deposition and etch. The content of this chapter relates to Papers I, II and III.

Chapter 3 deals with the p⁺-n junction formation on Ge bulk. An analysis of the reverse current is conducted. The junction leakage data are compared to similarly sized diode structures from the literature. The content of this chapter relates to Paper III.

Chapter 4 is a summary of the GOI development. A detailed explanation of the GOI process flow is presented with results from Papers IV, V & VI.

Chapter 5 includes a detailed analysis of Ge PFETs fabricated on GOI. The Ge devices of this chapter are ion implanted PFETs fabriated on a 100 mm GOI wafer. These results are shown in Paper VII.

Chapter 6is the concluding chapter where the research highlights are summarized.

Chapter 7 provides a future outlook of the possible applications of Si1−xGex

layers, from a M3D and Ge devices point of view.

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Chapter 2

Selective epitaxial growth of Si _1−x Ge _x

This chapter deals with the selective growth of Si1−xGex alloys. An overview of the basic concepts behind epitaxial growth is given with emphasis on growth kinetics, in situ doping and approaches to achieve selectivity towards SiO2. Si1−xGex layers are grown on SOI substrates to form nanowire sensor arrays (Papers I & II). Then using the same alloy composition and growth, p-n junction diodes on bulk Ge are formed (Paper III).

2.1 Epitaxial growth of Si

1−x

Ge

x

Epitaxial growth is the method were a film is grown on a substrate following its crystal orientation. The substrate can be the same material as the grown film (homoepitaxy) or different (heteroepitaxy). Epitaxial growth by chemical vapor deposition (CVD) is a common process in CMOS manufacturing. In order to achieve good growth conditions, the surface of the substrate needs to be free of any type of contaminants. Any type of film or particle on the surface will affect the surface reactions and possibly create lattice defects. Basic requirements for a clean and epitaxy ready substrate are:

• Oxide free surface

• Etch damage free surface

• Particle/contamination free surface

The most common choice for a pre-epitaxy surface clean consists of an ex situ followed by in situ treatment. A detailed presentation of the various surface treat-

9

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ment solutions is given in [53]. The ex situ treatment for Si substrates involves a standard clean 1 (SC-1) or a Piranha (H2SO4:H2O2) followed by an aqueous hydrofluoric acid (HF) bath to remove the native oxide. The HF clean helps to hydrogen passivate the surface. Another popular approach substitutes the HF clean with a mix of HF, hydrocholoric acid (HCl) or isopropanol (IPA) diluted in deion- ized water (DIW) [54, 55]. A wet in situ clean can simplify the process. Dedicated wet cleaning stations or a cluster integrated chambers for wet in situ cleaning are already available [56]. Once the wet surface treatment procedure is complete, the substrate undergoes a hydrogen bake at 800 °C - 1000 °C for > 30 s in the reactor chamber.

In the case of Ge, the surface treatment needs to be modified. Standard surface clean procedures (SC-1, SC-2) contain H2O2which is a known Ge etchant. Ge oxide forms within seconds of air exposure. The water soluble GeO2can also decompose at 430 °C [57]. HF solutions can etch GeO2but fail to remove Ge sub oxides (GeOx, x<2). Hydrofluoric acid and HCl solutions have been demonstrated to remove Ge sub oxides [58, 59]. The Ge surface quality will play an additional role also in the formation of p-n junctions with epitaxial p- or n-SiGe layers. Dangling bonds at the interface betwewn Ge and SiGe will create interface states with densities ≈ 10¹² cm⁻²eV⁻¹ [60, 61]. Common techniques used for Si such as hydrogen passivation do not yield the same results in Ge [62]. An alternative to hydrogen is sulfur (S) and fluorine (F) passivation. Sulfur passivation is usually achieved in an aqueuous (NH4)2S solution [63, 64] while F passivation employs CF4plasma [65, 66].

Once the substrate surface is cleaned, the epitaxial growth process can begin.

Figure 2.1 is a graphical representation of the processes taking place during CVD epitaxy. At first the gas precursors¹ enter the reaction chamber along with the carrier gas. The latter is usually an inert gas such as hydrogen. The gases then diffuse to the surface of the substrate. Only a fraction of the gas flow that enters the chamber reaches the surface of the substrate. The kinetics of the gas flow above the substrate can be described by a boundary layer model that is created above the substrate [67]. This is especially true in the case of selective growth as will be explained later. The gas molecules that diffuse into this boundary layer can reach the surface where they adsorb, recombine into nuclei and eventually form the solid film. The energy needed to facilitate the chemical reactions on the surface is provided by the substrate temperature. The reaction byproducts are desorbed from the surface back to the main flow of the gases and then to the exhaust of the reactor chamber.

Common silicon precursors are SiH4, Si2H6, Si3H8, SiCl4, SiHCl3(TCS), SiH2Cl2

(DCS). Some of the earliest reports on SiGe growth [69, 70, 71] have been using some of the precursors listed above. Common germanium precursors are GeH4and Ge2H6. The growth rate of the deposition depends on precursor concentration, gas

1The precursors are not limited to gaseous form. Liquid preursors are also used for some production purposes although the majority of research and industrial production uses gas precursors.

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2.1. EPITAXIAL GROWTH OF SI1−xGEx 11

Figure 2.1: Steps of a CVD process: (a) reactant transport, (b) reactant diffusion, (c) surface reactions, (d) desorption and (e) evacuation. Reproduced from [68]

flow, temperature, pressure and even reactor geometry. The choice of precursor depends on the requirements for the film and is limited by process conditions. In general, chloride precursors tend to reduce the growth kinetics compared to hy- drides, when the growth conditions are similar. Another factor to consider is the deposition temperature as it can cause gas phase nucleation if the precursors decompose in the gas flow. As a result of this, the hydride precursors are preferred for low temperature (<600 °C) growth.

The Si1−xGexalloys have a lattice parameter that varies between that of the Si cyrstal (5.431 Å) and that of Ge (5.667 Å). This variation is dependent on the Ge content in the alloy, x:

αSi_1−xGe_xαSi+ x(αGe− αSi) (2.1) Incorporating Ge atoms in the lattice has direct effect to the growth kinetics.

Compared to pure Si epitaxial film growth, the growth rate of Si1−xGex alloys is drastically increased. However this still remains a function of the Ge content in the film. For low Ge content (xGe<0.1) and low temperatures (T<600 °C) the growth rate is proportional to the Ge content increase. The rate limiting mechanism is hydrogen desorption from the surface. Hydrogen desorption is favored from Ge sites than Si sites in Si1−xGexalloys, which leads to an increase in the growth rate with Ge content [72]. The Ge atoms on the surface of the growing film behave as desorption centers and the activation energy for hydrogen desorption is reduced.

Hydrogen desorption from Si sites has an activation energy of 47 kcal/mol [73]

compared to 37 kcal/mol for Ge [74]. For higher Ge contents this trend is reversed.

The growth kinetics are also different depending on the temperature regime the growth takes place. The increase in Ge content has another side effect: the more Ge at the surface, the harder it is for SiH4 and GeH4 to adsorb since the sticking coefficient is lower at Ge sites [75].

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The incorporation of Ge atoms in the lattice induces strain in the film. Si1−xGex

films grown on Si substrates exhibit biaxial compressive stress. The stress is a function of the film thickness (∝ t²SiGe). There exists a critical thickness up to which film quality does not degrade. Nucleations can lead to the propagation of misfit dislocations through the film. These dislocations are usually created at the Si1−xGex interface and facilitate the relaxation of the remaining film at the top.

The propagation of the lattice defects depends on the dislocation energy and the relaxation gain. When the energy of the dislocation is larger than the energy needed for relaxation, the film is defect free. The opposite occurs at a specific critical film thickness. For a Si∼80Ge∼20 this thickness is 20 nm. The unwanted effect of Stranski-Krastanov growth [76] can also occur and is a function of the deposition time and film thickness as well as the amount of strain in the film. A rule of thumb is to have an as large as possible Ge content-critical thickness window. In addition to the above, the Ge composition of the alloy alters its chemical properties which can affect the film’s etch behavior. This particular feature will be of use in the GOI fabrication development discussed in Chapter 4.4.

In situ doping of Si_1−xGe_x

In situ doping of SiGe epitaxial layers has been widely used in CMOS fabrication [11, 77]. Common dopant precursors are B2H6and PH3for boron and phosphorous doping respectively. The epitaxial process allows dopant atom incorporation during the film growth as substitutional sites. The dopants introduced in this way in the lattice are readily electrically active thus eliminating the need for an activation anneal.

The amount of Ge in Si1−xGex affects also the electrical properties of n⁺- or p⁺- doped films. It has been reported [78] that, for a B doped film, even a slight change in the Ge content from 0.83 to 0.88 will decrease the resistivity by 6 times.

In [79] Qi et al argue that there exists a limit in the B concentration that can be of benefit for device integration. They report a 3% increased ION/IOF F for a 7%

increase in Ge concentration and a 4% ION/IOF F increase for a 14% increase in Ge concentration as measured by secondary ion mass spectoscopy (SIMS). An increase in B2H6 flow has little to none effect in the growth rate [80, 81]. This is attributed to enhanced hydrogen desorption by the B atoms during film growth.

Phosphorous doped films behave differently with Ge content showing an increase in resistivity with increased Ge content. This is potentially attributed to the dopant segregation at the grain boundaries: B atoms do not diffuse to the grain boundaries [82] while P atoms tend to segregate more. The growth rate of P doped Si1−xGexis reduced with increased PH3flow [81]. This is effect is similar to Si:P doped epilayers and is attributed to surface poisoning at high phosphine flows. Meta and Tao in

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2.1. EPITAXIAL GROWTH OF SI1−xGEx 13

[83] propose a model that includes a "blocking factor" which takes into account PH3

decomposition to P2 and P4 at high flows.

Achieving selectivity during Si1−xGex growth

The term "selective" refers to the ability to achieve growth only on specific areas.

These areas are openings to the substrate while the rest of the surface is masked with another material. The material used to mask the substrate is usually an oxide or nitride. The selectivity can be achieved either during the growth by suppressing growth that takes place in non wanted parts but also after the growth by etching the (usually polycrystalline or amorphous) films that are formed on the masking material.

For the first case HCl or Cl based precursors are introduced in the gas chemistry.

A common choice for selective growth using a Cl based precursor for Si species is DCS [84]. An early report [85] on selective epitaxial growth of Si1−xGex explains the two-fold role of Cl. Chlorine acts as an etchant removing Si and Ge atoms that nucleate on the oxide (or nitride) mask surface. The efficiency of this etch is increased when higher Cl content is introduced in the chamber. A very increased Cl presence in the chamber can result in the epitaxial growth being suppressed on the substrate as well. In addition, Cl can increase the mobility of Si and Ge atoms which in turn helps atoms deposited on the mask to diffuse to the substrate openings. A balance should be achieved for the process to remain selective without heavily limiting the epitaxial growth on the areas of interest (or even stopping it with excess Cl etching). An increased HCl flow leads to increased activation energy and reduced growth rate [86]. In [87] the authors propose a mechanism that explains the reduced growth rate as the HCl flow is increased. Hydrogen desorption from the surface is gradually replaced by Cl or HCl desorption. In the same work, for heavily B doped Si1−xGex films, surface roughening is witnessed for high HCl flows.

The amount of Ge in the Si1−xGex is a function of the gas flows for DCS and GeH4. In [88] the following relation for the Ge composition x, germane (F(GeH4)) and DCS (F(DCS))flows is proposed:

x²/(1 − x) = n(F (GeH4)/F (DCS)) (2.2) where n is a constant that depends on the temperature and pressure conditions of the growth. The Ge content in the film affects also the growth rate. Increased hydrogen desorption due to the Ge atoms on the surface leads to an increased amount of free nucleation sites for incoming Si and Ge atoms. Therefore higher GeH4flows result in increased growth rate [81]. Growth selectivity also depends on

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the amount of Ge atoms with larger Ge content rendering the process more selective to oxides [89].

2.2 Si

_1−x

Ge

_x

growth on bulk Si

The epitaxial growth was done in an ASM Epsilon 2000 RPCVD reactor. The substrates were bulk n-Si and p-Si wafers (525 µm, ρ ≈ 20 − 40Ohm · cm). The surface of the wafers was treated prior to loading in the reactor (ex situ) and when in the reactor chamber (in situ). The layer growth parameters are:

• Surface treatment:

– Ex situ:

∗ H2SO4:H2O2 (3:1), 5 min

∗ Deionized water (DIW) rinse and dry

∗ 1% HF, 30 s

∗ Deionized water (DIW) rinse and dry – In situ:

∗ 800 °C bake, 10 min, H2ambient

• Epitaxy:

– Gas precursors: SiH2CL2 (60 sccm), GeH4 (10 sccm), B2H6 (80 sccm) – Temperature: 650 °C

– Pressure: 20 Torr

In Table 2.1 a summary of the results from the layer characterization is shown.

The surface roughness measurements were done in tapping mode atomic force mi- croscopy (AFM) on a 5x5 µm area. The resistivity was extracted from four point probe measurements and Van der Pauw structures. The doping concentration was determined by SIMS from Evans Analytical Group. The layer thickness was measured by spectroscopic ellipsometry and step height. The Ge content was determined by SIMS and it was found that it agrees well with the value given by spectroscopic ellipsometry.

In addition to step height and spectroscopic ellipsometry measurements for layer thickness, the wafers were weighed as well. Weighing the wafer pre and post epitaxial growth is not an accurate measurement method on its own. However, when benchmarked towards other more accurate methods it can be a useful tool for fast film thickness estimation. A comparison between these measurements is shown in Fig. 2.2.

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2.2. SI1−xGExGROWTH ON BULK SI 15

Layer property p⁺-SiGe n⁺-SiGe Surface roughness (nm) 2.4 2.7

Resistivity (mΩ·cm) 3.5 2.5

Doping concentration (cm⁻³) 8·10¹⁹ 10²⁰

Ge content (%) ≈27 ≈27

Table 2.1: Summary of the results from the layer analysis of the SiGe growth on Si layers.

Figure 2.2: Thickness comparison of p⁺-SiGe layer grown on Si. The thickness was measured with step height (SH), spectroscopic ellipsometry (SE) and estimated by wafer weight (W).

Si_1−xGe_x integration on SOI

The first application of the above layers was on Si nanowires fabricated on 100 mm SOI wafers. The nanowires have been fabricated with sidewall transfer lithography (STL). Also known as spacer patterning [90], STL is a method for fabricating linear features of arbitrary width² using i-line lithography. The fabrication process flow is explained in detail in Paper I.

Figure 2.3(a) shows the final structure after all the metal contacts are defined. In the same figure the measured drain current (IDS) at VDS=0.1 V for one (Fig.2.3(b)),

2Depending on process related factors such as: spacer deposition uniformity, thickness control, etch parameters.

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(a) (b)

(c) (d)

Figure 2.3: Schematic of the device under test (a). Wafer scale I-V characteristics of the 1x, 2x and 6x nanowire arrays. Drain current was set to VDS=0.1 V and -5 V<VBS<5 V. SEM images of the (b) single, (c) double and (d) sextuple nanowire arrays.

two (Fig.2.3(c)) and six (Fig.2.3(d)) nanowires as a function of the applied VBS

is shown. A first observation is related to the intended purpose of the nanowires.

Considering that the nanowires are to be used as biosensors, it is the subthreshold regime that is of importance. There, the sensitivity of silicon nanowire biosensors is highest [91]. Indeed, the ratio of IDS in on state (IDS>100 nA) over off state (IDS<1 pA) is more than 10⁵ which offers a wide range of IDS in the subthreshold region.

The devices show a uniform subthreshold slope of 75 mV/dec. The spread for the on voltage³, VON, is approximately 1-2 V for all three nanowire arrays. This is not related to the epitaxial growth but most probably to the fixed oxide charges in

3Defined as VBSat IDS=10⁻⁸A.

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2.3. SI1−xGExGROWTH ON GE BULK 17

the BOX. For an oxide charge density of 6·10¹²charges/cm²a shift of approximately 1 V is expected, assuming that all charges are located at the BOX/bulk Si interface.

The nanowire devices can be thought of as accumulation mode FETs with the buried oxide (BOX) being the gate oxide. At VBS<0 the Si nanowires are in accumulation, conducting current from drain to source. Increasing the VBS to positive values depletes the holes in the silicon nanowires which reduces IDS to

<1 pA for all the devices. The high ION/IOF F ratio indicates a low resistivity source/drain contact. No obvious leakage is seen from the source and drain areas of the nanowire. We can therefore assume a good junction quality between the Si nanowire and the epitaxially grown p⁺-Si0.75Ge0.25 with insignificant lekage and high ION.

2.3 Si

1−x

Ge

x

growth on Ge bulk

In this section growth on Ge susbtrates is discussed. The substrates are either Ge bulk wafers or in house grown 2 µm thick Ge strain relaxed buffer (SRB) [92]. The use of Ge SRB substrates is preferred for process development due to their reduced cost compared to Ge wafers and to the option of tailoring their properties (doped, undoped, thickness).

Growth using SiH₂CL₂

The growth of B doped Si1−xGex layers on Ge bulk substrates was largely based on the already developed layers of section 2.2. A key difference was the surface treatment: Ge surfaces require a different ex situ cleaning approach. Being an issue that affects not only the S/D contacts but the gate stack as well, there has been extensive research connected to surface passivation of Ge surfaces [58, 64, 93, 94, 95, 96, 97, 98]. For this work we applied a simple HF dip and rinse dry approach as an ex situ approach. The surface preparation and growth details are as follows:

– Ex situ:

∗ 1% HF, 30 s

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(a)

(b)

Figure 2.4: (a) SIMS profile of the B doped Si0.73Ge0.27 grown on Ge SRB. (b) XRD profile of the same layer.

• Epitaxy:

– Gas precursors: SiH2CL2 (60 sccm), GeH4 (10 sccm), B2H6 (80 sccm) – Temperature: 650 °C

– Pressure: 20 Torr

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2.4. CDE GROWTH OFIN SITU DOPED SI1−xGEx 19

The growth rate of the p⁺-Si0.73Ge0.27 on Ge was 40-45 nm/min. The layer thicknesses were measured in a similar way as in section 2.2. The root mean square (RMS) surface roughness was found less than 3 nm. The SIMS profiles are shown in Fig. 2.4(a). Dopant concentration of 2.5·10¹⁹B atoms/cm³is achieved. Ge content is approximately 27% in agreement with the result from SE. X-ray diffraction (XRD) measurements were performed on SiGe layers grown on 1.7 µm of Ge SRB (Fig. 2.4(b)). We can therefore grow highly doped p⁺-Si0.73Ge0.27 films selectively to SiO2, on bulk Ge surfaces.

2.4 CDE growth of in situ doped Si

_1−x

Ge

_x

Another approach towards selectivity is the so called cyclic deposition-etch (CDE) method [99, 100, 101, 102, 103, 104, 105]. It consists of numerous cycles of deposition steps followed by dedicated gaseous HCl chemical vapor etching (CVE) steps [106], without breaking vacuum. In this way, the in situ doped Si1−xGex is grown both on the wanted openings and the mask material. The growth on the mask material is usually polycrystalline whereas growth on the openings is single crystalline.

Etch rate of the polycrystalline material is higher than the etch rate of the single crystalline. This enables the selective etching of the unwanted growth, eventually resulting in layers grown only on the desired openings. By tweaking the process parameters (gas flows, growth temperature, etch temperature and pressure) one can achieve selective growth of an in situ doped Si1−xGex layer of specific thickness.

An advantage of this method is the low temperature growth. Depending on the choice of Si precursor, growth temperatures as low as 450 °C can be achieved.

From a monolithic 3D integration point of view, this temperature budget is ideal.

A preliminary study of growing p⁺- and n⁺-Si1−xGexlayers on Ge substrates with CDE has been conducted. The initial growth results presented below show the potential of this approach to achieving selectivity.

CDE growth of p⁺-Si1−xGex on Ge

The substrates used in this study are 2.4 µm thick n-Ge SRB grown on Si wafers.

The aim was to first develop a layer with low resistivity and then assert the feasibil- ity of the cyclic deposition etch process by etching for various times. The SiH4and GeH4gas flows were kept constant at 90 sccm and 216 sccm respectively. Only the flow of B2H6 was varied in order to determine a process window where resistivity is lowest. The gases are diluted with 2 slm H2 and then injected in the epitaxy chamber. The term gas flow refers to the set value at the mass flow controller (MFC) of the non diluted gas. The injection flow was kept equal to this value. The process conditions were as follows:

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– Ex situ:

∗ 1% HF, 30 s

• Cyclic deposition - etch (for each cycle):

– Growth cycle:

∗ Gas precursors: SiH4 (90 sccm), GeH4(216 sccm), B2H6

∗ H2 flow: 20 slm

∗ Temperature: 560 °C

∗ Pressure: 20 Torr – Etch cycle:

∗ Etch gas: HCl

∗ Carrier gas: H2

∗ Temperature: 500 °C

∗ Pressure: 760 Torr

∗ Time: 10 s → 60 s

In figure 2.5(a) the growth rate and the Ge content in the layer is plotted against the partial pressure ratio of GeH4 and B2H6. The increase in B2H6flow results in a growth rate increase by a factor of almost 2. This behavior has been reported in [102] and is attributed to the B atoms catalyzing H desorption and thus freeing sites for the Si and Ge atoms. The Ge content in the layer remains the same regardless of the B2H6 flow as shown in the same figure. In [102] the authors report the opposite behavior. However, they report on lower Ge content layers (<50%) and with a different gas chemistry (Si2H6 instead of SiH4).

Figure 2.5(b) shows the layer resitivity plotted against the GeH4 and B2H6

partial pressure ratio. As intuitively expected, the resistivity of the layer is reduced with increasing B atom incorporation, owing to the increased B2H6 flow in the chamber. The resistivity reduction is not monotonous however and it might as well be that it will start to increase again as reported in [102].

SIMS analysis was performed on the sample with B2H6 flow of 195 sccm. The SIMS profile is shown in Fig. 2.6. The B dopant concentration was 1.5·10²¹ B atoms/cm³. The dopant concentration is very high and is in agreement with the resistivity results of Fig. 2.5(b) for the sample with the highest B2H6flow. The Ge

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2.4. CDE GROWTH OFIN SITU DOPED SI1−xGEx 21

(a) (b)

Figure 2.5: (a) Growth rate and Ge content plotted against increasing B2H6 flow. The GeH4flow was kept stable and was used as a reference. (b) Layer resistivity with increasing B2H6 flow as extracted from thickness and four point probe measurements on blanket depositions.

Figure 2.6: SIMS analysis of a SiGe layer grown on Ge SRB with SiH4, GeH4and B2H6. The very high B concentration resulting in very low resistivity value is confirmed. The Ge content difference between SIMS and SE (red dash line) is attributed to the high B concentration.

content is however significantly lower than that measured by spectroscopic ellipsometry and is shown in Fig. 2.5(a). This is attributed to the effect the substitutional B atoms have in the SiGe lattice. Boron atoms induce tensile strain in the layer and cause strain compensation.

In order to evaluate the selectivity of the CDE method, SiGe layers were grown on Ge SRB substrates patterned with 200 nm plasma enhanced chemical vapor

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Layer property 1 cycle 2 cycles

Thickness (nm) 27 35

Surface roughness (nm) 4.3 5.2

Table 2.2: Thickness and RMS roughness results of the SiGe layer after one and after two deposition-etch cycles. Thickness was measured with spectroscopic ellipsometry and roughness with AFM.

(a) (b)

Figure 2.7: (a) SEM image of one cycle of 60 s deposition and 10 s etch. (b) SEM image of a different sample with two cycles of 60 s deposition and 10 s etch.

deposition (PECVD) SiO2. Each cycle of the process consists of a 60 s deposition and a 10 s etch. The etch was done in H2 ambient, at 500 °C in atmospheric pressure, inside the growth chamber and without breaking vacuum. In Fig. 2.7 tilted top down SEM images of the two samples are shown. It is clear that no growth is present on the SiO2 surfaces. Table 2.2 summarizes the thickness and roughness measurements for each sample. In agreement with [102, 107], the roughness increase for the 2 cycles growth is to be expected and is attributed to the HCl etch. The surface gets progressively rougher when more (and longer) etch steps are added.

CDE growth of p⁺-Si_1−xGe_x on SOI

Boron doped p⁺-Si1−xGex was grown on the source and drain areas of SOI gate last MOSFETs. Although the MOSFETs were not processed fully to allow for a wafer scale device characterization, the results were promising in terms of layer resistivity, doping concentration, thickness and selectivity control. Process details were as follows:

Applications of Si1

monolithic 3D integration

Contents

List of Publications

List of Acronyms

Chapter 1

Introduction

1.1 CMOS technology and scaling

Silicon germanium alloys in CMOS technology

The re-emergence of Ge devices

1.2 Monolithic 3D integration

Monolithic 3D integration with Ge

1.3 Scope, objectives and achievements

1.4 Thesis Organization

Chapter 2

Selective epitaxial growth of Si 1−x Ge x

2.1 Epitaxial growth of Si

Ge

2.2 Si

Ge

growth on bulk Si

2.3 Si

Ge

growth on Ge bulk

2.4 CDE growth of in situ doped Si

Ge

Selective epitaxial growth of Si _1−x Ge _x