IN
DEGREE PROJECT ELECTRICAL ENGINEERING, SECOND CYCLE, 30 CREDITS
STOCKHOLM SWEDEN 2020,
Filter Design for an HVDC protection IED
EVGENY GENOV
KTH ROYAL INSTITUTE OF TECHNOLOGY
Filter Design for an HVDC protection IED
The School of Electrical Engineering and Computer Science KTH Royal Institute of Technology.
Master’s thesis project.
Evgeny Genov
Abstract
A selective fault detection approach is necessary for successful implementation of multi-terminal high-voltage direct-current (HVDC) grids. Fault detection is per- formed by an intelligent electronic device (IED) that takes in voltage and current measurements, performs fault detection algorithms, and outputs, e.g., trip signals for circuit breakers. A digital low-pass filter is utilised for removing the noise from the signal monitored. The amount of delay imposed on the signal by the filter implementation is critical for speed requirements of DC fault detection. The goal of this research is selecting the best performing design of a digital filter based on considerations, which are application-specific. After considering the theoretical constraints and previous research conducted, a filter design most suitable for the fault detection in HVDC grids is proposed. A series of specifications of Butter- worth filters are tested in a lab environment using the intelligent electronic device (IED) prototype and the dv/dt fault detection algorithm. The behaviour of the filter is studied with respect to changes in threshold setting and slope of a voltage collapse. The speed and accuracy of fault detection are the criteria used for as- sessment of filter performance. The suggested filter design improves the accuracy of fault detection to −2.5 % as compared to −8 % when using no filter (both — for the lowest dv/dt threshold setting). The improved filter shows a more consistent performance across the operational range of threshold settings in the IED.
Filter Design f¨ or HVDC protection IED
The School of Electrical Engineering and Computer Science KTH Royal Institute of Technology.
Master’s thesis project.
Evgeny Genov
Abstrakt
F¨or ett v¨alfungerande h¨ogsp¨and likstr¨oms system (HVDC) med fler terminaler ¨an tv˚a (MTDC) ¨ar det n¨odv¨andigt att ha en selektiv feldetektering. Feldetekterin- gen utf¨ors av en IED (intelligent electronic device) som l¨aser in sp¨annings- och str¨omm¨atningar, k¨or algoritmer f¨or feldetektering och skickar ut t.ex. brytsig- naler till str¨ombrytare. Ett digitalt l˚agpassfilter implementeras f¨or att reducera st¨orningar p˚a de ¨overvakade signalerna. Den f¨ordr¨ojning som uppkommer p˚a grund av filtret, ¨ar kritisk f¨or de tidsbegr¨ansningar som finns f¨or att uppt¨acka fel i lik- str¨omssystem. M˚alet med denna studie ¨ar att v¨alja den digitala filter design med b¨ast prestanda, baserat p˚a ¨overv¨aganden som ¨ar applikationsspecifika. Efter att ha
¨
overv¨agt de teoretiska begr¨asningarna och tidigare genomf¨ord forskning, f¨oresl˚as en filter design b¨ast l¨ampad f¨or fels¨okning inom MTDC. En serie av Butterworth filter
¨
ar testade i labbmilj¨o med en IED prototyp och dv/dt algoritm f¨or feldetektering.
Filtrets beteende analyseras med avseende p˚a f¨or¨andringar i tr¨oskelniv˚aer och lut- ningen av sp¨anningskollapsen. Hastigheten och noggrannheten i fels¨okningen ¨ar kriterier som anv¨ands vid utv¨arderingen av filters beteende. Den f¨oreslagna filter designen f¨orb¨attrar noggrannheten i feldetekteringen med −2.5 % i j¨amf¨orelse med
−8 % med det ursprungliga filtret (d¨ar b˚ada har den l¨agsta dv/dt tr¨oskelniv˚an).
Det f¨orb¨attrade filtret visar mer konsekvent prestanda ¨over hela det operativa omr˚adet av tr¨oskelniv˚aerna i IEDn.
Contents
1 Introduction 5
1.1 Background . . . 5
1.2 Scope of the work . . . 6
2 Theoretical background 7 2.1 Travelling waves . . . 8
2.2 Fault detection algorithms . . . 8
2.3 Noise . . . 10
2.4 False detection signals . . . 10
2.5 Digital filters . . . 11
2.5.1 FIR filters . . . 12
2.5.2 IIR filter design . . . 12
2.6 Relevant research on filter design . . . 14
2.6.1 Wavelet-based protection strategies . . . 14
2.6.2 Resonant filter and discretization methods . . . 15
3 Method 17 3.1 Experimental Setup . . . 17
3.1.1 Analog pre-filter . . . 18
3.1.2 Digital filter . . . 18
3.1.3 Playing Waveforms to the IED . . . 20
3.1.4 Fault detection algorithm . . . 21
3.2 IIR designs . . . 22
3.2.1 Butterworth . . . 22
3.2.2 Bessel . . . 22
3.3 Filter specifications . . . 22
3.3.1 Filter order . . . 23
3.3.2 Phase response . . . 23
3.3.3 Cut-off frequency . . . 23
3.4 Filter assessment . . . 24
3.4.1 Theoretical vs measured frequency responses . . . 24
3.4.2 Functional testing . . . 25
4 Results 29 4.1 Compliance with theory . . . 29
4.2 Spectrum analysis of noise . . . 31
4.3 Step response . . . 32
4.4 Functional testing . . . 33
5 Discussion 36 5.1 Characteristic accuracy . . . 37
5.2 Performance in time domain . . . 37
5.3 Further research . . . 38
5.3.1 Floating-point arithmetic . . . 38
5.3.2 Differentiator low-pass filter . . . 38
6 Conclusion 39
A Filter coefficients 42
Chapter 1 Introduction
1.1 Background
Integration of renewable energy generation into the grid sets new challenges to the operation and the design of power systems. As opposed to conventional power plants running on fossil fuels, the wind power plants and photovoltaics are inter- mittent. Therefore, the energy generation is variable and cannot be dispatched at any given time. Furthermore, the generation sites are much more geographically dispersed as compared to conventional power plants running on fossil fuel. Wind turbines are increasingly moving offshore, further and deeper into the sea. Due to the intermittency of renewable sources, more generation capacity has to be in- stalled. The resulting power flows increase, which makes it necessary to improve the energy transmission infrastructure.
Offshore wind energy is envisioned at the core of European energy transition.
The European Commission estimates the total capacity installed to be in the range between 230 and 450 GW by 2050 [3]. In all scenarios, scaling up from 22 GW in 2019 to the projected capacity will require an appropriate upgrade to electricity grid infrastructure [18]. High-voltage direct-current (HVDC) technology enables flexible and efficient power transfer while reducing losses associated with alternat- ing current (AC) solutions. HVDC will play a more prominent role in the future of the European power system. Meshed grid connections, including combined grid solutions and interconnector tie-ins between countries, are integral to the Euro- pean vision on offshore development. The ‘PROgress on Meshed HVDC Offshore Transmission Networks’ (PROMOTioN) project was established as a part of the EU Horizon 2020 initiative in order to ensure there is a technical and regulatory framework in place for such developments. Among other technologies, the project sets out to develop and demonstrate the DC Grid protection methodologies.
The HVDC grid protection poses a number of challenges for engineering the
next generation electricity infrastructure. In case of faults, the existing point-to- point voltage source converter (VSC) HVDC systems disconnect the entire DC line by activating the switchgear at the AC side. For multi-terminal HVDC systems, this approach is not suitable. Disconnection of the complete grid in case of faults results in a great loss of power which can be detrimental for the surrounding AC grid. Therefore, it is important to isolate the faulted line while keeping the rest of the system in operation. In a typical cable system, if a fault occurs, the resulting discharge wave propagates extremely fast. The wave has a steep wavefront and leads to high short-circuit currents [8]. The mentioned currents can do damage to the power electronic components in DC converters. Therefore, a successful DC fault clearing strategy includes prompt fault detection, discrimination and selective opening of the affected line within a few milliseconds. The opening of the line is facilitated with DC circuit breakers (DCCBs). In this study the main focus lies on on a fully-selective protection strategy using DCCBs.
High speed fault detection is essential for attaining a sufficiently fast DC-side protection. The speed of fault detection depends on the properties of the actual surrounding grid and the properties of intelligent electronic device (IED), the de- cide that processes the fault signal. The fault distance and the grid structure are important factors which determine the clearance time of the fault. For example, if a very remote fault in a grid with long cables is to be detected, the waveform has been dampened and detection will take longer as compared to a grid with short cables where the wavefront is not dampened as much. On the IED side the type of signal being monitored as well as delay produced by the processing hardware and the digital filtering all factor in the speed of fault detection. Digital filtering is important to avoid false fault detection caused by noise.
1.2 Scope of the work
This study presents a comparative analysis of digital filters and their specifications in an HVDC protection intelligent electronic device (IED). The filters need to be optimally designed to provide a trade-off between noise suppression and fast fault detection. The filters investigated are implemented on an IED prototype. The implemented filters were tested using analogue input signals representing faults occurring at different distances from the point of measurement. The quality of a filter design in assessed empirically by observing the accuracy of voltage derivative detection. The effect of a filter design on the time delay imposed on the fault de- tection time is investigated. The relative error between the actual IED operation output and a pre-defined slope of input signal is measured throughout the opera- tional range of the IED. Discrepancies between theoretical frequency response and the practical implementation of the filter are also considered.
Chapter 2
Theoretical background
This chapter provides the theoretical background for fast HVDC fault detection.
The focus of this study will be on DC meshed grid topologies with a redundancy in the system. That means that connections can be done within DC system without conversion to and from AC. In a Multi-Terminal DC (MTDC) grid the redundancy needs to be supported on the fault clearing level, for example by using a fully se- lective protection with DC circuit breakers. If a fault occurs, the ultimate goal is to detect and isolate the fault only for a part of the grid, while keeping the rest of the system operational. For example, in Fig. 2.1, if a fault emerges in the cable 14, only the faulted part gets disconnected, while the rest of the grid continues operation.
Figure 2.1: Example of an MTDC grid
The main advantages behind using MTDC grid for energy transmission are low impedance and low losses. Furthermore, the grid layout enables saving the number of converter stations as opposed to several point-to-point links. At the same time the same advantages present challenges in fault detection and clearing.
A short circuit induces high currents propagating in the grid very fast. The DC fault clearing time needs to be in an order of a few to a few tens milliseconds [8].
2.1 Travelling waves
Unlike for high-voltage AC (HVAC) systems, impedance-measurement methods are difficult to realise in DC grids. In DC, it is not possible to measure voltage and current for one period at e.g. 50 Hz. Due to small timescale and large influence of transient effects calculation of impedance employed in distance protection methods is too slow and unreliable [5]. The DC fault current rises quickly and has a large steady-state value. In order to comply with the required high speed of detection a travelling wave based protection approach is often suggested.
The travelling wave refers to an electromagnetic transient wave emerging when a short circuit fault happens. The said wave propagates at a speed near half the speed of light for cables and around the speed of light for overhead lines. [5] The wave increases locally measured current magnitude and decreases voltage magni- tude while propagating through a line. Conventionally, the sign of the current wave is same as sign of the voltage wave in positive direction and opposite of it – in negative direction. [14]
At points of impedance discontinuity, e.g. the end of a transmission line, the travelling wave gets partially reflected. Throughout the grid the travelling wave keeps propagating and there are more reflections creating forward and backward waves. The result is the consequent fault signal gets attenuated and distorted. The measurement for the IED is placed such that the first wavefront on a faulty line may be dampened through propagation in the line, but should not be distorted by reflections. The Bewley diagrams make a useful visual representation of travelling waves in the time domain. An example of such diagram from [5] is shown below.
As can be seen in the diagram 2.2, the forward and reflected voltage waves, u−
and u+, are related by the voltage reflection coefficient r, defined as r = u−
u+ = Zl− Zc
Zl+ Zc (2.1)
where Zl is a constant impedance at the terminal, different from the characteristic impedance Zc of the transmission line.
2.2 Fault detection algorithms
The objective for fault detection in VSC HVDC grids is to operate reliably within its designed protection zone. That means that the protection system should be ac-
Figure 2.2: Bewley lattice diagram
tivated when intended and not disturb the regular flow of operation. Furthermore, it is especially critical for DC grids to make the detection fast enough to minimise the possibility of damage done to the converters. If the detection happens not swiftly enough, there is also a possibility that the current exceeds the breaking capability of DC breakers.
For fault detection there are two main categories of methods employed: single- ended and double-ended protection schemes. The difference is a utilization of a communication link. Single-ended protection algorithms are used in non-unit protection, making use of measurements at a single location. Double-ended algo- rithms use measurements at two different ends of a line. A communication link is necessary in order to compare the two signals.
Within the scope of this research the focus primarily lies on a single-ended method. The most commonly referenced algorithm uses a calculation of a volt- age derivative of the signal. An incremental change in a voltage measurement is compared with respect to a threshold. A fault is detected if
∆υ ≤ ∆υref (2.2)
This algorithm relies on a rapid collapse of voltage when a fault occurs. The method is influenced by the magnitude of a wave-front, which can be partially damped while traversing through the line. [6] The quality of the voltage deriva- tive based detection also depends on the impedance of the line and bus. If the
impedance is mainly inductive, a reflection of the fault signal reinforces a voltage collapse. If is is capacitive, a current-based detection method is preferred. [6]
2.3 Noise
The electric signal in HVDC networks carries noise that may affect the precision of fault detection. The noise is attributed to various kinds of sources, e.g., partial reflections of travelling waves at cable segments, stray inductances and capaci- tances in cables and bus bars, measurement noise, quantization noise, noise due to electronics or noise due to converter switching [9]. The stray inductances and capacitances are known to generate noise dominant in high frequencies [9].
The issues arising from presence of noise can be partially resolved with a suf- ficiently high sampling rate. The Digital Signal Processing (DSP) theory states that statistical noise uncertainty is inversely proportional to the square root of the number of samples used [16]. However, there are relevant trade-offs, particularly the cost and hardware limitations with the speed of operation.
2.4 False detection signals
An important criterion for implementation of fault protection in MTDC grids is se- lectivity. It means that the detection would react only to faults within designated range and ignore signals coming from external DC faults and non-DC transients.
External faults are faults occurring outside of the protected line.
The only electrical difference influencing internal and external fault behavior is a DC reactor. The DC reactor adds inductive reactance, which helps achieving protection selectivity based only on local measurements. [11] The measurement for the IED is on the line side of the reactor, not the converter side. The reason is that the IED measurement should get the travelling wave that is not impacted by the inductor. After the wave has gone through the inductor it is much dampened such that all other IEDs, for example on neighbouring lines, would see this much decreased travelling wave and not trip. The added electrical distance is used for limiting the reach of the protection zone. The steady-state fault current levels would be significantly damped when travelling the said distance before reaching the IED.
Another utility of the reactors in ends of line is protection and current limitation
Figure 2.3: Example of an MTDC grid
in the breakers. The reactors limit the rate of change in current and therefore, they grant extra time for breakers to trip while currents have not reached harmful levels yet [6].
2.5 Digital filters
For a successful implementation of a selective fault detection method in meshed HVDC networks a digital filter is needed in the IED. The digital filter enables discrimination between true signal and noise. The most important trade-off to be made is between removing noise and sufficient speed. A digital filter is a sys- tem of mathematical operations performed on data for signal separation or signal restoration. In many ways digital filters are similar to their analog counterparts, with the main difference being the sampled discretized, not continuous, input data.
Compared to analog, digital filters are largely superior in terms of performance.
In terms of accuracy and stability, analog filters are constrained with limitations of electronics and characteristics of its their components. The superior performance of digital filters manifests in higher complexity and selective design. Analog filters are subject to component non-linearities, which in turn build up variable errors.
Digital filter performance would be constrained only with accessible computer memory and processing speed requirements.
Generally, there are two ways to implement a digital filter: by convolution and by recursion. All possible linear filters can be designed by convolving the input signal with an impulse response of a filter. This type of filters are referred to as finite impulse response (FIR) filters. An alternative approach to filter design is using recursion. The final output calculated with such filter would depend not only on input samples but also on previously calculated values. Therefore, the filter
operation and is recursive. The class of filter that uses feedback from previous outputs, i.e. recursion, is commonly referred as an infinite impulse response (IIR) filter.
For convenience of calculation the discrete time systems are converted to the frequency domain. The conversion is done by means of a Z-transform, or its special form — discrete Fourier transform. The representation in the Z is useful for analysis of designed filter and construction of the transfer function. The transfer function for a linear, time-invariant digital filter can be expressed in a form
H(z) = B(z)
A(z) = b0+ b1z−1+ b2z−2+ · · · + bNz−N
1 + a1z−1+ a2z−2+ · · · + aMz−M (2.3) The order of a filter would be the greater value of N or M. The numerator roots are called the zeros of the transfer function. The denominator roots are the poles.
If there is no feedback incorporated in the system, i.e. denominator is equal to unity, the resulting operation leads to a FIR filter.
2.5.1 FIR filters
Filters carried out by convolution (FIR) tend to be more numerically stable and have a constant linear phase response. IIR filters require less coefficients and memory as compared to FIR. To satisfy the same set of specifications, i.e. cut-off frequency and stopband attenuation, such filter would require less buffer length.
IIR filters also have low latency, which makes them more suitable for high-speed real-time applications [15].
2.5.2 IIR filter design
To this date the most common design method for IIR filter design is configuring a reference analog filter. This includes the design of a continuous-type prototype resonator and subsequent discretization for digital implementation. Z. Milivojevi´c [12] outlines the following steps in IIR filter design
• Defining filter specification
• Specifying analog prototype filter
• Computing a suitable filter order
• Formulating the transfer function
• Scaling
• Conversion from analog to digital
• Reiterate steps 3-7 until satisfactory
Design in frequency domain
In order to determine IIR filter specifications one needs to identify the desirable cutoff frequency, transition width, maximum passband attenuation and minimum stopband attenuation. The classic analog filter design methods are Elliptic, But- terworth, Chebyshev Type I and Chebyshev Type II. Each of them makes certain trade-offs, e.g. ripple in passband versus wide transition band. The final selection should be the design that meets the specifications with the lowest order.
Once the type and order of the filter are determined, it is possible to evaluate the transfer function of an analog prototype. Moreover, the reference prototype should be scaled with respect to the desirable cut-off frequency.
Lastly, the transfer function of the analog prototype filter needs to be converted into its digital counterpart. The most commonly utilized conversion is known as bilinear transformation. Bilinear transformations are advocated for numerical stability of the resulting filter. Filter stability is questioned only due to coefficient quantization which is performed at the end of the design process.
In the event that the resulting filter does not fulfill the given specifications, or the filter order can be lowered, a part of the design process is reiterated until a satisfactory output.
Design in time domain
An approach to filter design is application specific. Some applications are not only concerned with preserving the shape of the original signal but also the amount of delay imposed by the filter’s implementation. Real-time detection, akin to the detection performed in the IED, falls into this category of time-critical applica- tions. If the filter designed in frequency domain has great attenuation with small filter complexity, there can be unwanted distortions in the time domain caused from different components of the signal being delayed to a different extent [17].
This effect is commonly referred as a ’non-linear phase delay’. An example of such disturbance would be ringing on a filter output that can lead to a false trigger detection.
Step response is an important characteristics subject to analysis in time domain applications. Step response has three important parameters: risetime, overshoot, and phase linearity. Risetime is the number of samples between 90% and 10%
level change in the output signal. The faster risetime is a desired quality for identifying trigger events like electrical faults. Overshoot is another parameter important in step response. Overshoot describes the ringing, ripples at the edges of the output step. The distortions from overshot are not desired, as they can mask the information about the original input signal changes. Phase linearity is a
third parameter that is often considered. In the context of a step response, phase linearity refers to a symmetry above and below the 50% level.
2.6 Relevant research on filter design
2.6.1 Wavelet-based protection strategies
A methodology for fault detection using wavelets was presented in [2]. The so- called fast dyadic wavelet transform (FDWT) was used, commonly applied in de-noising applications. The FDWT is notably a translation-invariant wavelet transform with fast enough performance enabled by dyadic scales. For calculating the wavelet coefficients, the Haar wavelet was employed as mother wavelet. The workings of the final algorithm used in the study are described in [10].
It is concluded that only compactly supported wavelets can be useful. This im- plies that the wavelets need windows with lowest number of samples. In testing, the proposed protection strategy uses a combination of three fault detection cri- teria: voltage wavelet coefficients, current wavelet coefficients, voltage derivative and magnitude. The proposed scheme was performed with a detection time of less than 1.0 ms.
It is also shown that adding load variation and converter switching noise to the simulated signal does not influence the selectivity properties of the studied fault detection strategy. Using only current wavelet criteria causes a lack of selectivity.
A study [9] investigates the impact of non-ideal measurements on DC fault detection. Application of matched filter theory is proposed for optimal discrimi- nation between fault signal and noise. Assuming a DC fault as a step input, the matched filter corresponds to a dilation of the Haar wavelet and has the digital form
hl[k] =
(−1/√
l f or 0 ≤ k ≥ l/2 1/√
l f or l/2 < k ≥ l (2.4)
The matched filter is configured for faults at different locations by adjusting the filter length l. Longer windows showed to successfully detect remote faults where filters of shorter outputs fail. Therefore, the required signal-to-noise ratio (SNR) decreases with increasing filter length or with decreasing distance of the fault to the relay location. With simulated fault detection signals at different distance and associated filters, the employed fault detection methods were found to comply with selectivity requirements.
The filters designed with the use of wavelet coefficients can be considered as digital FIR filter coefficients in the filter design.
2.6.2 Resonant filter and discretization methods
As a part of the larger study on design, control and application of modular mul- tilevel controllers a design for DC-bus voltage controller was proposed in [13] pro- posed. The system included a phase-locked loop (PLL) low-pass filter. The filter is used to suppress ripple and other high-frequency disturbances. The design choice was a second-order Butterworth filter
Hp(s) = a2b s2+√
2abs + a2b (2.5)
The transfer function given in (2.5) can be formulated as a special case to a more general continuous-time resonant filter
Hh(s) = Kh(s cosφh− hωl sinφh)
s2+ ahs + (hωl)2 (2.6) where Kh is the DC gain, ah is the bandwidth, φh is the compensation angle and ωl is the angular resonant frequency. In the low-pass variant in (2.5) the following parameters hold
h = ab
ωl Kh = ab ah =√
2ab φh = −π
2 (2.7)
We can point out that ab would be the desired cut-off frequency, also knows as 3-dB bandwidth of the filter. The quality factor for the second-order Butterworth filter is Qp = 1/√
2.
For realization in the IED, the continuous-time prototype resonator in (2.6) needs to be discretized. The most commonly used conversion method is prewarped Tustin discretization, also called Bilinear transformation. The method reliably suc- ceeds with the main objective of such conversion — a stable system with unaltered resonant frequency. [4] The conversion involves the following substitution with a z-transform
s → wr tanwr2T
z − 1
z + 1 (2.8)
where the prewarping frequency is the resonant frequency wrand T is the sampling period. The generalized direct-form II transposed (DFIIt) structure used for the discretization of resonator filters is based on the inverse of the delta operator δ = z − 1. The transformation in (2.8) is modified respectively
s → wr tanwr2T
δ
δ + 2 (2.9)
Implementing the transform (2.9) to the resonator transform function (2.6) yields the transfer function from the input signal u to output y
H(z) = b0δ2+ b1δ + b2
δ2+ a1δ + a2 (2.10)
The DFIIt structure used in this implementation is shown in a scheme 2.4. The expressions for coefficients α1,2 and β0,1,2 in the recursive and transversal paths are given in [13]. The compensation angle φh is considered zero.
Figure 2.4: DFIIt structure for resonator discretization
Chapter 3 Method
3.1 Experimental Setup
The digital filter is designed and tested for protection applications in an intelligent electronic device (IED) prototype. The prototype used in this study has been developed as a part of the PROMOTioN Project [7]. The hardware and software configurations to the prototype are available open-source.
An HVDC IED processes the electric signal measured in MTDC grid and ex- ecutes fault detection algorithms. If the employed protection algorithms identify a DC fault, the device sends commands for other protection equipment, such as DC breakers. The prototype is a modular solution built on the base of a develop- ment board Zedboard. The board incorporates Xilinx Zynq-7000 System-on-Chip (SoC) and many peripheral interfaces. This SoC circuit tightly integrates field- programmable logic (PL) and dual-core processing unit (PS). While the PL deals with data-acquisition and peripheral communication, the central processing unit is used for algorithm implementation, filtering and memory management. The func- tionality of the development board is also extended with custom and off-the-shelf peripheral modules PMODs. PMODs add the ability for processing digital inputs and outputs, as well as converting to and from analogue signals.
The PL and PS parts of the IED are programmed in different platforms. The programmable logic is coded in Hardware Description Language (HDL) and not specifically touched upon in this research. The processing system is rather within scope of interest, as it is used for higher order computation. Among other func- tions, like communication with a graphical user interface (GUI), the digital filter is run on one of the cores in the processor. Its implementation is coded in C language and programmed to the device via USB-UART interface or a boot file pre-loaded on an SD card. The software filtering calculation adds a fixed group delay. However, this delay is constant and negligible within the sampling period
of 20µs.
Figure 3.1: Experimental IED configuration used in filter tests. Analogue input ports are located at the back panel of the device
3.1.1 Analog pre-filter
The analog-to-digital converter peripheral module (PMOD) includes an analog RC pre-filter aimed to prevent aliasing of noise. The resistance on the PMOD is 90 Ω and capacitance is 2.7 nF resulting in a cut-off frequency
fcutof f = 1/(2 ∗ pi ∗ RC) = 655kHz
This analog pre-filter is configured only to eliminate high frequency noise.
3.1.2 Digital filter
The current previous version of the IED implementation uses an infinite impulse response (IIR) filter. This filter will be modified in the remainder of this master thesis. More precisely, the implemented designs are discrete time realizations of a resonant filter. The transfer function and the discretization method are discussed in the previous chapter 2.6.2. The coefficients α1,2and β0,1,2in the transfer function
are calculated using the following expressions
rh = 1
1 + 2hωαh
1 sin (hω1Ts) (3.1)
Kh0 = Khrh
2hω1 (3.2)
b0 = Kh0 [sin (hω1Ts+ φh) − sin φh] (3.3) b1 = Kh0 [3 sin (hω1Ts+ φh) − 4 sin φh− sin (hω1Ts− φh)] (3.4) b2 = Kh0 [2 sin (hω1Ts+ φh) − 4 sin φh− 2 sin (hω1Ts− φh)] (3.5)
a1 = 2 [1 − rhcos (hω1Ts)] (3.6)
a2 = 2rh[1 − cos (hω1Ts)] (3.7)
The coefficients are pre-calculated for the selected filter design, which can be repre- sented as a special case for a resonant filter. The formulations for different designs can be obtained by modifying the variables h, Kh, ah and φh. For example, the filter used in current implementation is configured with the coefficients
h = ab
w1 Kh = ab ah = 3√ 2 ·√
2ab φh = −π
2 (3.8)
w1 is defined to be an angular resonant frequency. In the currently implemented case it is formulated as
w1 = 2π · 1
Ts · 0.25 (3.9)
which is equivalent to 12.5 kHz. The final filter design that is currently used has the frequency response within the band of interest from 0 to 25 kHz, which is the Nyquist frequency at a sampling frequency of 50 kHz. The resulting filter shares the flat amplitude response quality with Butterworth filters. However, the roll off starts sooner with a slower by 3√
2 damping. The numeric coefficients that constitute the transfer function are found with the expressions given in (3.2) - (3.7)
b0 = 0.125 b1 = 0.5 b2 = 0.5 a1 = 2 a2 = 0.5
The filter is coded in the equation form in C-language in SDK (Software Develop- ment Kit). The coefficients calculated for the each design under test are inputs in the same script. Once it is done, a boot file is generated from the coded software
Figure 3.2: Frequency response of the current filter implementation
and inserted to the IED for programming. The filter algorithm can be expressed as the following
y(n) = b0u(n) + x1(n)
x1(n + 1) = x1(n) + x2(n) + b1u(n) − a1y(n) x2(n + 1) = x2(n) + b2u(n) − a2y(n)
(3.10)
All variables are initialized as 0. The current implementation of the DFIIt res- onator negates the effects of quantizers and overflow characteristic. These phe- nomena are potentially inclined to cause overflow effects, errors and instability in operation of filter, as discussed in a general overview on resonant controllers in fixed-point arithmetic [4]. However, in the IED test case, these occurrences are considered negligible and a simplified system of equations is studied.
3.1.3 Playing Waveforms to the IED
In this study a simple configuration is used. Voltage and currents waveforms are generated and sent to IED analogue inputs by means of the portable signal gener- ator and data acquisition (DAQ) devices — ’Digilent Analog Discovery 2’. More realistic fault signals, and corresponding voltage waveform, can be extracted from a power system design software, PSCAD. Simpler waveforms for functional and frequency response tests are formulated in MATLAB, as well as, in the provided
’WaveForms SDK’ interface from Digilent. The scripts used for reading and writ- ing custom waveforms to the IED are programmed in the MATLAB environment.
MATLAB supports the ’Digilent Analog Discovery’ hardware by using an add-on
’Data Acquisition Toolbox’. MATLAB support allows no operation in the back- ground. This means that one cannot write a signal from one signal generator and simultaneously read the trip signal with a data acquisition device. There is also a limitation on a hardware side, since no more than two analogue inputs or out- puts can be used simultaneously with this setup. An inherent limitation of this approach is inability to set up a closed loop test. The utility of ’Analog Discovery’
devices can possibly be expanded with more functionality accessible via commands in ’Digilent Waveforms’ software development kit (SDK). The tools provided in the SDK require an implementation programmed in C++ or Python.
Data capture
After a fault is detected by the IED or the manual trip signal has been triggered, the data log is saved via the graphical user interface (GUI) to the local computer.
The IED GUI is implemented within the MATLAB environment. The current IED implementation allows to record 800 data points at 50 kHz. Therefore, the recorded window covers the duration of 16 ms. The data log has capacity to store signals from multiple links, positive and negative poles, both in raw signal and filtered form.
3.1.4 Fault detection algorithm
This study centers its attention at the dv/dt algorithm. The dv/dt algorithm is the most commonly referenced algorithm for multi-terminal HVDC grid protec- tion. The reason for that is that it is easier to achieve selective fault detection as compared to purely current-based measurements. As a result of having to use voltage measurements, the voltage measurement difficulties have to be taken into account. The associated noise is substantially higher in field voltage measurements as compared to current measurements. The reason is the underlying technical chal- lenge imposed by measuring voltage in HVDC grids. The solution to this challenge is a cascade of voltage dividers with highly accurate RC-elements. This way the output signal is scaled down to a level agreeable with voltage measurement speci- fications. Parasitic inductances in RC dividers add up to a noise and disturbances observed in voltage measurements. The noise constitutes the demand in a digital filter employed by the IED.
3.2 IIR designs
3.2.1 Butterworth
A Butterworth filter has a maximally flat magnitude in the passband and a mono- tonic frequency response. Having no ripples in the passband makes it particularly suitable for DC applications. An additional benefit is linear passband phase re- sponse. The trade off is the slowest roll-off of all analogue designs of equivalent order. The roll-off becomes steeper with increasing order but the filter’s overshoot also increases [16]. The magnitude response of an n-th order Butterworth filter is given by
|H(jw)|2 = 1
1 + (w/wc)2n (3.11)
where wc is the cut-off frequency. The Butterworth filter is most-commonly used as an anti-aliasing filter due to its maximum flat band nature. Butterworth filters have a more linear phase response in pass-band than the alternative designs, such as Chebyshev or elliptic filters. This is advantageous for best performance of the IED in the time domain: low group delay, no discrepancy in delay in different frequency bands and a lower level of overshoot. Butterworth is a low-pass filter design of choice in DC voltage control applications in [13] and [9].
3.2.2 Bessel
Thr Bessel filter is another type of analog IIR filter. Its main characteristic is maximally flat phase delay in the passband. Therefore, the filter of this type has the best linear phase response qualities. However, it is inappropriate to apply the bilinear transformation to digitally convert the analog Bessel filter. The bi- linear transformation does not preserve the maximally-flat group delay, just the amplitude response.
3.3 Filter specifications
The specifications of the digital filter need to be formulated by following the pro- cedure outlined in section 2.5.2. The relevant specifications typically used in IIR filter design are cut-off frequency, transition width, maximum passband attenua- tion and minimum stopband attenuation. However, the problem examined in this study is non-trivial. It means that there is a lack of information about the meshed HVDC system that makes strict constraints and specifications impossible. Some considerations and justifiable assumptions about the systems in question are made regarding the qualities sought upon in the digital filter for applications in DC fault
detection. The utility of implemented filters is assessed in functional tests. The functional tests evaluate the characteristic accuracy of a voltage derivative fault detection algorithm run on the IED.
3.3.1 Filter order
Butterworth and Chebsyhev filters have an increasing overshoot as the order, i.e.
number of poles, increases [16]. What is unique to digital Butterworth filters, the amount of overshoot and ringing also depends on the cut-off frequency of the filter.
This happens when the filter design is overoptimized for performance in frequency response at the expense of the time-domain. In [13], a second-order low-pass Butterworth filter is used for a similar application in a dc-bus-voltage controller.
In [9] it is noted that an increase in order of Butterworth filter significantly impacts the delay on fault detection for sampling rates lower than 50 kHz.
The design approach used in this study is focusing on filter designs of minimal, second order. The choice is motivated by speed considerations and thus, minimum complexity in filter discretization is desired. If the test results expose errors arising from slow roll-off in the transition band and too narrow pass band, the higher order filter designs should be studied.
3.3.2 Phase response
A linear phase response is a desirable characteristic. The slope of the linear func- tion is indicative of the amount of delay, by which the input signal is shifted. A linear phase filter will minimize the disruptions in the signal shape in the time domain. It can be important since the excessive ringing would add excessive noise that could affect the performance of the IED.
3.3.3 Cut-off frequency
The exact frequency spectrum of noise is unknown. A realistic assumption for noise level in field made in this study is ±1 kV. This translates to a maximum possible change in voltage of 2 kV over one sample period (20µs). The range of dv/dt signal of interest in HVDC grid is from 6 kV to 40 kV. At the IED side the maximum change due to noise in input analogue signal is 12.5 mV/20µs. A useful detectable dv/dt signal is from 75 mV to 250 mV per sample at the sampling rate of 50 kHz. The resulting minimum signal to noise ratio (SNR) is
SN R = 75 mV 12.5 mV = 6
1 (3.12)
This approximation takes in noise from the field measurement as a benchmark for noise levels. At the hardware side, the noise levels of ±2 mV have been indicated in
IED tests [7]. The combined noise should be attributed as main source of relative error to the overall characteristic accuracy of the dv/dt fault detection algorithm in the IED.
Another purpose to a filter is anti-aliasing. The anti-aliasing filter is purposed to remove the unwanted input frequencies. According to the Shannon’s sampling theorem, the frequencies above half of the sampling frequency contribute to alias- ing, ambiguous reconstruction of the signal from its samples. In this paper, the IED sampling frequency is pre-determined, the filter cut-off frequency should be assessed for values equal or lower than the Nyquist frequency — 25 kHz. According to [17], there is no general rule of thumb for picking the particular fraction of the Nyquist frequency as the cut-off frequency. Particularly with Butterworth filters with slower roll-off, there is a sharp roll-off. A significant portion of filter response remains active outside of a filter’s defined passband.
In some cases it is beneficial to pick a lower cut-off frequency, as it would relax a sharp cut-off requirement for the anti-aliasing filter. This can be done if the sampling rate well exceeds the Nyquist rate, twice the the maximum component frequency of the function being sampled. Furthermore, there can be disturbances of lower frequencies and a lower-cut off frequency would cancel them out.
In this study different Butterworth filters of several cut-off frequencies are selected for comparison: 20 kHz, 12.5 kHz, 6.25 kHz and 3.125 kHz. The corre- sponding coefficients, calculated according with the method in the section 3.1.2, are provided in the appendix A.
3.4 Filter assessment
3.4.1 Theoretical vs measured frequency responses
In order to validate the correct experimental setup the comparison between the- oretical and measured frequency response of the implemented filter is done. The measured data is obtained from recording the response to input sinusoidal with particular frequencies. Theoretical and measured are slightly different but within reasonable limits. Towards high frequencies, 10 kHz and more, the deviations be- come more significant. An alternative method was trialed for evaluating the com- pliance with theoretical performance. A step function from 5 V to 0 V is fed to an analogue input with a waveform generator. The transfer function is estimated from known input and filtered output signals. This test is a less laborious method. The approximation of the practical frequency response is more approximate and shows more variance rather than testing individual frequencies. Nevertheless, the results shown in 3.4 checks with the frequency response in 3.3. In the band near Nyquist
Figure 3.3: Bode diagram. Amplitude and phase response of a resonant low-pass filter. Line: theoretical frequency response. Scatter points: practical data as response of a system to sinusoidal inputs
frequency the performance starts deviating from the performance expected from the theoretical transfer function. Regarding the method, for sake of better accuracy the response to individual sinsusoidal input as shown in 3.3 is used thenceforth.
The response to step function remains in use for initial design validations.
3.4.2 Functional testing
The procedure for the functional type testing of the IED was adapted from [1].
The objective of the testing is to determine the relative error between the actual IED operation point and the operation point defined in the device settings. This is done by comparing the actual thresholds at which the IED detects faults with the threshold set in the setting of the device’s fault detection algorithm. The threshold under test is the fixed dv/dt script values in the operational range of the IED — from 6 kV to 40 kV per sample (20µs), as suggested in [1].
The waveforms with a ramp of predefined dv/dt slopes are applied to the IED.
These slopes are superimposed on a signal with a typical steady-state value (320 kV.
The ramp rolls off after 0.25 s of flat steady-state signal. The amount of slope in- crementally changes by a fixed interval δ with every iteration.
The initial test procedure as described in [1] is shown in 3.5b. The ramp tran- sients with incrementally increasing slope are applied to the IED. The first test shot has the slope at a value that is lower than the threshold by an expected maximum error band b. While initially chosen to be 10 %, b was increased to
Figure 3.4: Bode diagram. Amplitude and phase response of a resonant low-pass filter. Line: theoretical frequency response. Scatter points: practical data as response to an input step function
20 % for filter design showing a more significant deviation in operation range. If IED does not trip, a new test shot is applied with a slope closer to the set thresh- old, increased by δ = 0.05% every iteration. Five threshold settings are tested:
6 kV/20µs, 10 kV/20 µs, 15 kV/20 µs, 20 kV/20 µs, 40 kV/20 µs. These values cover full range of operational conditions expected from the IED. Different thresholds are necessary for applications dependant on the type of HVDC system and cable lengths requiring different threshold settings.
During the test it was discovered that the IED setup demonstrates a peculiar behaviour after the first trip. There is a region of dv/dt values for the threshold where the fault detection algorithm performs inconsistently. Trip signal reliability over the said region is low. The functional testing procedure has been adjusted to account for the new-found transitional band of operation. The updated situation is shown in 3.6. There are two error values that are evaluated to determine the accuracy of the IED. 1 is the percentage difference between the threshold in the IED setting and the slope of the test shot applied at the input for which the trip signal is first observed. 2 is the percentage difference between the threshold in the IED setting and the slope of the test shot for which the IED sends trip signal consistently. Here it is defined as the threshold value after which the IED trips in 10 next consecutive iterations.
(a) dv/dt slope iterations until first trip
(b) Routine for evaluating dv/dt algo- rithm actual threshold
Figure 3.5: Functional testing procedure for evaluation of dv/dt algorithm accu- racy as in [1]
Figure 3.6: Threshold test ramp with sparse trip region
The accuracy metrics 1 and 2 are evaluated for different threshold settings. The measurements are repeated 3 times for each setting, the characteristic accuracy is determined by mean values. An example of plotted results 3.7 is provided for the filter design used initially. The yellow area shows the transitional region where the fault detection is inconsistent. The blue line is the accuracy for which the IED first trips, measured as a percentage difference to the set threshold. The orange line is accuracy for which the IED trips consistently for threshold values above it.
The red dotted line represents the threshold level programmed in the IED setting.
Figure 3.7: IED dv/dt algorithm threshold accuracy (earlier used filter)
Chapter 4 Results
This chapter presents the results from testing different Butterworth filters of dif- ferent cutoff frequencies compared with the initial filter and no filter.
4.1 Compliance with theory
The frequency responses of digital filters implemented on the IED are compared to their theoretical counterparts. The Bode diagrams for the transfer functions of filters in testing are shown in Fig. 4.1. The scatter points in Fig. 4.2 demonstrate the frequency response in practice. The observation is that there is major disparity between the theoretical phase response and the realization of the filter for the Butterworth filters with higher cut-off frequency. The practical phase response is more linearized than predicted by theory. The practical magnitude response is more attenuated in the passband, closer to the Nyquist frequency. The attenuation is clearly visible in the response for the filter with 6.25 kHz in 4.2c. In the region close to the Nyquist frequency, the hardware delay and aliasing effects disrupt the integrity of the filers.
Figure 4.1: Frequency response of Butterworth filters
(a) Cut-off frequency 20 kHz (b) Cut-off frequency 12.5 kHz
(c) Cut-off frequency 6.25 kHz (d) Cut-off frequency 3.125 kHz Figure 4.2: dv/dt algorithm accuracy for Butterworth filters
4.2 Spectrum analysis of noise
The frequency content of noise is valuable information for designing the filter, the tool of suppressing noise. It is possible to estimate the noise content if the input signal is stationary, e.g. in a steady state. The Fig. 4.3 is a power spectral density plot. It is the frequency content of the output signal when a steady state wave- form at 4 V is generated at the analogue input. The DC frequency component is excluded from the plot, as it evidently dominates in signal power density distri- bution. As seen in the plot, the biggest noise contributions appear at frequencies 6 kHz and higher.
Figure 4.3: Frequency spectrum of measured signal (DC excluded)
4.3 Step response
A simple step function was generated at the analogue input of the IED. The step response of the Butterworth filters under test are shown in Fig. 4.5. Butterworth filters show an overshoot in their step responses. The overshoot is of 17% to 4%
depending on a cut-off frequency. Filters with lower 3-db bandwidth show the higher overshoot values. The rise time, fall time in Fig. 4.5, is clearly inversely proportional to a cut-off frequency. The fall time changes within a range from 20µs to 130 µs. The fluctuations in the lower half of the step response, and thus lack of symmetry between halves, highlight the non-ideal linear phase in the filter.
The prolonged fall time for the filter of a lower 3-db bandwidth makes a direct influence on the IED operation time. Fig. 4.4 shows an example oscilloscope measurement for two extreme cases. Here, for 20 kHz cut-off frequency and low dv/dt threshold the IED operating time is 100.2µs. For lower cut-off frequency, 3.125 kHz, and high dv/dt threshold, the operating time is 120.3µs, one sampling period longer.
(a) 20 kHz cut-off frequency.
dv/dt threshold at 6 kV/20µs
(b) 3.125 kHz cut-off frequency.
dv/dt threshold at 40 kV/20µs
Figure 4.4: Operational time of a Butterworth filter. Orange is a step function at IED input. Blue is the trip signal. The area represents the distribution of the waveform with lower population density.
Figure 4.5: Step response of Butterworth filters with different cut-off frequencies
4.4 Functional testing
Five settings for the dv/dt threshold covering the suggested operational range of the IED are tested: 6 kV/20µs, 10 kV/20 µs, 15 kV/20 µs, 20 kV/20 µs and 40 kV/20µs. The overall accuracy has been determined for each setting, as shown in plots 4.6a-4.6b, 4.7a-4.7d and tables 4.1-4.4. Two values for accuracy are pro- vided, a lower bound 1 is a relative accuracy when the IED trips first. An upped bound 2 is a relative accuracy when the tripping of the IED becomes consistent.
The yellow area in figure 4.7 shows the transitional region where the fault detec- tion is inconsistent.
As seen from 4.7, the overall basic accuracy improves with the cut-off frequency.
The transitional region narrows down and the value for accuracy converges to
−2 %. Compared to the older implementation (Fig. 4.6b) and the implementation without filter (Fig. 4.6a), the error of the Butterworth filter is flat and consistent across the full range of threshold settings 4.7a-4.7d.
(a) No filter (b) Earlier used filter Figure 4.6: dv/dt algorithm accuracy for reference settings
(a) Cut-off frequency 20 kHz (b) Cut-off frequency 12.5 kHz
(c) Cut-off frequency 6.25 kHz (d) Cut-off frequency 3.125 kHz Figure 4.7: dv/dt algorithm accuracy for Butterworth filters
IED dv/dt setting (kV/20µs) 1 (%), first trip 2 (%), always trip
6 kV/20µs -20.13% -8.61%
10 kV/20µs -17.93% -3.94%
15 kV/20µs -16.55% -3.91%
20 kV/20µs -15.00% -2.75%
40 kV/20µs -14.22% -3.00%
Table 4.1: Characteristic accuracy for dv/dt algorithm (δ = 0.05%) on IED.
Butterworth filter with a cut-off frequency 20 kHz
IED dv/dt setting (kV/20µs) 1 (%), first trip 2 (%), always trip
6 kV/20µs -9.49% -3.47%
10 kV/20µs -9.18% -4.20%
15 kV/20µs -9.06% -4.08%
20 kV/20µs -9.30% -4.53%
40 kV/20µs -8.87% -4.10%
Table 4.2: Characteristic accuracy for dv/dt algorithm (δ = 0.05%) on IED.
Butterworth filter with a cut-off frequency 12.5 kHz
IED dv/dt setting (kV/20µs) 1 (%), first trip 2 (%), always trip
6 kV/20µs -3.78% -1.32%
10 kV/20µs -3.15% -1.90%
15 kV/20µs -3.31% -1.91%
20 kV/20µs -3.30% -1.95%
40 kV/20µs -3.00% -2.05%
Table 4.3: Characteristic accuracy for dv/dt algorithm (δ = 0.05%) on IED.
Butterworth filter with a cut-off frequency 6.25 kHz
IED dv/dt setting (kV/20µs) 1 (%), first trip 2 (%), always trip
6 kV/20µs -3.07% -1.39%
10 kV/20µs -2.55% -1.55%
15 kV/20µs -2.33% -1.55%
20 kV/20µs -2.45% -1.70%
40 kV/20µs -2.47% -1.80%
Table 4.4: Characteristic accuracy for dv/dt algorithm (δ = 0.05%) on IED.
Butterworth filter with a cut-off frequency 3.125 kHz
Chapter 5 Discussion
In designing a sampled-time system, a filter design consists of a series of trade offs between signal accuracy and resources (computation power, memory, cost, power consumption) imposed on the system implementation. With the fixed sampling rate, the design of the digital filter is the main tool in optimization of a sampled- time system’s response. This study deals with a task of finding the filter settings that enable a) matching the filter’s output frequency spectrum to the spectrum of the input fault signal, b) matching the output’s time domain properties to the time domain properties at the input, c) imposing a time delay acceptable for HVDC fault detection requirements. These objectives are commonly reached at making reasonable trade-offs specific to the application of such system. For example, im- plementation of a digital filter bears added group delay and frequency-dependent delay due to non-linearities in the phase response. If the magnitude response of the filter is over-optimized, the shape of signal over time and the amount of delay become a concern.
The use case of the IED, being DC fault detection, puts up significant con- straints on the speed of operation. Therefore, IIR minimal-order designs are uti- lized as the most time-efficient topology. Therefore, the analogue prototypes are used in the design of filter, with Butterworth filter being the design with best linear phase delay properties. In given conditions, picking the right specifications for the filter is a matter of trade-off between best characteristic accuracy and the amount of time delay.
5.1 Characteristic accuracy
The functional testing results in Fig.4.7 indicate that there is a systematic offset in dv/dt signal persistent with any filter configuration. The IED trips for wave- forms with voltage at a slope at about 2 % lower than the threshold set in the dv/dt algorithm. It is suggested that the bias can be originating from a wrongly calibrated waveform generator as well as quantization error in ADCs.
From the accuracy standpoint, among the tested set of specifications, the Butter- worth filters with the lowest cut-off frequency delivers the best performance. This conclusion is consistent with the observed noise frequency density plot shown in Fig.4.3. The majority of noise is present in the frequency range of 6 kHz and above.
Furthermore, a sharp roll-off in frequency response of the filter enables uniform performance within entire settings range from 6 kV/20µs to 40 kV/20 µs. Filters with a slower roll-off let in more signal disrupted with noise in higher frequencies.
The result is divergence in characteristic accuracy between lower and higher dv/dt thresholds. An example of this phenomenon is seen in Fig.3.7.
5.2 Performance in time domain
The results for step response of the filters show that the cut-off frequency is in- versely proportional to the fall time of the voltage signal in the time domain. The fall time is 20µs for a filter with a 20 kHz cut-off and 130 µs for a filter with a 3.125 kHz cut-off. This means that for the filter with the highest cut-off the delay lies within one sampling period (20µs) and is completely negligible. For filters with higher cut-off than 20 kHz the delay could comprise of 1 sampling period or more. A more accurate calculation of the impact of the filter on the IED operation time requires a real-time simulator. As reported in [1], the IED operation time ranges from 100µs to 150 µs for fault locations at 0 to 200 km from the IED for the initial filter with 12.5 kHz cutoff and slow roll-off.
The time delay considerations are confirmed in a test oscilloscope measurement for extreme cases in Figures 4.4a and 4.4b. 20 kHz cut-off frequency and low dv/dt threshold enables faster fast detection by 20.1µs than the filter with a 3.125 kHz cut-off and high dv/dt threshold. Therefore, for the extreme case, difference is equivalent to one sampling period of the IED. The amount of delay is comparable to a total variability of 23.2µs in the operation time of the IED found in [7] when applying the same waveform repeatedly.
5.3 Further research
5.3.1 Floating-point arithmetic
The current IED implementation uses the fixed point arithmetic and stores the data measured as a 32-bit unsigned integer. The filter outputs are also stored in a fixed-point 32-bit format. The floating point arithmetic had a more dynamic range. Numbers are no longer uniformly spaced, as it is in the fixed-point format.
The floating point representation has smaller gaps between small numbers and larger gaps between large numbers. As a result, the floating computation assures a better precision. The qunatisation error, resulting from rounding to the nearest value that can be stored, is smaller for floating-point arithmetic. Therefore, the quantisation error is much more pronounced with the fixed-point computations.
Quantisation error is expected to be one of the primary noise contributors to the noise spectrum as shown in Fig. 4.3.
Floating-point processing potentially yields a much better precision. It should be possible to remake the current C code implementation of the digital filter and replace the int types with float or double data types.
5.3.2 Differentiator low-pass filter
The algorithm used for fault detection tracks the differential voltage signal. There- fore, the final output data from the IED can be seen as a convolution of a differ- entiator at low frequencies, acting as a high-pass filter, and a low-pass filter that removes the high-frequency noise. Therefore, the combined transformation would comprise a band-pass filter. One of the consequences is that the signal-to-noise ra- tio of the final output would be lower due to differentiation. A more sophisticated filter design procedure would benefit from analysis of such transformation in the frequency domain.
Chapter 6 Conclusion
This thesis project outlined and followed the design process of a digital filter used for fault detection in the IED. Furthermore, a methodology on evaluating the performance of the digital filter was presented. Unlike with the classic approach to filter design, it was not possible to infer the precise filter specifications from field data due to a lack of such. The chosen approach combined the assumptions made about the HVDC fault detection system. A range of filter specifications was selected for testing, namely Butterworth filters with the cut-off frequencies: 20 kHz, 12.5 kHz, 6.25 kHz and 3.125 kHz. Implementations with no filter and with an initial filter used in earlier studies were used as references. The filter outputs were evaluated in the frequency and time domains. An agreement between theoretical and actual performance of the filters was also assessed. The tested accuracy of a filter is the accuracy of the voltage derivative slope detection for a given threshold.
It was assessed via a functional test adapted from [1]. One of the insights was an uncertainty range of thresholds, where the IED was not secured to trip on every test run. The accuracy of the Butterworth filters with higher cut-off frequencies, 6.25 kHz and 3.125 kHz, showed a significant improvement from −8 % when using no filter to −2.5 % (both — for the lowest dv/dt threshold setting). For higher dv/dt threshold settings, the improvement was still valid, yet of lower magnitude.
The overall characteristic accuracy became a flat value, consistent across the full operational range of dv/dt thresholds in the IED.
Bibliography
[1] Geraint Chaffey et al. “Requirements for functional testing of HVDC pro- tection IEDs”. In: CIGRE Science & Engineering (2019), pp. 1–12. issn:
2426-1335.
[2] K. De Kerf et al. “Wavelet-based protection strategy for DC faults in multi- terminal VSC HVDC systems”. In: IET Generation, Transmission and Dis- tribution (2011). issn: 17518687. doi: 10.1049/iet-gtd.2010.0587.
[3] European Commission. “A Clean Planet for all - A European long-term strategic vision for a prosperous , modern , competitive and climate neutral economy”. In: Com(2018) 773. (2018).
[4] Lennart Harnefors. “Implementation of resonant controllers and filters in fixed-point arithmetic”. In: IEEE Transactions on Industrial Electronics (2009). issn: 02780046. doi: 10.1109/TIE.2008.2008341.
[5] Dirk V A N Hertem, Oriol Gomis-bellmunt, and J U N Liang. HVDC grids:
for offshore and supergrid of the future. 2016. isbn: 978-1-118-85915-5. doi:
10.1002/9781119115243.
[6] I. Jahn, N. Johannesson, and S. Norrga. “Survey of methods for selective DC fault detection in MTDC grids”. In: IET Conference Publications. 2017.
doi: 10.1049/cp.2017.0041.
[7] I Jahn et al. “An Open-Source Protection IED for Research and Education in Multiterminal HVDC Grids”. In: IEEE Transactions on Power Systems 35.4 (2020), pp. 2949–2958. issn: 1558-0679 VO - 35. doi: 10.1109/TPWRS.
2020.2970477.
[8] Willem Leterme. “Communication-less protection algorithms for meshed VSC HVDC cable grids”. PhD thesis. KU Leuven, 2016.
[9] Willem Leterme, Mike Barnes, and Dirk Van Hertem. “Signal processing for fast fault detection in HVDC grids”. In: CSEE Journal of Power and Energy Systems 4.4 (2018), pp. 469–478. issn: 2096-0042.
[10] Stephane Mallat. A Wavelet Tour of Signal Processing. 2009. isbn: 9780123743701.
doi: 10.1016/B978-0-12-374370-1.X0001-8.
[11] J. I. Marvik, S. D’Arco, and J. A. Suul. “Communication-less fault detec- tion in radial multi-terminal offshore HVDC grids”. In: IET Seminar Digest.
2015. doi: 10.1049/cp.2015.0050.
[12] Zoran Milivojevic. “Digital filter design”. In: MikroElektronika (2009).
[13] Kamran Sharifabadi et al. “Dynamics and Control”. In: Design, Control, and Application of Modular Multilevel Converters for HVDC Transmission Systems. IEEE, 2016, pp. 133–213. isbn: 9781118851524. doi: 10 . 1002 / 9781118851555 . ch3. url: http : / / ieeexplore . ieee . org / document / 7656771.
[14] Lou van der Sluis. Transients in Power Systems. 2001. doi: 10 . 1002 / 0470846186.
[15] Steven W Smith. “14 Introduction to Digital Filters”. In: The Scientist and Engineer’s Guide to Digital Signal Processing. 1997. isbn: 0-9660176-3-3.
doi: 10.1118/1.594889.
[16] Steven W. Smith. “Statistics, Probability and Noise”. In: Digital Signal Pro- cessing. 2003. doi: 10.1016/b978-0-7506-7444-7/50039-x.
[17] Tim Wescott. “Sampling: What Nyquist Didn’t Say, and What to Do About It”. In: Wescott Seminars (2016).
[18] WindEurope. “Offshore wind in Europe - Key trends and statistics 2019”.
In: Refocus (2019). issn: 14710846. doi: 10.1016/s1471-0846(02)80021-x.
