Linköping Studies in Science and Technology Dissertations, No. 1367
Design of High-Speed
Analog-to-Digital Converters
using Low-Accuracy Components
Timmy Sundström
Department of Electrical Engineering Linköping University, SE-581 83 Linköping, Sweden
Linköping 2011 ISBN 978-91-7393-203-5
Design of High-Speed Analog-to-Digital Converters using Low-Accuracy Components
Timmy Sundström
Copyright © Timmy Sundström, 2011 ISBN 978-91-7393-203-5
Linköping Studies in Science and Technology Dissertations, No. 1367
ISSN 0345-7524 Electronic Devices
Department of Electrical Engineering Linköping University
SE-581 83 Linköping SWEDEN
Cover image
A low-accuracy and color quantized image, by Mikael Sundström, illustrating the printed circuit board of the 1.0 GS/s, 7.5 ENOB, 73 mW pipeline ADC.
Printed by LiU-Tryck, Linköping University Linköping, Sweden, 2011
v
Abstract
The scaling of CMOS technologies has increased the performance of general purpose processors and DSPs. However, analog circuits designed in the same process have not been able to utilize the scaling to the same extent, suffering from reduced voltage headroom and reduced analog gain. Integration of the system components on the same die means that the analog-to-digital converters (ADCs) needs to be implemented in the newest technologies in order to utilize the digital capabilities at these process nodes. To design efficient ADCs in nanoscale CMOS technologies, there is a need to both understand the physical limitations as well as to develop new architectures and circuits that take full advantage of the potential that process has to offer.
As the technology scales to smaller feature sizes, the possible sample-rate of ADCs can be increased. This thesis explores the design of high-speed ADCs and investigates architectural and circuit concepts that address the problems associated with lower supply voltage and analog gain. The power dissipation of Nyquist rate ADCs is investigated and lower bounds, as set by both thermal noise and minimum feature sizes are formulated. Utilizing the increasing digital performance, low-accuracy analog components can be used, assisted by digital correction or calibration, which leads to a reduction in power dissipation. Through the aid of new techniques and concepts, the power dissipation of low-to-medium resolution ADCs benefit from going to more modern CMOS processes, which is supported by both theory and published results.
New architectures and circuits of high-speed ADCs are explored in test-chips based on the flash and pipeline ADC architectures. Two flash ADCs were developed, both based on a new comparator that suppresses common-mode kick-back by a factor of 6x compared to conventional topologies. The first flash ADC is based on redundancy in the comparator array, allowing the use of low-accuracy, small-sized and low-power comparators to achieve an overall low-power solution. The flash ADC achieves 4.0 effective bits at 2.5 GS/s while dissipating 30 mW of power. The second Flash ADC further explores the use of low-accuracy components, relying on the process variations to generate the reference levels based on the mismatch induced comparator offsets. The reference-free ADC achieves a resolution of 3.7 bits at 1.5 GS/s and dissipates 23 mW of power, showing that process variations does not necessarily has to be seen as detrimental to circuit performance, but rather can be seen as a source of diversity.
In two implemented pipeline ADCs, the potential of very high sample-rates and energy efficiency is explored. The first pipeline ADC utilizes a new high-speed current-mode amplifier in open-loop configuration in order to reach a sample-rate of 2.4 GS/s in a single-channel pipeline ADC, a speed which is significantly faster than previous state-of-the-art The ADC achieved above 4.7 bits throughout the Nyquist range while dissipating 318 mW. The second pipeline ADC relies on an inverter-based amplifier, used in switched-capacitor feedback in order to keep the amplifier biased at a power-optimal point. The amplifier uses asymmetrically biased transistors in order to better match the p- and n-type transistors, which increases linearity and allows for fully symmetrical layout. Operating at 1.0 GS/s, the effective resolution of the ADC was 7.5 bits and the power dissipation was 73 mW. This shows that it is possible to achieve low power dissipation while maintaining both high sample-rates and medium resolution.
vii
Populärvetenskaplig sammanfattning
Dagens ständigt ökande krav på högre dataöverföringshastigheter leder till ett antal olika problem i överföringen av information. Den ström av ettor och nollor som sänds ut påverkar varandra och när de kommer fram till mottagaren går det inte att bestämma vad det var som sändes ut. Genom att omvandla den mottagna signalen i en analog-till-digitalomvandlare till en högre upplösning än endast ettor och nollor och sedan använda digital signalbehandling går det att återfå den utsända informationen.
Med höga prestandakrav på digital signalbehandling betyder det att analog-till-digitalomvandlare behöver integreras tillsammans med digitala byggblock på samma chip. Även om utvecklingen av tillverkningsprocesserna leder till ökat antal transistorer per yta såväl som förbättrad prestanda för digital logik så har analoga kretsar inte samma fördelar av processkalningen. Till exempel blir det svårare att bygga kretsar med hög förstärkning och linjäritet i och med att matningsspänningen minskar.
Utvecklingen av analog-till-digitalomvandlare har därför gått mot att börja använda analoga kretsar med otillräcklig prestanda och att sedan använda den kraftfulla digitala signalbehandlingen som finns tillgänglig för att korrigera för de fel som uppstår.
Denna avhandling undersöker möjligheter och gränser för denna digitalt understödda analogdesign. Flera analog-till-digitalomvandlare har konstruerats och demonstrerar olika tekniker för att uppnå både höga samplingstakter såväl som låg effektförbrukning. Effektförbrukningen är en av de viktigaste parametrarna hos analog-till-digitalomvandlare och de lägsta gränserna undersöks för olika omvandlararkitekturer.
Det har skett en ständig minskning av effektförbrukningen hos publicerade omvandlare och de börjar nu närma sig vad som är teoretiskt möjligt.
ix
Preface
This Ph.D. thesis presents the results of my research during the period from March 2006 to April 2011 at the Electronic Devices group, Department of Electrical Engineering, Linköping University, Sweden. The following papers are included in the thesis:
• Paper I – Timmy Sundström, Boris Murmann and Christer Svensson, “Power Dissipation Bounds for High‐Speed Nyquist Analog‐to‐Digital Converters,” in
IEEE Transactions on Circuits and Systems—I: Regular Papers, Volume 56,
Issue 3, pp. 509 - 518, March 2009.
• Paper II - Timmy Sundström and Atila Alvandpour, ”A Kick‐back Reduced Comparator for a 4‐6‐bit 3‐GS/s Flash ADC in a 90nm CMOS Process,“ in
Mixed Design of Integrated Circuits and Systems, MIXDES, Ciechocinek,
Poland, pp. 195 - 198, 21 ‐ 23 June 2007.
• Paper III - Timmy Sundström and Atila Alvandpour, ”A 6‐bit 2.5‐GS/s Flash ADC using Comparator Redundancy for Low Power in 90nm CMOS,“ in
Analog Integrated Circuits and Signal Processing, Volume 64, Issue 3,
pp. 215 - 222, August 2010.
• Paper IV - Timmy Sundström and Atila Alvandpour, ”Utilizing Process Variations for Reference Generation in a Flash ADC,“ in IEEE Transactions
on Circuits and Systems—II: Express Briefs, Volume 56, Issue 5,
pp. 364 ‐ 368, May 2009.
• Paper V – Timmy Sundström, Christer Svensson and Atila Alvandpour, “A 2.4 GS/s, Single-channel, 31.3 dB SNDR at Nyquist, 8-bit Pipeline ADC in 65nm CMOS,” accepted for publication in Journal of Solid-State Circuits. • Paper VI – Timmy Sundström, Christer Svensson and Atila Alvandpour, “A
7.5 ENOB, 1.0 GS/s, 73 mW Pipeline ADC in 65nm CMOS,” manuscript to be
submitted.
During my research I have also been involved in projects generating the following papers, which are either beyond the scope of the thesis or overlapping in content with the included papers:
• Timmy Sundström and Atila Alvandpour, “A comparative analysis of logic styles for secure IC's against DPA attacks,“ in Proceedings of the
23rd Norchip conference, pp 297 – 300, Oulu, Finland, November 2005.
• Timmy Sundström, Behzad Mesgarzadeh, Mattias Krysander, Markus Klein, Ingemar Söderquist, Anneli Crona, Torbjörn Fransson and Atila Alvandpour, “Prognostics of Electronic Systems through Power Supply Current Trends, “ in International Conference on Prognostics and Health
Management 2008, PHM2008, Denver, USA, October 2008.
• Timmy Sundström and Atila Alvandpour, “A 2.5-GS/s 30-mW 4-bit Flash ADC in 90nm CMOS,” in Proceedings of the 26rd Norchip conference, pp 264 – 267, Tallinn, Estonia, November 2008,.
• Jonas Fritzin, Timmy Sundström, Ted Johansson, Atila Alvandpour, "Reliability study of a low-voltage Class-E power amplifier in 130nm CMOS", in Proceedings of IEEE International Symposium on Circuits and
Systems (ISCAS), pp. 1907 – 1910, Paris, France, May 2010.
• Timmy Sundström, Christer Svensson and Atila Alvandpour, "A 2.4-GS/s, 4.9 ENOB at Nyquist, Single-channel Pipeline ADC in 65nm CMOS, " in proceedings of the European Solid-State Circuits Conference, pp. 370 - 373, Sevilla, Spain, September 2010.
xi
Contributions
The main contributions of this dissertation are as follows:
• An analysis of the power dissipation bounds for Nyquist-rate analog-to-digital converters.
• A comparator with reduced common-mode kick-back.
• A study and implementation of redundancy in the comparator array of flash analog-to-digital converters.
• The implementation of a reference-free ADC, relying on process variations to generate the reference levels.
• The implementation of a very high sample-rate single-channel pipeline ADC with open-loop amplifiers.
• The implementation of a medium resolution pipeline ADC with high-linearity and energy efficient closed loop amplifiers.
xiii
Abbreviations
ADC Analog-to-digital converter
BER Bit error rate
CMOS Complementary metal-oxide-semiconductor CMP Chemical-mechanical polishing
DAC Digital-to-analog converter DFE Decision feed-back equalizer
DFSE Decision feed-back sequence estimation DSP Digital signal processing DNL Differential non-linearity
DR Dynamic range
EDC Electronic dispersion compensation ENOB Effective number of bits
ERBW Effective resolution bandwidth
FoM Figure of merit INL Integral non-linearity ISI Inter-symbol interference
ITRS International technology roadmap for semiconductors LSB Least significant bit
MDAC Multiplying DAC
MLSD Maximum-likelihood sequence detection
MMF Multimode fiber
MSB Most significant bit
NBTI Negative bias temperature instability PAM Pulse amplitude modulation
PCB Printed circuit board PDF Probability density function
PRML Partial response maximum likelihood QPSK Quadrature phase shift keying
ROM Read-only memory
SAR Successive approximation register SFDR Spurious free dynamic range
S/H Sample and hold
SINAD Signal to noise and distortion ratio SMR Signal to metastability ratio SNDR Signal to noise and distortion ratio SQNR Signal to quantization noise ratio SNR Signal to noise ratio
T/H Track and hold
THD Total harmonic distortion
xv
Acknowledgments
Many people have supported and encouraged me during my years as a Ph.D. student and deserve my deepest gratitude and warmest thanks.
• First, I would like to thank my supervisor, Prof. Atila Alvandpour, for the inspiration, encouragement and the opportunity to learn the art of circuit design.
• Prof. emeritus Christer Svensson for always offering a new approach to problems.
• Lic. Eng. Jonas Fritzin for your great friendship and for the company throughout these years.
• Dr. Martin Hansson for the great collaboration with tape-outs and teaching and for being a great friend.
• Dr. Henrik Fredriksson and Dr. Stefan Andersson for all the valuable technical discussions.
• Anna Folkesson for always helping with the non-technical aspects of being a Ph.D. student.
• Research Engineer Arta Alvandpour for his assistance in a wide variety of problems.
• All the past and present members of the Electronic Devices research group especially visiting Ass. Prof. Christer Jansson, M.Sc. Daniel Svärd, M.Sc. Ameya Bhide, Dr. Peter Caputa, Assoc. Prof. Jerzy Dąbrowski, Ass. Prof. Behzad Mesgarzadeh, Adj. Prof. Ted Johansson, Dr. Håkan Bengtsson, Dr. Rashad Ramzan, Dr. Naveed Ahsan, Dr. Ingemar Söderquist, Dr. Sriram Vangal, Dr. Shakeel Ahmad, Dr. Mostafa Savadi Osgooei, M.Sc. Dai Zhang, M.Sc. Ali Fazli, M.Sc. Amin Ojani, M.Sc. Fahad Qazi, M.Sc. Omid Esmaeilzadeh Najari and M.Sc. Duong Quoc Tai.
• All my friends for enriching my out-of-work life. • My family for all the support.
• Finally, I would like to thank my fiancée Camilla for all the love and support and her patience with me when my mind is far away.
Timmy Sundström Linköping, April 2011
xvii
Table of Contents
Abstract v
Populärvetenskaplig sammanfattning
vii
Preface ix
Contributions xi
Abbreviations xiii
Acknowledgments xv
List of Figures
xxiii
Part I Design of High Speed ADCs
1
Chapter 1 Introduction
3
1.1
Introduction to Analog-to-Digital Converters ... 3
1.2
Applications ... 3
1.3
Motivation and Scope of the Thesis ... 5
1.4
Organization of the Thesis ... 6
1.5
References ... 6
Chapter 2 Fundamentals of Analog-to-Digital Conversion 9
2.1
The Analog-to-Digital Converter ... 9
2.2
Quantization ... 9
2.2.1 Static and Dynamic Errors ... 12
2.3
Sampling ... 15
2.3.1 Switch Distortions ... 16
2.3.2 Thermal Noise ... 17
2.3.3 Sampling Jitter ... 19
2.4
References ... 20
Chapter 3 High-Speed ADC Architectures
23
3.1
Introduction ... 23
3.2
Flash ADCs ... 26
3.2.1 Inherent Sample and Hold ... 27
3.2.2 Flash Decoders ... 27
3.2.3 Comparator accuracy and redundancy ... 28
3.2.4 Flash ADC Performance ... 28
3.3
Folding ADCs ... 29
3.3.1 Interpolation ... 30
3.3.2 Folding ADC Performance ... 31
3.4
Pipeline ADCs ... 32
3.4.1 Pipeline ADC Performance ... 35
3.5
Successive Approximation ADCs ... 37
3.5.1 Redundancy or Reduced Radix ... 38
3.5.2 Performance of Successive Approximation ADCs ... 39
3.6
Time-Interleaved ADCs ... 39
3.6.1 Performance of Interleaved ADCs ... 40
3.7
References ... 42
Chapter 4 ADC Building Blocks
47
4.1
Comparators ... 47
xix 4.1.2 Speed ... 48 4.1.3 Offset ... 48 4.1.4 Noise ... 49 4.1.5 Kick-back ... 49 4.1.6 Metastability ... 51
4.2
Sampling Circuits och Techniques ... 51
4.2.1 Bottom-plate sampling ... 51 4.2.2 Bootstrapping ... 52
4.3
Amplifiers ... 53
4.3.1 Open-loop amplifiers ... 53 4.3.2 Closed-loop amplifiers ... 53 4.3.3 Comparator-based switched-capacitor ... 534.4
References ... 53
Chapter 5 Challenges and Trends
55
5.1
Effects and Limitations due to Scaling ... 55
5.1.1 Reduced Supply Voltage ... 55
5.1.2 Increased Transit Frequency ... 56
5.2
Matching and Process Variations ... 57
5.3
Trends in Nanoscale CMOS Design ... 58
5.4
Power Dissipation Trends and Limits ... 58
5.5
References ... 60
Chapter 6 Conclusions
63
6.1
Conclusions ... 63
Part II Papers
65
Paper I
67
I.I
Introduction ... 68
I.II
Preliminaries ... 69
I.III
Power Dissipation of ADC Components ... 73
I.IV
Power Dissipation of ADCs ... 78
I.V
Case Studies ... 83
I.VII
Appendix ... 87
I.VIII
References ... 89
Paper II
93
II.I
Introduction ... 94
II.II
Differential Pair Comparator ... 95
II.III
Kick-back effects ... 96
II.IV
Proposed Comparator ... 98
II.V
ADC Implementation ... 99
II.VI
Performance Comparison ... 100
II.VII
Conclusions ... 103
II.VIII
References ... 103
Paper III
105
III.I
Introduction ... 106
III.II
Comparator Redundancy ... 107
III.III
ADC Architecture ... 110
III.IV
Measurement Results ... 115
III.V
Conclusion ... 120
III.VI
References ... 122
Paper IV
125
IV.I
Introduction ... 126
IV.II
Distribution of Reference Levels ... 127
IV.III
ADC Architecture ... 131
IV.IV
Measurement Results ... 133
IV.V
Conclusion ... 136
IV.VI
References ... 137
Paper V
139
V.I
Introduction ... 140
V.II
ADC Architecture ... 141
V.III
Circuit Implementation ... 148
xxi
V.V
Conclusion ... 157
V.VI
References ... 162
Paper VI
165
VI.I
Introduction ... 166
VI.II
ADC Architecture ... 167
VI.III
Circuit Implementation ... 169
VI.IV
Evaluation and Measurement Results ... 172
VI.V
Conclusion ... 175
xxiii
List of Figures
Figure 1.1 – An example of the front-end of a slicer-based serial link receiver. ... 4
Figure 1.2 – An ADC-based serial link receiver. ... 4
Figure 2.1 – Quantization of the input signal. ... 10
Figure 2.2 – Quantization error as a function of input level. ... 11
Figure 2.3 – Simulated 16K-point FFT spectrum of an ideal 8-bit ADC with a full scale input signal (dBFS = 0 dB). ... 12
Figure 2.4 – Non-linear static errors in ADCs. ... 13
Figure 2.5 – Simulated 16K-point FFT spectrum of an 8-bit ADC with a full scale input signal (dBFS = 0 dB). A third order non-linearity is introduced as well as uncertainty of the reference levels with a standard deviation of LSB/8. 14
Figure 2.6 – The a) DNL and b) INL errors for the simulated 8-bit ADC showing the reference variations and non-linear component of the transfer function. 15
Figure 2.7 – The sampling process with a) a simple track-and-hold sampling circuit and b) the associated waveforms of the input and output with the track and hold modes highlighted. ... 16
Figure 2.8 – Sampling of an input signal on a capacitor and (b) the equivalent model with the switch on-resistance and resistor noise source. ... 17
Figure 2.9 – Sampling jitter introduces a frequency dependent error in the sampled voltage. ... 19
Figure 2.10 – SNDR versus input frequency for an ideal 8-bit ADC with 500 ps of rms sampling jitter. ... 20
Figure 3.1 – Performance of different high-speed ADC architectures with data taken from converters published in the conferences ISSCC or VLSI symposium between 1997 and 2011. ... 24
Figure 3.2 – Energy efficiency of the set of ADCs divided into four ranges of different FoM. ... 25
Figure 3.3 - Flash ADC architecture. ... 26
Figure 3.4 – a) The principle of the folding ADC and b) the functionality of the folding circuit for n = 2. ... 30
Figure 3.5 – Interpolation in an ADC with a) resistive interpolation and b) the interpolated output near the thresholds. ... 31
Figure 3.6 – Example architecture of a pipeline ADC. n k-bit pipeline stages are followed by an m-bit flash stage. The amount of redundancy determines the overall resolution. ... 33
Figure 3.7 – A pipeline stage with the MDAC highlighted. ... 33
Figure 3.8 – a) The transfer function of a standard 1-bit pipeline stage without redundancy. Dout corresponds to the comparator (1-bit sub-ADC) output.
b) The effect of comparator offset on the stage output. Offset will cause out-of range errors (highlighted in circles), which will overdrive the following stages. ... 34
Figure 3.9 – a) The transfer function of a redundant 1.5-bit pipeline stage. Dout
corresponds to the sub-ADC binary output. b) The effect of comparator offset on the stage output. Offset up to VFS/8 is tolerated without
overdriving the following stages. ... 34
Figure 3.10 – A differential successive approximation ADC architecture. The switches connecting to the capacitor array is removed for clarity. ... 37
Figure 3.11 – Interleaving of ADCs with the use of double sampling. ... 39
Figure 4.1 – Various components of a comparator. The requirements determines which components are used, and in which configuration. The figure shows a comparator with two pre-amplifiers followed by both clocked and static latches. ... 48
Figure 4.2 – Part of a sense-amplifier based comparator, highlighting the source of the kick-back noise. ... 49
Figure 4.3 – Proposed kick-back reduced sense-amplifier based comparator from Paper II. 50
Figure 4.4 – a) Top-plate sampling and b) bottom-plate sampling. ... 51
xxv
Figure 5.1 - Expected change in supply voltage according to the ITRS, the solid line corresponds to known process solutions while the dashed line is extrapolated values without a known manufacturing process. ... 56
Figure 5.2 - Expected change in transit frequency according to the ITRS, the solid line corresponds to known process solutions while the dashed line is extrapolated values without a known manufacturing process. ... 57
Figure 5.3 - Trend of decreasing the energy per conversion of flash, pipeline and SAR ADCs. P/fs has halved every 1.7 years over the past fifteen years.
For the specific architectures, the energy halves every 3.0 years for Flash ADCs, every 2.1 years for pipeline ADCs and every 1.5 years for SAR ADCs. 59
Figure I.1 - Comparison of published ADC power-dissipation data and minimum required sampling power (PS). ... 71
Figure I.2 - Trend of decreasing power dissipation for flash and pipeline ADCs. P/fs has halved every 2.5 years over the past ten years. ... 73
Figure I.3 - Switched-capacitor gain stage. (a) Schematic with switches and feedback network. (b) Model for analysis in the redistribution phase (Φ2). ... 75
Figure I.4 - Predicted power bounds for process-limited pipeline ADCs [(I.27)] and flash ADCs [(I.29)] together with ADC survey data (○,Δ). The following typical process parameters were used. (350-nm CMOS) VFS=3
V, Veff=300 mV and Cmin=3 fF. (90-nm CMOS) VFS=1 V, Veff=100 mV,
and Cmin=1 fF. (Other parameters) n=SNRbits+0.5, κ=1, and T=300 K. ... 81
Figure I.5 - Predicted power limits for pipeline ADCs [purely process-limited (I.27) and with additional capacitor-matching constraints (I.35)] together with survey data (Δ). The following typical process parameters were used. (350-nm CMOS) VFS=3 V, Veff=300 mV, and Cmin=3 fF. (90-nm CMOS)
VFS=1 V, Veff=100 mV, and Cmin=1 fF. (Other parameters) n=SNRbits+0.5,
κ=1, KC=1 fF/μm2, Kσ=1%µm, and T=300 K. ... 83
Figure I.6 - Experimental data points used for our case study (90-nm pipeline ADC [29] and 90-nm flash ADC[30]). The labels marked “stages only” and “comp only” represent the P / fS values counting only power
dissipated in the pipeline stages and flash comparators, respectively. Also shown for comparison are the curves of Figure I.4 for 90-nm technology. ... 85
Figure I.7 - (a) Veff versus VGS and fT versus VGS for nMOS devices in 90- and
350-nm technology. ... 88
Figure II.1 - Kick-back from the comparator to the inputs. ... 95
Figure II.2 - Original sense-amplifier based comparator. ... 96
Figure II.3 - Model for the differential-pair currents. ... 97
Figure II.4 - Proposed kick-back reduced comparator. ... 98
Figure II.5 - Drain and source voltages of the original comparator. ... 99
Figure II.6 - Drain and source voltages of the proposed comparator. ... 99
Figure II.8 - ADC chip micrograph. ... 101
Figure II.9 – Comparator output voltages. ... 102
Figure II.10 - Reference voltage suffering from kick-back under one clock cycle. ... 103
Figure III.1 - Mean achievable effective resolution of a 6-bit Flash ADC using different calibration techniques. ... 108
Figure III.2 - Mean achievable effective resolutions for a 10-bit Flash ADC. ... 109
Figure III.3 - Flash ADC Architecture. ... 110
Figure III.4 - Differential pair sense-amplifier based comparator. ... 111
Figure III.5 - External SPI control interface and clock-gating circuit. ... 112
Figure III.6 - 63-to-6 bit Wallace Tree Decoder. ... 113
Figure III.7 - A transmission gate full adder cell. ... 114
Figure III.8 - The PCB with the directly bonded die. ... 114
Figure III.9 - Chip micrograph. ... 116
Figure III.10 - Differential non-linearity (DNL) and integral non-linearity (INL) of the ADC. 117
Figure III.11 - Effective number of bits and SNDR vs. sampling frequency. ... 117
Figure III.12 - Effective number of bits and SNDR vs. input frequency. ... 118
Figure III.13 - Output waveform showing every 32nd sample with 256 sample
points at 2.5 GS/s and an input frequency of 1.3 MHz. ... 118
Figure III.14 - Output spectrum showing the fundamental and harmonics in marked with circles. The SFDR is 31.3 dBFS and the SNDR 25.5 dB. ... 119
Figure IV.1 - Distribution of reference levels in relation to the ideal locations of a 4-bit ADC. 128
Figure IV.2 - ENOB assuming only static errors, achieved for an ADC with normally distributed reference levels. ... 129
Figure IV.3 - Architecture of the Flash ADC. ... 130
Figure IV.4 - Wallace tree decoder (63-to-6 bits). ... 132
Figure IV.5 - Transmission gate full-adder cell. ... 132
Figure IV.6 - Sense-amplifier-based comparator. ... 133
Figure IV.7 - ENOB/SINAD versus input frequency. ... 134
Figure IV.8 - Micrograph of the fabricated ADC. ... 136
Figure V.1 - Architecture of the pipeline ADC. ... 141
Figure V.2 - 1.5-bit pipeline stage with the associated timing diagram. ... 142
Figure V.3 - Redundancy in the pipeline stages with – a) the transfer functions (dashed lines) for the three possible digital inputs and corresponding DAC levels as well as the aggregate transfer function (thick grey) when using comparators with the nominal threshold voltages. b) the effect of offset in the comparators and the redundancy margin shown in grey. Highlighted with circles are the input/outputs that can cause out of range
xxvii
voltages when having comparator offsets larger than what is tolerated by the redundancy. ... 143
Figure V.4 - The worst-case settling output, which determines how early the comparators can be clocked. tsettled is determined by when the output is
guaranteed to have crossed the sub-ADC comparator thresholds, which is restrained by the offset budget... 144
Figure V.5 - Metastability occurs when the comparator does not have enough time to amplify a small voltage difference at the input to acceptable voltage levels for digital logic. ... 145
Figure V.6 - SMR versus comparator decision time for the nominal, fast and slow process corners with the time constants from simulating the extracted layout. Also shown is the 49.9 dB limit, which corresponds to 8 effective bits of SNDR. ... 147
Figure V.7 - Double-sampled S/H, a) illustration and b) circuit implementation. ... 148
Figure V.8 - Differential MDAC implementation. ... 149
Figure V.9 - Differential pair comparator based on the StrongARM sense-amplifier latch... 150
Figure V.10 - Chip micrograph. ... 152
Figure V.11 - Digital calibration principle. ... 153
Figure V.12 - Measured DNL and INL. ... 154
Figure V.13 - Measured SNDR vs. input frequency for sample rates up to 2.4 GS/s. 155
Figure V.14 - Measured 2K-point FFT spectrum, sampled at 2.4GS/s and down-sampled a factor 32. The spectrum corresponds to the data points of a) Fin
= 550 MHz b) Fin = 2350 MHz from Figure V.13 with the harmonics
indicated by circles. ... 156
Figure V.15 - Measured output sampled at 2.0 GS/s and down-sampled a factor 32 with Fin = 1.25MHz showing a) waveform indicating only minor
disturbances and b) 16K-point FFT spectrum. ... 158
Figure V.16 - Measured output sampled at 2.4 GS/s and down-sampled a factor 32 with Fin = 1.25MHz showing a) waveform with visible metastability
induced impulse noise and b) 16K-point FFT spectrum. ... 159
Figure VI.1 - Architecture of the pipeline ADC. ... 167
Figure VI.2 - 0.8-bit pipeline stage with the associated timing diagram. ... 168
Figure VI.3 - Track-and-hold half-circuit. ... 169
Figure VI.4 - MDAC implementation. ... 170
Figure VI.5 – Comparator schematic. ... 171
Figure VI.6 - Chip micrograph. ... 172
Figure VI.7 – Measured SNDR (solid line) and SFDR (dashed line) vs. input frequency. 173
Figure VI.8 – A measured 16K-point FFT of a 576MHz input signal, sampled at 1 GS/s and downsampled a factor of 32. ... 173
1
Part I
3
Chapter 1
Introduction
1.1
Introduction to Analog-to-Digital Converters
An analog-to-digital converter (ADC) is the interface between the on-chip digital domain and the real-world domain of analog signals. It is a necessary component whenever analog data from sensors or transducers should be digitally processed or when transmitting data either through long-range wireless radio links or for high-speed transmission between chips on the same printed circuit board (PCB) or over backplanes.
1.2
Applications
There are many applications for analog-to-digital converters, ranging from sensors, audio and data acquisition systems to video, radar and communications interfaces. The applications that require the highest sample-rates in the ADC are typically found in video, radar and communication areas. A field where ADCs has recently emerged as the favorable implementation option is in high-speed serial links, where both high-speed and low power dissipation is of importance.
1.2.1
High-Speed Serial-Links
In order to cope with the increasing demands on communication capacity, the data throughput of serial links continues to increase. Even when transmitting digital two-level signals, the impedance mismatch, channel impairments, crosstalk and frequency dependent attenuation will cause significant problems such as inter-symbol-interference (ISI) at the receiver side.
In order to deal with the channel degradations, equalization of the input signal is required and an example is shown in Figure 1.1. A feed-forward equalizer (FFE) and a decision-feedback-equalizer (DFE) are used together with a one-bit slicer to compensate for the ISI [1], [2].
With a combination of high-speed multi-bit ADCs and the digital speed and logic density available in the newest technology nodes, some of the processing can be moved to the digital domain as shown in Figure 1.2.
Using a multi-level ADC offers several advantages in flexibility and programmability. Examples include using more advanced digital processing when required by the channel, while also offering the option of using other modulation schemes than the two-level binary PAM2 for higher throughput when possible [2].
There is a wide range of both electrical and optical wireline serial-links utilizing ADCs. The applications have different requirements on sample-rate as well as resolution and include the following examples:
Figure 1.1 – An example of the front-end of a slicer-based serial link receiver.
1.3 Motivation and Scope of the Thesis 5
The partial response maximum likelihood (PRML) read-channel is used in DVD systems and in [3], an ADC with a sample-rate of 550 MS/s with a resolution of 7 bits was used.
Gigabit Ethernet uses 5-level signaling (PAM5) over four wire pairs. In order to remove the ISI, a 9-bit 125 MS/s ADC was used together with digital decision feed-back sequence estimation (DFSE) in [4].
In current 10 Gb/s Ethernet links, multimode fibers (MMF) are used for the optical transmission over distances less than 1 km [5]. The multimode propagation of these fibers causes signal dispersion similar to those resulting from multi-path fading in wireless links. This requires electronic dispersion compensation (EDC) implemented in the transceivers. The receiver implementation is moving towards maximum-likelihood sequence detectors (MLSD), which requires ADCs with 6-bit resolution at 10 GS/s [5] - [7].
For optical networks, data rates of 100 Gb/s per channel with wavelength division multiplexing are currently under development. In such systems, the more advanced modulation schemes requires moving to multi-bit ADCs with the least stringent ADC requirement being 27 GS/s sample-rate at 6-bit resolution when using dual polarization 16QAM modulation. Another modulation candidate is dual polarization QPSK where the requirements on the ADC are a sample-rate of 56 GS/s at 5-bit resolution [8], [9].
It is a challenge to implement ADC for these requirements. Although a 125 MS/s, 9-bit ADC is well within what is possible to implement with a single ADC in a modern CMOS process [10], the demands of for example 100Gb Ethernet requires multiple ADCs to be time-interleaved in order to achieve the required sample-rate.
1.3
Motivation and Scope of the Thesis
With the increasing data-rates and tight power budgets of serial links there is a corresponding increase in the demands on sample-rate, bandwidth and power dissipation for ADCs. Although the scaling of CMOS technologies has increased the performance of general purpose processors and DSPs, analog circuits designed in the same processes have not been able to utilize the scaling to the same extent. The supply voltage needs to be reduced in order to reduce oxide stress, which leads to lower voltage headroom. Also, the short channel-lengths lead to low transistor voltage gain. Utilizing the increasing digital performance, low-accuracy analog components can be used, assisted by digital error-correction, which leads to a power dissipation reduction. This is further investigated in Paper I, exploring the power dissipation of Nyquist rate ADCs. Lower bounds for the power dissipation, set by thermal noise and minimum feature sizes, are formulated and it is seen that the power of low-to-medium resolution ADCs benefit from the technology scaling.
New architectures and circuits for high-speed ADCs are explored in Paper II to Paper VI with test-chips based on the Flash and Pipelined ADC architectures. Two Flash ADCs were developed, both based on a new comparator that suppresses common-mode kick-back by a factor of 6x compared to conventional topologies, which is presented in paper II. The first of the two Flash ADCs is presented in Paper III and is
based on redundancy in the comparator array, allowing the use of small-sized, low-power, low-accuracy comparators to achieve an overall low-power solution. The Flash ADC achieves 4 effective bits at 2.5 GS/s while dissipating 30 mW of power. The second Flash ADC, presented in Paper IV, further explores the use of low-accuracy components relying on the process variations to generate the reference levels based on the mismatch induced comparator offsets. The reference-free ADC achieves a resolution of 3.7 bits at 1.5 GS/s while dissipating 23 mW, showing that process variations does not necessarily has to be seen as detrimental to circuit performance, but rather can be seen as a source of diversity.
Two pipeline ADCs were also designed, one focusing on exploring the potential of very high sample-rates and the other on achieving an energy efficient solution. The first pipeline ADC is presented in Paper V and utilizes a new high-speed current-mode amplifier in open-loop configuration in order to reach a sample-rate of 2.4 GS/s in a single-channel pipeline ADC, a speed which is significantly faster than previous state-of-the-art The ADC achieved above 4.7 bits throughout the Nyquist range while dissipating 318 mW. In Paper VI, the second pipeline ADC is presented, which instead relies on an inverter-based amplifier used in switched-capacitor feedback in order to keep the amplifier biased at a power-optimal point. The amplifier uses asymmetrically biased transistors in order to increase linearity in feedback with the advantage of allowing fully symmetrical layout. Operating at 1.0 GS/s, the effective resolution of the ADC was 7.5 bits. Dissipating 73 mW, this shows that it is possible to achieve low power dissipation at medium resolution while maintaining a high sample-rate.
1.4
Organization of the Thesis
This thesis is organized into two parts: • Part I – Design of High Speed ADCs • Part II – Papers
In the first chapter of Part I, an introduction to analog-to-digital converters is given. Chapter 2 presents the fundamentals of analog-to-digital conversion and also describes how the converters can be characterized. In Chapter 3, common architectures used to implement high-speed ADCs are described. Chapter 4 discusses the building blocks of an analog-to-digital converter and their design trade-offs. The challenges in implementing ADCs in the nanoscale CMOS process and current trends in ADC design is presented in Chapter 5. Concluding remarks regarding the design of high-speed analog-to-digital converters is discussed in Chapter 6.
Part II of the thesis contains the full versions of the research papers.
1.5
References
[1]. J. Kim, J. Ren, B.S. Leibowitz, P. Satarzadeh, A.-A. Abbasfar, J. Zerbe, “Equalizer design and performance trade-offs in ADC-based serial links,” in
1.5 References 7
[2]. E.-H. Chen, C.-K. Ken Yang, ”ADC-Based Serial I/O Receivers,” in IEEE
Transactions on Circuits and Systems I: Regular Papers, Volume 57, Issue 9, pp.
2248 – 2258, Sept. 2010.
[3]. M. Bathaee, H. Ghezelayagh, W. Q. Heng, D. Nicolae, O. Fratu, R. Pop, G. Dilimot, V. Feies, P. Agache, R. Ruscu, M. lorgulescu, J. Gang, W. M. Lin, M. Lei, D. Z. Hui, and W. Tao, “A 0.13µm CMOS SoC for all format blue and red laser DVD front-end digital signal processor,” in Digest of Technical Papers
IEEE International Solid-State Circuits Conference, pp. 1012 – 1021, Feb 2006.
[4]. H. Runsheng, N. Nazari, and S. Sutardja, “A DSP based receiver for 1000 BASE-T PHY,” in Digest of Technical Papers IEEE International Solid-State
Circuits Conference, pp. 308 – 309, Feb. 2001.
[5]. A.C. Carusone, “The limits of light: The finite bandwidth of optical fibre [Open Column],“ in IEEE Circuits and Systems Magazine, Volume 8, Issue 2, pp. 56 – 63, Second Quarter 2008.
[6]. A. Nazemi, et.al., “A 10.3GS/s 6bit (5.1 ENOB at Nyquist) time-interleaved/pipelined ADC using open-loop amplifiers and digital calibration in 90nm CMOS,” in IEEE Symposium on VLSI Circuits, pp. 18 – 19, June 2008. [7]. O.E. Agazzi, et.al., “A 90 nm CMOS DSP MLSD Transceiver With Integrated
AFE for Electronic Dispersion Compensation of Multimode Optical Fibers at 10 Gb/s,” in IEEE Journal of Solid-State Circuits, Volume 43, Issue 12, pp. 2939 – 2957, Dec. 2008.
[8]. H. Sun, J. Gaudette, Y. Pan, M. O’Sullivan, K. Roberts, and K.-T. Wu, “Modulation Formats for 100Gb/s Coherent Optical Systems,” in Conference on
optical fiber communication, OFC2009, pp. 1 - 3, Mar 2009.
[9]. G. Raybon, P.J. Winzer, “100 Gb/s Challenges and Solutions,“ in Optical Fiber
communication/National Fiber Optic Engineers Conference, pp. 1 – 35, Feb.
2008.
[10]. K.-W. Hsueh, Y.-K. Chou, Y.-H. Tu, Y.-F. Chen, Y.-L. Yang, H.-S. Li, “A 1V 11b 200MS/s Pipelined ADC with Digital Background Calibration in 65nm CMOS,” in Digest of Technical Papers IEEE International Solid-State Circuits
9
Chapter 2
Fundamentals of Analog-to-Digital
Conversion
2.1
The Analog-to-Digital Converter
The conversion of an analog signal to digital quantizes the input in both time and amplitude [1]. Quantization in time is referred to as sampling and is performed in the ADC front-end, often by an explicit track-and-hold circuit. The amplitude quantization, referred to just as quantization, approximates the input signal given a set of fixed reference levels. The number of possible quantization levels determines the resolution of the ADC, which is typically described with the number of binary bits, n, needed to represent the quantization level.
2.2
Quantization
The quantization of an input signal introduces errors that cannot be removed as the accurate signal information between the quantization steps is lost [2]. This is illustrated for a 3-bit ideal ADC in Figure 2.1, showing how a normalized input between 0 and 1 is
ma wh ste W If (2. de Fi
apped to the corr here the first tran ep size, defined a
Where VFS is the fu
the analog input .3) where Dout is scribed by (2.4). gure 2.1 – Quan responding outpu nsition occur qs as in (2.1), and Vm
ull-scale input ran
signal is approxi the decimal valu
ntization of the i
ut codes using th above Vmin. Her min is the lower en
nge and is define
imated with a co ue of the output c input signal. he mid-riser conv re, qs correspond nd of the input ra d as: orresponding anal code then the qua
vention given in d to the quantizat
ange.
(2.1)
(2.2)
log output, Vout a
antization error, ε (2.3) (2.4) [3], tion as in ε, is
2.2 inp qu res can ap ap be A qu de Fi 2 Quantization
Ideally, the qua put signal as sh uantization error solution increase n be approxima proximated as u proximately 4 bi calculated as in sinusoidal input uantization-noise-cibels then result
gure 2.2 – Quan Quan z aon Err or -qs/ qs/ antization error i hown in Figure is strongly cor es, the quantizati ated as noise. T uniform white no its [1], [4]. With (2.5). signal with an a -ratio (SQNR) ts in the famous f ntization error a /2 /2 1 8 2 8 0 is bound between 2.2. For conver rrelated with the on error become The distribution oise given that t
this approximatio amplitude of VFS/ as expressed by formula of (2.7). as a function of i 3 8 4 8 5 8 6 8 n –qs/2 and qs/2
rters with very e input signal. H es less correlated
of the quantiz the resolution of on, the quantizat
/2 then results in y (2.6). Expres input level. Inp 6 8 7 8
and varies with low resolution, However, when d with the input
ation noise can f the ADC is ab tion noise power
(2.5)
an output signal ssing this result
(2.6) ut Level 11 the the the and be bove can l-to-t in
no Fig the
2.
Th dis an de alw dis int are Fi sca The quantizatio oise floor for the gure 2.3. A full s e ratio to the full2.1
Static
The limited ac hese non-idealitie
stortions in the s nd offset in the t
pend on the spec ways important stortion of the tra
These error so tegral non-lineari e defined as:
gure 2.3 – Simu ale input signal
on noise appears e ADC. The simu
scale input signa scale input in dB
and Dynamic
ccuracy of the mes will shift the stair-case transfe transfer function cific applications [2], [3]. Beside ansfer curve is im ources are quan ity (INL). In the
ulated 16K-poin (dBFS = 0 dB).
as wideband nois ulated spectrum al was used and th B.
c Errors
manufacturing pr reference levels er-function. The of the ADC. Th s but when used es the linear ga mportant as it is antified using dif IEEE standard f
nt FFT spectrum
se in the spectrum of an ideal 8-bi he power is give
rocess will caus s from their idea
distortions give he importance o
in a time-interlea ain error and of
source of harmo fferential non-lin for measurement
m of an ideal 8-b (2.7)
m and gives rise it ADC is shown en in dBFS, whic
e circuit variatio al locations caus rise to a gain e f these error sou aved ADC these ffset, the non-lin onic distortion.
nearity (DNL) ts of ADCs [3], t
bit ADC with a
to a n in ch is ons. sing rror urce are near and they full
2.2 Quantization 13
• DNL[k] – The difference between the code bin width of code k and the average code bin width, divided by the average code bin width after correcting for gain and offset.
• DNL – The maximum absolute value of DNL for all k.
• INL[k] – The difference between the ideal and actual code transition level k after correcting for gain and offset.
• INL – The maximum absolute value of INL for all k. These quantities are shown for a 3-bit ADC in Figure 2.4.
In order to completely quantify ADC performance, the errors related to input and sampling frequency should also be characterized. Quantities used to describe the dynamic performance are, as defined in [1], [2] and [3]:
• Signal-to-noise-ratio (SNR) – The ratio of the signal power to the total
noise power at the output, typically measured for a sinusoidal input.
• Signal-to-noise-and-distortion-ratio (SNDR, also SINAD) – The ratio of the
signal power to the total noise and harmonic power at the output, when the input is a sinusoidal signal.
• Effective number of bits (ENOB) – Defined as in (2.8), where SNDR is the
maximum SNDR for the converter, measured in decibel.
Th no LS Fi inp un • Dynam sinuso • Spurio power • Total h harmo hese quantities ar on-linear distortio SB/8. The DNL an gure 2.5 – Simu put signal (dBF ncertainty of the mic range (DR) oidal to the power ous free dynamic r to the largest sp harmonic distort onic components
re shown in Fig on and a referen nd INL for this c
ulated 16K-poin FS = 0 dB). A t e reference levels – The ratio of r of a sinusoidal c range (SFDR) – pur or distortion c tion (THD) – The to the power of th
gure 2.5 for a sim nce level uncert converter are show
nt FFT spectrum hird order non s with a standar
of the power of input for which S – The ratio betw component within e ratio between th he input signal.
mulated 8-bit AD tainty with a sta wn in Figure 2.6 m of an 8-bit AD -linearity is int rd deviation of L (2.8) f a full-scale in SNR = 0 dB. ween the input sig
n the Nyquist ban he total power of DC with third or andard deviation . DC with a full sc roduced as well LSB/8. nput gnal nd. f the rder n of cale l as
2.3 Sampling 15
There are many sources responsible for degrading the dynamic performance. Most error sources are related to specific architectures and will be discussed in Chapter 3. However, common for ADCs is the sampling process which can increase the noise floor, introduce non-linear distortion and limit the ADC bandwidth. The sampling process will be described below.
2.3
Sampling
In sampling, a continuous-time input waveform is assigned discrete-time values [3]. Although several forms of sampling can be considered, such as ideal and zero-order hold, track-and-hold is the most common sampling scheme in high sample-rate ADCs as the acquisition time is comparable to the sampling period [1]. Track-and-hold
Figure 2.6 – The a) DNL and b) INL errors for the simulated 8-bit ADC showing the reference variations and non-linear component of the transfer function.
sam an mo ref sam [2] the im dis
2.3
wi on cap ele len vo on inp Fi an mo mpling is shown nd output wavefo ode. The samplin ferred to as Nyq mpling process d ]. However, the s ermal noise and mplemented in astortion.
3.1
Switch
Considering the ith an nMOS tran n-resistance, Ron, pacitance will de ectron mobility, ngth of the devi oltage [1]. In order to achi n-resistance is de put–level causin gure 2.7 – The s nd b) the associa odes highlighted in Figure 2.7 wi orms. The quant ng of an input si quist sampling. does not introduc sampling process d jitter in the
circuit, non-idea
h Distortions
e simple samplin nsistor, there are of the transisto etermine the trac
Cox is the gate-o
ice, VGS is the g
ieve a high band ependent of the ng non-linear d
sampling proces ated waveforms d.
ith both a simple tization is then p ignal at a rate at Given fixed and ce any error as th
s is never ideal. S sampling clock alities in the swi
ng circuit of Figu e several sources or, as given by cking bandwidth oxide capacitanc gate-source volta
dwidth, the devic input voltage, th distortion for h ss with a) a simp s of the input an sampling circuit performed by the t least twice the
d equidistant sa he signal can be i Sampling onto a limit the band itch introduce of
ure 2.7a and impl s limiting the per (2.9), together . In the expressio e per unit area, age and VTH is th
ce width needs to he bandwidth w higher input fre
ple track-and-ho nd output with t as well as the in e ADC during h signal bandwidt ampling instants deally reconstruc capacitor introdu dwidth. Also, w
ffset and non-lin
ementing the sw rformance. First,
with the sampl on for Ron, µn is
W/L the width o
he device thresh
(2.9)
o be large but as will change with equencies. Using
old sampling circ the track and h
nput hold h is the cted uces when near witch the ling the over hold the the g a cuit hold
2.3 tra dif ga wi ov va ch tot by de [1] sou co sw sig ach sam
2.3
no po ge Fig Fi mo 3 Sampling ansmission-gate w fferent switch solWhen increasin ate-source and ga ill couple through ver the overlap a alue, with a magn With the fallin hange the gate-to-tal gate capacitan y (2.10) will then pends on the inp ], [5].
There are sever urces. Different mponents into witches is anothe gnal in order to k hieve high bandw mpling circuits a
3.2
Therm
Whenever a vo oise will be introd ower dissipation nerated by the o gure 2.8b.
gure 2.8 – Sam odel with the sw
with parallel nM lution is needed t ng the device wid ate-drain capacita h overlap capacit and sampling cap nitude dependent ng edge of the c -output capacitan nce and Cov is th
n be distributed b put voltage the ch
ral techniques an ial implementati
common-mode, er technique that keep VGS constant
width and lineari are further discuss
mal Noise
oltage is sampled duced in the proc
of ADCs, and n-resistance of th
mpling of an inp witch on-resistan
MOS and pMOS to achieve high b dths in order to r ances increase. T tance to the outp pacitance. This w
on the switch siz clock, the nMOS nce of the transis he overlap capaci between the inpu hannel charge-inj
nd circuits used ions are often
at least to the t is used, where t. This will suppr ity. The different sed in Chapter 4. d onto a capacit cess. This is unav is further explo he switch with th
put signal on a nce and resistor
transistors redu bandwidth or high
reduce the on-res The falling edges put and the charg will introduce an ze and sampling c S transistor will tor from CG/2 to
itance. The chann ut and output. As njection leads to n
to reduce the im used, turning se e first-order. Bo e the clock signa ress non-linear di t implementation .
or Csample, as sho
voidable and will red in Paper I. he equivalent mo
capacitor and noise source.
uce this effect bu h resolution. sistance, the over s on the clock sig ge will be distribu n offset of the h capacitance.
turn off. This w
Cov where CG is
nel charge, as gi s the channel cha non-linear distort (2.10) mpact of these e everal of the e ootstrapping of al follows the in istortions in orde ns and technique own in Figure 2 limit the achieva The noise is be odel being shown
(b) the equival 17 ut a rlap gnal uted hold will the iven arge tion rror rror the nput er to s of 2.8a, able eing n in lent
(2. sw tim of ide Ins Th de the the vno de Th By (2. AD qu eff
The noise gene .10) [6].
The noise will b witch on-resistanc
mes the bandwidt f an ideal
brick-entical to that of
serting (2.11) and
his shows that t creasing the resi e bandwidth.
It is interesti ermodynamics, w
oise is free to vary
rived from:
his gives:
In an ADC, the y setting the sam .16), an estimati DC can be expre uantization noise
fect on the overal
erated by the resi
be filtered by the ce, the total inte th. The noise ban wall filter for w the low-pass filte
d the 3dB bandw
the sampled no istance both decr ing to note th which says that a y) will fluctuate
e thermal noise in mpled noise equal
ion of the minim essed as in (2.17
can vary, but as ll estimations.
istor is white no
e RC filter forme egrated noise is
ndwidth is define which the output er. The output no
width gives the fam
ise is independe rease the power hat this is res system with one with energy kT/
ntroduced by the l to the quantizat mum capacitance 7). Note that the is mentioned in
oise with a spectr
ed by the samplin given by the no ed as the being th
t root-mean-squa oise is then given
mous ‘kT/C’ nois
ent of the switc spectral density sult also follow e degree of freedo /2 [7]. Therefore e sampling will r ion noise of an n e needed to samp exact balance b the discussion in
ral density given
(2.11)
ng capacitor and oise spectral den he cut-off freque are (RMS) noise n by (2.12): (2.12) se formula: (2.13) ch on-resistance as well as incre ws from statist
om (in this case o e, (2.13) can also
(2.14)
(2.15)
raise the noise flo
n-bit ADC, given
ple the signal in between thermal n Paper I, it has li (2.16) (2.17) n by d the nsity ency e is e as ease tical only o be oor. n by n an and ittle
2.3 n-b cap po po
2.3
Ph tim de Fig ap ach Fi sa 3 Sampling An estimation o bit ADC can the pacitance to VFSower, as given by ower dissipation o
3.3
Sampl
The sampled th hase noise in the ming jitter will re pendent on the gure 2.9 for two erture jitter and v
For a certain hievable SNR giv gure 2.9 – Sam mpled voltage. of the minimum en be expressed within half the y (2.18), is the st of an ADC, whic
ing Jitter
hermal noise is sampling clock esult in a corresp slope of the inp o input signals wverror is the resulti
input frequency ven by (2.19) [8] mpling jitter in power dissipatio by assuming tha period of the sa tarting point in f ch is explored in P
not the only no will lead to an u ponding error vol put signal at the with different freq ing rms voltage e y, fin, the sampl ]. ntroduces a fr on needed to sam at an ideal ampli ampling frequenc formulating the lo Paper I.
ise source in the uncertainty in th ltage of the samp
sampling instan quency. tjitter is t
error.
ling jitter will l
equency depen
mple the signal for ifier is charging cy fs. This minim
ower bounds for
(2.18)
e sampling proc he sample-time. T
pled signal, whic nt. This is shown
he rms value of limit the maxim
(2.19) dent error in 19 r an this mum the cess. This ch is n in f the mum the
The sampling jitter will limit the bandwidth of the ADC and the 3dB-bandwidth can be found by equating the SNDR of the ADC without sampling jitter to the SNR given by (2.19). For an ideal 8-bit ADC with an rms sampling jitter of 500 ps, the effective resolution bandwidth (ERBW) is just above 1 GHz. This is confirmed by a simulation of the ideal 8-bit ADC introducing jitter in the sampling process. The achieved SNDR versus input frequency is shown in Figure 2.10.
2.4
References
[1]. B. Razavi, Principles of Data Conversion System Design, IEEE Press, 1995. [2]. R.J. van de Plassche, CMOS Integrated Analog-to-Digital and Digital-to-Analog
Converters, 2nd Edition, Kluwer Academic Publishers, 2003.
[3]. IEEE Standard for Terminology and Test Methods for Analog-to-Digital
Converters, IEEE Standard 1241-2000, 2000.
[4]. P.R. Perez-Alcazar, A. Santos, “Relationship between sampling rate and quantization noise,“ in 14th International Conference on Digital Signal
Processing, pp. 807 – 810, July 2002.
[5]. J. M. Rabaey, A. Chandrakasan, B. Nikolic, Digital Integrated Circuits, Pearson Education Inc., 2003.
Figure 2.10 – SNDR versus input frequency for an ideal 8-bit ADC with 500 ps of rms sampling jitter.
2.4 References 21
[6]. D.A. Johns, K. Martin, Analog Integrated Circuit Design, John Wiley & Sons, 1997.
[7]. R. Sarpeshkar, T. Delbruck, C.A. Mead, “White noise in MOS transistors and resistors,“ in IEEE Circuits and Devices Magazine, Volume 9, Issue 6, pp. 23 – 29, Nov. 1993.
23
Chapter 3
High-Speed ADC Architectures
3.1
Introduction
There is a wide variety of different ADC architectures available depending on the requirements of the application. They can range from high-speed, low resolution flash converters to the high-resolution, low-bandwidth oversampled noise-shaping sigma-delta converters. The high-sample rates required for serial link applications can be attained in two ways. First, a single-channel high speed ADCs can be used, which limits the choice of architectures available. The alternative solution is to use several lower sample-rate ADCs in a time-interleaved (TI) configuration, in order to increase the sample-rate. This allows for a variety of architectures to be used depending on the specific requirements such as power dissipation, area, latency and design time. The architectures that are used for high-sample rate applications, either in a single-channel or time-interleaved are:
• Flash ADCs – The most parallel converter architecture. The entire conversion is complete within one clock cycle.
• Folding ADCs – These are closely related to flash ADCs but using a multi-step implementation. The conversion is often finished within one clock cycle.
• Pipeline ADCs – Several stages are pipelined, achieving a high throughput at the cost of increased latency while allowing more efficient implementations for medium resolutions.
• Successive approximation ADCs – This architecture typically generate one bit per clock cycle, the benefits are the low area needed for the implementation.
An overview of the performance for the different single-channel and interleaved architectures is shown in Figure 3.1 for converters published in the international solid-state circuit conference, ISSCC, or the VLSI symposium between 1997 and 2011 [1]. It is seen that for resolutions below 6 effective bits and sample rates up to 10 GS/s, flash ADCs are the most common architecture. Folding ADCs are used to increase the resolution at the cost of sample-rate. For resolutions above 6 bits, pipeline ADCs are often found around 100 MS/s, targeting wireless applications [2]. Time-interleaved ADCs exist throughout the entire range with interleaved SARs covering the range from 13.5 bits at 40 MS/s to 3.9 bits at 40 GS/s.
Figure 3.1 – Performance of different high-speed ADC architectures with data taken from converters published in the conferences ISSCC or VLSI symposium between 1997 and 2011.
3.1 fig po Th fou me for cir [3] wi Fi dif 1 Introduction A common met gures-of-merit. O ower dissipation he unit is energy p In Figure 3.2, t ur different sub-s edium resolution r a decade, whic rcuits and often
][4]. For the sam ith FoM less than
gure 3.2 – Ene fferent FoM.
thod of measurin One such figure-to the number o per conversion-s
the energy efficie sets with high to ns ADCs under 2 ch have led to t implemented as mple-rates excee n 1 pJ/conversion ergy efficiency
ng the energy eff -of-merit (FoM) of effective quant
tep where power
ency of the same low FoM. The b 200 MS/s. This h
the development interleaved SAR eding one gigasa n-step exist.
of the set of A
ficiency of ADC is shown in (3 tization steps tim r efficient ADCs
e set of ADCs is est energy efficie have been an are t of power effic Rs or single-chan ample per second
ADCs divided in
Cs is through vari 3.1) and relates mes the sample-r
have low numbe
(3.1)
shown, divided i ency is found for ea of active resea
ient techniques nnel pipeline AD d several conver
nto four ranges 25 ious the rate. ers. into r the arch and DCs rters s of
3.2
Flash ADCs
The flash ADC architecture offers the highest potential single-channel sample rate of all the architectures, with the principle being shown in Figure 3.3. The correct quantization level is decided through the parallel comparison of the input signal to 2n-1
reference levels. Typically, a resistor ladder with 2n equally sized resistances is used to
generate the reference voltages. Each comparator determines whether the input signal is larger than the reference level, which will cause the digital outputs to be thermometer coded. In the thermometer code, the ‘1’-to-’0’ transition indicates which quantization level corresponds to the input signal. A decoder is used in order to convert the thermometer code to an n-bit digital output word. Flash ADCs mainly target applications where low latency is important, for example in control loops.
3.2 Flash ADCs 27
The flash ADC is most suitable for low resolutions as the hardware required doubles for a resolution increase of 1 bit. However, as the comparator requirements scale with the resolution, the power dissipation increases by more than a factor of two.
Because of the number of parallel comparators, the flash architecture often have a high input capacitance when compared to other architectures, which leads to higher demands on the driver circuit.
3.2.1
Inherent Sample and Hold
As the correct quantization level is decided within one clock cycle there is no requirement to precede the comparator array with a sample-and-hold, as sampling is inherently performed by the comparators. The absence of a single sample-and-hold increases the circuit requirements and introduces several error sources.
Timing skew between the comparators result in signal dependent distortion as the comparators would sample different time instances of the input signal. By matching the delay of the signal and clock paths, the impact of clock skew can be reduced.
At the latching clock edge, the comparators will start to regenerate. With high input slew-rates the comparator decision could change after the latching edge, effectively introducing a slew-rate dependent latching instant. This effect can be reduced by increasing the rise time of the clock signal, resulting in a power dissipation increase in the clock driver [5].
These error sources results in signal and clock frequency dependent harmonic distortion, reducing the signal to noise and distortion ratio. The power saved by not including an explicit sample-and-hold must then be weighed against the respective costs mentioned above.
3.2.2
Flash Decoders
The choice of decoder topology has an impact on the ADC latency and robustness to comparator offset and noise. The most straightforward implementation of a decoder consists of first detecting the ‘1’-to-‘0’ transition in the thermometer code. This transition point is then used to address a line in a ROM which contains the corresponding binary coded output word. Offset and noise in the comparators could introduce errors in the thermometer code, called bubble-errors. These would result in several lines in the ROM being addressed at the same time thereby introducing significant errors, especially for input signals in proximity to the major code transition. One way to correct for the above error is to use bubble-suppressing logic which cancels the effect of bubbles when appearing near the ‘1’-to-‘0’ transition. However, the appearance of bubbles further away from the correct transition point requires more complex circuits in order to be corrected [6]. To reduce the impact of these bubble errors, the ROM contents can be grey coded so that when two nearby lines in the ROM are simultaneously addressed, the error would then be minimal.
Another decoder topology which is able to optimally correct for bubble-errors is the Wallace tree decoder [7]. By summing all the comparator output values, the bubbles are suppressed and the binary output is generated at the cost of additional hardware.
