A Sizing Algorithm for Non-Overlapping Clock Signal Generators

A Sizing Algorithm for Non-Overlapping

Clock Signal Generators

Master thesis performed in

Electronics Systems at Linköping Institute of Technology by

Fatih Kavak

LITH-ISY-EX 3482-2004

A Sizing Algorithm for Non-Overlapping

Clock Signal Generators

Master thesis performed in

Electronics Systems at Linköping Institute of Technology by

Fatih Kavak

LITH-ISY-EX 3482-2004

Supervisor: Erik Säll Examinor: Mark Vesterbacka

Avdelning, Institution Division, Department Institutionen för systemteknik 581 83 LINKÖPING Datum Date 2004-06-08 Språk

Language Rapporttyp Report category ISBN Svenska/Swedish

X Engelska/English Licentiatavhandling X Examensarbete ISRN LITH-ISY-EX-3482-2004

C-uppsats

D-uppsats Serietitel och serienummer _{Title of series, numbering} ISSN

Övrig rapport

____

URL för elektronisk version

http://www.ep.liu.se/exjobb/isy/2004/3482/

Titel

Title A Sizing Algorithm for Non-Overlapping Clock Signal Generators

Författare

Author Fatih Kavak

Sammanfattning

Abstract

The non-overlapping clock signal generator circuits are key elements in switched capacitor circuits since non-overlapping clock signals are generally required. Non-overlapping clock signals means signals running at the same frequency and there is a time between the pulses that none of them is high. This time (when both pulses are logic 0) takes place when the pulses are switching from logic 1 to logic 0 or from logic 0 to logic 1. In this thesis this type of clock signal generators are analyzed and designed for different requirements on the switched capacitor (S/C) circuits. Different analytical models for the delay in CMOS inverters are studied. The clock generators for digital circuits based on phase-locked loop and delay-locked loop are also studied. An algorithm, which can automatically size the non-overlapping clock generator circuits, was implemented.

Nyckelord

Keyword

Non-overlapping clock signal generator circuits, PLL, DLL, CMOS Transistors, Delay models for CMOS circuits

Abstract

The non-overlapping clock signal generator circuits are key elements in switched capacitor circuits since non-overlapping clock signals are generally required. Non-overlapping clock signals means signals running at the same frequency and there is a time between the pulses that none of them is high. This time (when both pulses are logic 0) takes place when the pulses are switching from logic 1 to logic 0 or from logic 0 to logic 1. In this thesis this type of clock signal generators are analyzed and designed for different requirements on the switched capacitor (S/C) circuits. Different analytical models for the delay in CMOS inverters are studied. The clock generators for digital circuits based on phase-locked loop and delay-locked loop are also studied. An algorithm, which can automatically size the non-overlapping clock generator circuits, was implemented.

Acknowledgements

This thesis has been written in the Electronics Systems division, at the department of Electrical engineering, Linköping University in the master program in SoCware-Integrated Systems for Communication and Media.

I would like to give thanks to all ISY department staff, especially my supervisor Erik Säll. I am grateful for his guidance, useful advices and tolerance.

I would like to thank to all my friends in Linköping especially Marcin Dzieweczynski who is always supportive and cheerful to me. Without my beloved parent nothing would be easier in my life. Thank you for everything in my life.

Contents

1.1 Thesis Outline... 8

2.1 Structure and Operation of the MOS Transistor ... 9

2.1.1 Threshold Voltage ... 10

2.1.2 Linear Region ... 11

2.1.3 Saturation Region ... 12

2.1.4 I-V Characteristics and Current Equations of NMOS Transistor ... 12

2.1.5 Channel-Length Modulation ... 13

2.1.5 Body Effect... 14

2.2 MOSFET Small-Geometry Effects ... 14

2.1.2 Short Channel Effect ... 14

2.1.2 Narrow Channel Effect... 15

2.3 MOSFET Parasitic Capacitances ... 15

2.4 Calculation of Delay Times MOS Inverters... 16

3.1 Delay Models ... 19

3.2 One Region Model ... 20

3.3 Two Region Model... 21

3.4 Three Region Model... 23

3.5 The Alpha Power Law Model ... 25

3.6 Four Region Model ... 27

3.7 Summary ... 28

4.1 Non-Overlapping Clock Signal Generators ... 29

4.2 Delay Circuits... 36

4.2.1 Inverter Based Delay Circuits ... 36

4.2.2 Current-Starved Inverter Delay Circuits ... 36

4.2.3 RC-Inverter... 37

4.3 Phase-Locked Loop and Delay-Locked Loop based Clock Generator Circuits ... 38

Abstract ... 1

Acknowledgements... 3

1. Introduction ... 7

2. MOS Transistor... 9

3. Delay Models for CMOS Circuits... 19

4. Clock Generators... 29

4.3.1 Functional Blocks of PLL Clock Generator... 38

4.3.2 Phase/Frequency Detectors ... 39 4.3.3 Charge Pumps... 41 4.3.4 Loop Filters ... 42 4.3.5 Voltage-Controlled Oscillators... 43 4.3.6 Frequency Synthesis... 44 4.3.7 Loop Dynamics ... 45

4.3.8 Delay-Locked Loop based Clock Signal Generators ... 47

5.1 Sizing Algorithm ... 52

Bibliography... 61

5.1.1 Finding the Proper Aspect Ratio ... 52

5.1.2 Reducing the Propagation Delay... 53

5.1.3 Sizing the Delay Buffers ... 54

5.2 Results ... 55

6. Conclusions ... 58

1. Introduction

The clock signals are important for the operation of digital and analog systems. Ideally, clock signals should have zero rise and fall times, constant duty cycles, and zero skew. In reality clock signals have nonzero skews and nonzero rise and fall times. The duty cycles can also vary. For digital and analog circuits many different clock signal generator circuits are used. In switched capacitor (S/C) circuits the clock signals control the switching activities and thereby determine the whole operation of the circuit. They must guarantee that no charges are lost when the switching operation is performed. In digital circuits, phase locked loop (PLL) or delay locked loop (DLL) based clock generator circuits are designed to eliminate the clock skew. Since many digital circuits are designed to work synchronously large clock skews could destroy the data transfer between sub-blocks.

When the output signals of the non-overlapping clock signal generator are switching, there must be a time gap between them that none of them is high. This time gap between signals depends on the how much the signals are delayed in the circuit. The propagation delay of the signals depends on the size of the transistor in the non-overlapping clock signal generator circuit. Because of this fact an algorithm which can size the non-overlapping clock generator circuit is implemented in Cadence’ Ocean script program.

1.1 Thesis Outline

In chapter two important aspects of MOSFET devices are presented. Chapter three presents analytical delay models of the CMOS inverters. In chapter four non-overlapping clock signals are studied. Depending on the switched capacitor (S/C) clock signal requirements the appropriate clock signal generators are presented. The theory behind the PLL and DLL based clock generator circuits is explained. In chapter five the implementation of the algorithm, which can automatically size non-overlapping clock generator circuits is explained. In chapter six the results of the use of the algorithm and conclusions made from the results are presented.

2. MOS Transistor

2.1 Structure and Operation of the MOS Transistor

A cross section of an n-channel MOS transistor is shown in figure 2.1.1. Heavily doped n-type source and drain regions are implanted into the lightly doped p-type substrate (often called body). A thin layer of silicon dioxide is placed over the region between source and drain. The conductive material, which is polysilicon, is placed between drain and source, on top of the silicon dioxide. This forms the gate of the transistor. Neighboring devices are insulated from each other by a thick layer of field oxide [1].

A simple model of the NMOS transistor is a switch in series with resistor. When the voltage applied to the gate is larger than the threshold voltage V , a _T

conducting channel is formed between drain and source. If there is a voltage difference between drain and source, a current will flow between drain and source. The conductivity of the channel is modulated by the gate-source voltage

GS

V . If V is increased, the channel resistance will be smaller and a larger _GS

current will flow through the conducting channel. When the gate voltage is lower than the threshold voltage, no conducting channel exists, and the switch is considered open [1].

A MOS transistor that has no conducting channel at zero gate bias is called an

enhancement-mode MOSFET. If a conducting channel exists at zero gate bias,

the device is called a depletion-mode MOSFET [2].

2.1.1 Threshold Voltage

The threshold voltage is the required gate voltage needed to switch a MOSFET from a blocking state to a conducting state. If the voltage applied to the gate terminal is increased, the holes in the p-type channel are repelled, and the electrons are attracted. The positive gate voltage causes enough positive charges to be driven away so that electrons become majority on the surface of the substrate side and the p-type material (close to the gate) is inverted into n-type material. Hence a conducting channel is formed. As the voltage is increased above the threshold voltage more electrons are induced into the channel. The amount of charge induced is given by

OX GT

ch V LWC

2.1.2 Linear Region

When a voltage is applied between the drain and the source, V , an electric _DS

field is generated, which accelerates the induced electrons. The speed of the electrons is v=Eµ_n, where µ_n is the mobility of the electrons, E is the electric

field (E =V

( )

x /L), L is the length of the conducting channel and V

( )

x is the voltage at a point x along the channel as seen in figure 2.1.2. The time for one carrier to cross the channel is v/L=Eµ_n/L. The current due to the electron movement through the channel is

DS GT OX n ch n DS _L V V W C L Q E I       = = µ µ (for V_DS <<V_GT) (2.2)

Hence for small V_DS the transistor operates as a voltage controlled resistor [1, 2, 3].

2.1.3 Saturation Region

As V is increased up to the point where _DS V_DS is equal to V_GT =V_GS −V_T, the channel is pinched off and the induced charge into the channel is zero. This is shown in figure 2.1.3. A further increase of V will not change the voltage _DS

difference over the channel and the current remains constant. In saturation region the transistor works like a current source, since an increase of the gate voltage increases the current flow through the channel.

Figure 2.1.3 Transistor in saturation.

2.1.4 I-V Characteristics and Current Equations of the NMOS transistor

The current-voltage relation in the linear region for long channel device can be expressed as T GS DS V V V ≤ − (2.3)

(

)

_      − − = 2 ' DS2 DS T GS n D V V V V L W k I (2.4)

with ox ox n OX n n C _t

k' =µ = µ ε (process dependent transconductance parameter). The current-voltage relation in the saturation region for long channel device can be expressed as T GS DS V V V ≥ − _D n

(

V_GS V_T

) (

V_DS

)

L W k I = − 1+λ 2 ' 2 _{, (2.5)}

where λ is a constant included into the equation to model the channel-length

modulation. This will be explained in section 2.1.5.

Figure 2.1.4 Regions of operations for an NMOS transistor [8].

2.1.5 Channel-Length Modulation

A MOSFET transistor operated in the saturation region is not an ideal current source. As V increases the depletion region at the drain junction grows, _DS

reducing the effective channel length. This results in a finite output impedance of the current source. As a result I_DS increases withV . _DS

2.1.6 Body Effect

The threshold voltage of a device increases as the bias voltage between the source and body terminals, V , is increased. This bias voltage increases the _SB

amount of depletion layer charges that must be displaced to form a conducting channel. Hence, the threshold voltage is increased. This gives the following expression for the threshold voltage

( )

[

(

)

1/2

(

)

1/2

]

0 2 F SB 2 F T SB T V V V V = +γ φ + − φ , (2.6)

where φ_F is the Fermi potential of the material [3].

2.2 MOSFET Small-Geometry Effects 2.2.1 Short-Channel Effect

If the threshold voltage is plotted as a function of the channel length of the MOS transistors it is seen that the threshold voltage decreases with L for very small geometries. This is because of the charge sharing between drain/source and the gate. For a long channel device the depletion charge regions near the source and the drain are a small fraction of the total depletion charge underneath the gate. However, as the channel lengths are reduced, the shared charges become a larger fraction of the total charge which results in a V roll-off for decreasing L. _T

The electric field in the channel increases when the channel length is decreased, which saturates the carrier velocity. The carrier velocity saturation reduces the saturation mode current below the current value predicted by the conventional long-channel current equations. The current is not dependent on channel length and the current equation is a quadratic function of the gate-to-source voltage

GS

( )sat d sat ox DSAT

D W v C V

I = × _{( )} × × , (2.7)

where v_{d( )sat} is the saturated carrier velocity [1, 2, 3].

2.2.2 Narrow-Channel Effect

Another effect is the narrow-channel effect, where V increases as the channel _T

width is reduced in narrow devices. In the short-channel effect the effective depletion charge is reduced due to charge sharing with the source/drain. However, in the narrow-channel effect the depletion charge belonging to the gate is increased. The effect is not important for wide devices [2].

2.3 MOSFET Parasitic Capacitances

The dynamic behavior of a MOSFET is determined by the time it takes to discharge and charge the capacitances between the device terminals and interconnecting lines. The MOSFET parasitic capacitances originate from the basic structure of the MOS transistor, the channel charge and the depletion regions near drain and source. The parasitic capacitances of MOSFET devices are due to the gate capacitance and the source/drain junction capacitance. The values of most of these capacitances change with the operating voltage.

L C C C_GS = _GSO + _OX × 2 1 Linear Region (2.8) L C C C_GS = _GSO + _OX × 3 2 Saturation Region (2.9) L C C C_GD = _GDO + _OX × 2 1 Linear Region (2.10) GDO GD C C = Saturation Region (2.11)

(

L W

)

C W L C

All parasitic capacitance can be combined into a single capacitance model for the MOS transistor, which is shown in figure 2.3.1.

S D B G GS C C_GD DB C SB C

Figure 2.3.1 MOSFET capacitance model.

2.4 Calculation of Delay Times for MOS Inverters

The propagation delay means the delay experienced by a signal when passing through the logic gate [3]. It is measured between the 50% transition point of the input and output waveforms, as shown in figure 2.4.1. The 50% point of the input and output waveforms is chosen because the transition point V is_M mostly located in the middle of the logic swing. An inverter has different response time for a low to high output transition (t_pLH) and high to low output transition (t_pHL). The overall propagation delay (t ) is computed as the average of those, _p

according to pLH pHL p t t t = + . (2.13)

The circuit performance is not only characterized by the propagation delay. Other factors are also important such as the rise and fall times of the output signal (t and _r t ). They are measured between the 10% and 90% points of the _f

output waveform, as illustrated in figure 2.4.1.

pHL

t

t

_pLH in

V

out

V

t

t

f

t

t

r

Figure 2.4.1 Delay time definitions for MOS inverters.

The propagation delay of the CMOS inverter is determined by the time it takes to charge and discharge the load capacitor C . The load capacitor is composed _L

of all the parasitic capacitances including the load connected to the output. All parasitic capacitances calculated in previous section are considered individually and added together.

The propagation delay is computed by integrating the capacitor discharge and charge currents,

(

)

_       + = + ≈ ⇒ =

_∫

n p DD L pLH pHL p v v L p k k V C t t t v i dv C t 1 1 2 2 1 ) ( 2 1 . (2.14)

The derivation can be found in [3].

3. Delay Models for CMOS Circuits

Many different simulation tools are used by the circuit designers. These tools allow complex circuits to be simulated with high accuracy giving valuable aid in the design of the circuit. Simulation tools like Cadence’ Spectre circuit simulator provide accuracy by recalculating the conditions of a circuit for each small increment of time in the simulation. Such tools are very time consuming which limit the size of the circuit that can be simulated at reasonable time. Hence there is a need for analytical models for the gate delay that provides accuracy without the large amount of computation required by time-stepped simulations.

Another aspect at circuit design is optimization of the design. Numerical optimizations are computationally intensive and require significant computer time even for small circuits. In order to optimize the circuit quickly, initial size of the transistors must be provided. This chapter presents such analytical models that give initial size of the transistors which are close to the optimum solution.

3.1 Delay Models

Five different delay models are presented. Each model takes a total load capacitance C , which includes all parasitic capacitances and relates the output _T

voltage V_out

( )

t to the output current I_out

( )

t by the following differential equation

( )

( )

T DD out out C V t I dt t dV ₌ − (3.1)

Each model has a different analytical expression for the output current of the device and solves this differential equation for the output voltage as a function

of the time. The expression for the output voltage is then solved for the delay as a function of the output voltage. All these models approximate the time varying capacitance of the load by an average value. For falling transitions only the current of the NMOS device is considered and for rising transitions only the current of the PMOS device is considered. All the following derivations are for an inverter with an input signal that begins to rise at time 0 and reach the supply voltage at time T . The delay time _IN t is measured from the time the input _D

begins to change to when the output has changed by ∆V_out. The equations for the output voltage as a function of time are only valid for a rising input, but the equations for delay as a function of ∆V_out are identical for rising and falling inputs.

3.2 One Region Model

The simplest way to model the delay of a CMOS gate is to replace each transistor with an equivalent resistor. Hence the model has only one operation region, this model is called one region model. The current drawn by a device of width W is written as the output voltage across an equivalent resistance R_F/W

[Ω],

( )

( )

F out DD out _R t WV V t I = . (3.2)

For a given total capacitance C ,_T composed of all the parasitic capacitances, T _F

is the characteristic time constant of the differential equation for the output voltage. The differential equations are written as follows

W C R

( )

( )

( )

( )

F out T F out T DD out out T t V C R W t V C V t I dt t dV ₌ − ₌− ₌−

(3.4)

Solving this equation for the output voltage as a function of time and the delay as a function of ∆V_out yields,

( )

_      − = F out T t t V exp

(3.5) and       ∆ − = out F D T _V t 1 1 log . (3.6)

( )

t

V_out is a decaying exponential function and the delay increases linearly with the load. The one region model completely ignores the shape and slew rate of the input signal [6].

3.3 Two Region Model

Making the output current proportional to the input voltage and to the output voltage gives more accurate results. The input voltage is assumed to be a ramp signal, which goes from logic 0 to logic 1 at timeT , _IN

( )

_IN

in t t T

V = / . (3.7) The first region roughly corresponds to when the device is in the saturation region. Then the output current for the first region is written as a function of the equivalent resistanceR_M /W , the input voltage V_in

( )

t and the threshold voltage

T

V . The second region roughly corresponds to when the device is in the linear

region. The output current is modeled like in the one region model,

( )

(

( )

)

( )

_      − = F out DD M T in DD out _R t WV V R V t V W V t I min , . (3.8)

Solving for the output voltage and delay gives the solutions below, as functions of the two characteristic time constant T and _M T , and the time _F t when the _v

device is turned on, which means that the input voltage exceeds the threshold voltage

.

T IN v T V t = T_M =R_MC_T /W T_F =R_FC_T/W

(3.9)

(

)

IN M v T T t t 2 1 2 − −

tv <t<ts

( )

t V_out =

(

)

_      −         ₋ − F s IN M v s T t t T T t t exp 2 1 2 t_s < t (3.10)

tv + 2TMTIN∆Vout

0<tD <ts D t =

(

₍

)

₎

_      ∆ − − + out IN M F v s F s V T T T t t T t 1 log t_s< t_D

The time t , when the model switches from the first region to the second, is _s

found by setting the two expressions for current within the minimum operator of the output current equation equal to each other and setting V_out

( )

t equal to the first region solution.

F IN M F v s t T T T T t = + 2+2 − (3.12)

This model assumes that the switching device moves out of saturation before the input voltage reaches its maximum value. This is often a reasonable assumption but causes the model to underestimate the delay of gates with fast inputs and that are driving large loads [6].

3.4 Three Region Model

There are three regions in this model. The first region is when the device is in saturation and the input is rising. In the second region, the device is still in saturation and the input is constant. The third region is when the device is in linear region and the input is constant.

The input V_in

( )

t is written as a function going from logic 0 to logic 1 in time T _IN

and then remains constant,

( )

min

(

/ _IN,1

)

in t t T

V = . (3.13) The output current is identical to the one used in the two region model. The first region roughly corresponds to the saturation region. In this region the output current is written as a function of the equivalent resistanceR_M /W , input voltage

( )

t

V_in and the threshold V . In the second region, it is written as a function of _T

( )

(

( )

)

( )

_      − = F out DD M T in DD out R t WV V R V t V W V t I min , . (3.14)

Solving for the output voltage and delay gives solutions in three regions in terms of the time constants t , _v T and _M T . _F

T IN v T V t = T_M =R_MC_T /W T_F =R_FC_T/W (3.15)

(

)

IN M v T T t t 2 1 2 − −

tv <t<ts

( )

t V_out

=

(

) (

)(

)

M IN T M T IN T T t V T V T − ₋ − − − 1 2 1 1 2 T_IN <t<t_s

(

) (

)(

)

_      −         _{− −} − − − F s M IN s T M T IN T t t T T t V T V T exp 1 2 1 1 2 t_s < t (3.16) t_v + 2T_MT_IN∆V_out 0<t_D <T_IN D t =

(

)

T out M T IN V V T V T − ∆ + + 1 2 1 T_IN <t_D <t_s

(

₍

)

(

₎

(

)

)

_      ∆ − + − − − + out M T IN s T M F s _{T V} V T t V T T t 1 2 1 2 1 2 log t_s < t_D (3.17)

The transition from the first to the second region occurs at time T , when the _IN

input voltage reaches its maximum. The time t is when the model switches _s

from the second region to the third region. It is found by setting the two expressions for current within the minimum operator of the output current equation (3.14) equal to each other and setting V_out

( )

t equal to the linear region solution [6].

(

)

F T M T IN s T V T V T t − − + + = 1 2 1 . (3.18)

3.5 The Alpha-Power Law Model

In the three region model it was assumed that the output current in the saturation region is a linear function of the input voltage, which is the case for a completely velocity saturated device. For a device that is not velocity saturated the output current is proportional to the square of the input voltage. Most modern devices are somewhere between the model described in the three region model which is the case for completely velocity saturated devices and the model which describes non velocity saturated devices. For that reason a new curve fitting parameter is introduced. The output current is described by the new equation,

( )

(

( )

)

( )

_       ₋ = F out DD M t in DD out R t WV V R V t V W V t I , α , (3.19) where 2 1≤α ≤ .

This approach was first used by Sakurai and is called the alpha-power model. The same input waveform is assumed as for the three-region model [4]. V_out

( )

t

and the delay as an function of output voltage is solved as for the three region model. The use of α in the expression for the current is the only initial assumption which is different from the three region model. The alpha-power law model is thereby described by the following equations,

(

)

(

)

α α α _{M IN} v T T t t 1 1 1 + − − +

tv <t<ts

( )

t V_out

=

₍

(

₎

)

(

) (

)

M IN T M T IN T T t V T V T − − − + − − α+ α α 1 1 1 1 1 T_IN <t<t_s

₍

(

₎

)

(

) (

)

_      −         _{− −} − + − − + F s M IN s T M T IN T t t T T t V T V T exp 1 1 1 1 1 α α α ts < t (3.20) ₊α+1

(

_{α +1}

)

α_∆ out IN M v T T V t 0<t_D <T_IN D t =

(

)

(

)

α α α T out M T IN V V T V T − ∆ + + + 1 1 TIN <tD <ts

(

)

(

₍

_{) (}

) (

(

)

₎

(

)

)

_       ∆ − + + − + − − + + out M T IN s T M F s _{T V} V T t V T T t 1 1 1 1 1 log α α α α α t_s < t_D (3.21)

(

)

(

M

)

F T IN s T V T V T t − − + + + = _α α α 1 1 . (3.22)

If α=1 the model is the same as the three region model. The value of α is found by comparing the drain current of the device at different gate voltages, as in the following equation [4, 5, 6],

(

)

(

) (

)

[

V_G VD_T VD_G V_T

]

I I − − = 2 1 2 1 / log / log α . (3.23)

3.6 The Four Region Model

In the two-region model the device leaves the saturation region before the time

IN

T . In the three-region model it was assumed that the device leaves the

saturation region after T_IN

.

A new model is developed by first comparing t , as _s

given in the two region model, to T . When the device switches from the first _IN

region to the second region the two region model equations are used, otherwise the three region equations are used. Because the first regions of these models are the same, they combine to give four delay equations [6].

t_v + 2T_MT_IN∆V_out

tD <TIN

tD < ts1

(

)

T out M T IN V V T V T − ∆ + + 1 2 1

ts1 >TIN

TIN <tD <ts2 D t

=

(

₍

)

₎

_      ∆ − − + out IN M F v s F s _{T T V} T t t T t 1 log 1 1 ts1<TIN ts1<tD

(

)

₍

(

₎

(

)

)

_      ∆ − + − − − + out M T IN s T M F s V T V T t V T T t 1 2 1 2 1 2 log 2 2

ts1 >TIN

ts2 <tD (3.24)

3.7 Summary

The one region model is the simplest one since it has only one current fitting parameter R . The slope of the input waveform is not considered in that model. _F

The accuracy it provides is poor when it is compared with the results of the SPICE simulations. The two-region model includes the effect of the input waveform and it requires the three curve-fitting parameters V_T,R_M and R . The _F

accuracy is better than the one region model. The three-region model provides better accuracy than the two region model with the same curve-fitting parameters. The three region model is the special case of the alpha-power law model. The four-region model combines the two region and three region models. It has the same accuracy as the three region model if the effect of the wire resistance is not considered, otherwise it provides better accuracy [6].

4. Clock Generators

4.1 Non-Overlapping Clock Signal Generators

Clock signals are essential for switched-capacitor circuits. The clock signals must in general be overlapping to guarantee that charge is not lost. A non-overlapping clock signal generator with two output clock signals may be constructed from inverters, NAND gates and two delay elements as illustrated in figure 4.1.1.

clk in

clk 2

clk 1

Figure 4.1.1 A basic non-overlapping clock signal generator circuit.

The delay elements are buffers of such dimensions so that the delay between Φ ₁ and Φ , ₂ t , is equal to the delay between _d1 Φ and ₂ Φ , ₁ t , as shown in figure _d2

1 Φ 2 Φ 1 d t t_d2 Input clock signal

Figure 4.1.2 Waveform obtained from figure 4.1.1.

The required signals for the S/C circuits can be different from topology to topology. For instance as in figure 4.1.3 the clock signal Φ is equal to ₁ Φ , but ₃ somewhat delayed compared to Φ , and ₃ Φ is the inverse of ₂ Φ . ₁

If Φ goes high before ₂ Φ₁ and Φ goes low, which could happen if the clock ₃ signals are overlapping, the potential on both sides of C in figure 4.1.3 would _S

be the same. The voltage appearing on the output during the hold mode would then not be equal to V . This is why it is important to have non-overlapping _in

clock signals in this particular case and the same or similar reasons are found in many other circuit topologies [15].

clk in 3

Φ

2

Φ

1

Φ

Figure 4.1.4 Clock signal generator circuit for the required clock signals in figure 4.1.3.

1 Φ 2 Φ 3 Φ td1 td2 t_d3 Input clock signal

The signals in figure 4.1.7 are the required clock signal for the circuit in figure 4.1.6. These clock signals can be created according to below.

1. It must be assured that the input clock cycle has 50%-50% duty cycle. This can be obtained by a positive edge triggered D flip-flop.

2. The time delay between Φ and ₁ Φ can be obtained by a delay ₂ element.

3. Φ , which has shorter pulse width than _1p Φ , can be obtained by using ₁ a NOR gate whose inputs are Φ and the output of the NAND gate. ₁ 4. Φ , which makes transition at the rising edge of ₄ Φ , can be obtained ₂

by a positive edge triggered D flip-flop, a delay element and an XOR gate.

5. Φ is a delayed version of _4d Φ . ₄

6. Φ , which makes transition at the falling edge of ₃ Φ , is obtained by ₄ similar methods as used when obtaining Φ . ₄

1 C 3 Φ Φ₁ 2 Φ 2 C dg C 1 Φ 2 Φ 2 Φ C_hold Φ₂ p 1 Φ store C 4 Φ Φ4d 1 C Φ3 2 Φ 1 Φ store C Φ1p 2 Φ 4 Φ hold C d 4 Φ 2 Φ dg C _Φ1 2 Φ 2 C + out V − out V + in V − in V + in V − in V + in V − in V

p 1 Φ 1 Φ 2 Φ 3 Φ 4 Φ d 4 Φ p t₁ 1 d t t_d2 3 d t Width of the pulse Input clock signal

Figure 4.1.7 Clock signals required for the T/H circuit in figure 4.1.6.

4.2 Delay Circuits

4.2.1 Inverter Based Delay Circuits

A MOS inverter can be used as a simple delay element and different delay can be obtained by cascading a number of inverters, as illustrated in figure 4.2.1. This type of delay elements has two major drawbacks.

• Many stages will be needed to realize a long delay if the delay difference between two buffers is small.

• The minimum delay adjustment step that is possible in a given technology is about two inverter delays using minimum size transistors. This is often too coarse for high-precision low-jitter applications [2].

in } : 0 { n sel 0 d d1 n d

Figure 4.2.1 Inverter based delay circuit [1].

4.2.2 Current-Starved Inverter Delay Circuits

The fundamental circuit elements generating delay in an inverter delay chain are MOSFET current sources charging MOSFET gate capacitances. If the current that charges and discharges this capacitor is restricted by current control transistors in series with the switching transistors in the inverters, as in figure 4.2.2, a delay element with adjustable delay is obtained [1].

p S k• n S k• CP

V

in

p S n S CN V out

Figure 4.2.2 Current-starved inverter delay circuit [1].

4.2.3 RC-Inverter

In the RC inverter circuit in figure 4.2.3 M1 is a PMOS transistor. Its bulk is connected to VDD and it is kept in the turned on state to work as a resistor. M2 is an NMOS that acts as a capacitor. These two transistors control the required RC delay. The two transistors to the right (M3 and M4) act as a CMOS inverter. The RC inverter behaves as an inverter with long rise and fall time [14].

4.3 Phase-Locked Loop and Delay-Locked Loop Based Clock Signal Generator Circuits

As the clock frequency of the integrated circuits continues to increase, distributing clock signals across the analog or digital systems and making sure that every component in the system is synchronized becomes very important issues. One way to solve the clock synchronization problem is to use an on-chip phase-locked loop (PLL) for clock generation. The PLL can generate an on-chip clock that is phase-locked to the off chip clock.

4.3.1 Functional Blocks of PLL Clock Generators

There are many types of PLLs for different applications. Some are designed to handle analog signals and consists entirely of analog circuits. Others are composed only of digital circuits. However most PLLs designed for clock generation and synchronization have both analog and digital circuits.

An example of PLL clock generator is shown in figure 4.3.1. The off-chip reference clock is first buffered and then connected to the phase detector. The other input to the phase detector is the on-chip clock generated by the voltage-controlled oscillator (VCO). The phase detector detects any phase difference between the input clock and the VCO clock and generates control signals for the charge pump to correct the phase difference. The control signals generated by the phase detector are used by the charge pump to modulate the amount of charge stored in the low-pass filter. In turn, the output voltage of the low-pass filter controls the oscillator frequency. The divide-by-N divider multiplies the off-chip reference clock frequency for higher on-chip clock frequency (see section 4.3.6). Next, functional blocks and the design considerations will be discussed.

BUFFER PHASE DETECTOR CHARGE PUMP LOW PASS FILTER VCO divide-by-2 divide-by-N Off-Chip Reference Clock On-Chip Clock

Figure 4.3.1 A typical phase-locked loop for clock generation and synchronization.

4.3.2 Phase/Frequency Detectors

A circuit that can detect both phase and frequency difference proves extremely useful because it significantly increases the acquisition range and locking speed of PLLs. The frequency detection capability can shorten the initial time for frequency lock-in. However, phase detection is required if the input is not a periodic waveform, which is the case in data communications. Fortunately for clock synchronization the input is always a periodic waveform.

Basically the outputs of a phase/frequency detector are two control signals called UP and DOWN. If the voltage controlled oscillator (VCO) clock is leading the reference clock, the voltage controlled oscillator has to slow down, hence the DOWN signal is activated. When the voltage controlled oscillator clock is lagging the reference clock the voltage controlled oscillator has to speed up. The UP signal is then activated. The advantage of the phase/frequency detector is that neither the UP signal nor the DOWN signal is activated when the PLL is in locked condition. Hence the phase/frequency detector is in a tri-state condition

since none of the control signals are activated when the loop is in the locked condition.

A possible implementation of the phase/frequency detector is shown in figure 4.3.2. The circuit consists of two edge-triggered resettable D flip-flops with their inputs connected to logical ONE. There are two input signals, one of them is the reference clock, and the other is the output of the VCO. These signals are input to the clock input of the D flip-flops. If both outputs are logical ZERO, a transition on the first flip-flop causes its output to go high. Subsequent transitions of the first flip-flop have no effect on its output and when the input of the second flop goes high the AND gate activates the reset input of the flip-flops. Thus both outputs are simultaneously high for a time given by the total delay through the AND gate and the reset path of the flip-flops. To illustrate the function of the phase/frequency detector the outputs of the circuit for different inputs are shown in figure 4.3.3.

CLK D Q 1-DFF CLK D Q 2-DFF O NE O NE Reset UP DO W N

Figure 4.3.3 (a) The reference clock is leading the VCO clock, both having the same frequency. (b) The VCO is leading the reference clock, both having the same frequency. (c) The reference clock is leading the VCO clock and there is a frequency difference between the reference clock and the VCO clock. (d) The VCO clock is leading the reference clock and there is a frequency difference between the reference clock and the VCO clock.

4.3.3 Charge Pumps

The output signals from the phase/frequency detector are used to control the charge pump. The purpose of the charge pump is to generate the control voltage of the VCO by adding and removing charges that are stored in the low-pass filter. This suppresses high frequency components in the phase/frequency detector output, allowing the dc value to control the VCO frequency. The charge pump shown in figure 4.3.4 works as follows. When the UP and DOWN signals switch either the current source I or _up I is connected to node _dn V_control, thus delivering or removing a charge, which moves V_control UP or DOWN. I_up and I_dn

must be equal in magnitude. When the nodes N1 and N2 are not connected to

sharing from the parasitic capacitances on N1 and N2 that can cause mismatch between the UP and DOWN current sources.

The phase/frequency detector and charge pump circuits provide a transfer function from the input phase error to the output charge. This transfer characteristic must be controlled over supply, temperature and process variations since it determines the clock skew [10].

Figure 4.3.4 Charge pump [10].

4.3.4 Loop Filters

The loop filters are simply RC filters. In some cases a first order filter may be sufficient. However in many designs additional high-frequency poles are added in order to filter out the ripple noise generated by the charge pump. Furthermore, the VCO will introduce a pole at the origin because its output phase is an integration of the frequency over the time. As a result a zero is needed in the filter to compensate for the poles and provide enough phase and gain margins in the loop. This zero will also introduce an additional time constant in the loop,

which allows the designer to choose the damping factor and the natural frequency of the loop independently. In real designs many additional high-frequency poles and zeros may exist because of the stray capacitances and resistances. The locations of the poles and zeros must be carefully analyzed to ensure the stability of the loop. The detailed stability analysis can be found in [9].

4.3.5 Voltage-Controlled Oscillators

The voltage controlled oscillator (VCO) is the key component in a PLL design. It takes the control input V_f and produces a periodic signal with frequency

VCO VCO

c k V

f

f = + , where f_c is the center frequency of the VCO and k_VCO is its

gain. The major design considerations of VCOs are linearity, tuning range, maximum speed, duty cycle, VCO gain, and noise performance. A linear transfer function is desirable because it makes the overall behavior of the PLL predictable and the design task much easier. The tuning range and maximum speed of the VCO depend on the requirements of the application. It is diffucult to attain a waveform with a 50-percent duty cycle at the output of the VCO. The common practice to get a 50-percent duty cycle is to double the VCO frequency and divide by two, which means that the VCO has to operate at double frequency of the clock signal. The VCO gain is the amount of frequency change caused by a given amount of control-voltage change. This is another important parameter that determines the overall loop gain. This parameter may also vary with the process and operating conditions. Hence it must be carefully designed. Ring-oscillators can function as a VCO. The VCOs are then mostly implemented as current-starved ring oscillators (see figure 4.3.5). If the control voltage increases, both the charge current and the discharge current increases because of the higher gate to source voltage. Consequently, the VCO will oscillate at a higher frequency.

Figure 4.3.5 Voltage controlled oscillator based on current starved inverters.

The most difficult part when designing a VCO is to make sure that the VCO can reject noise effectively. The digital circuits on the same chip will create switching noise, which can introduce excessive jitter at the VCO output. There are also other approaches when designing VCOs, like having no feedback path at PLL design. Because of the feedback in VCO, any transient disturbance introduced in the circuit will be recirculated. The drawback of this type of circuits is that the output and input frequencies must be the same, which is hard to obtain [10].

4.3.6 Frequency Synthesis

In VCO based PLLs the output frequency can be changed by programmable divide-by-N blocks, which allows lower frequency crystals to be used off chip. They, in turn, produce lower RF radiation. Since the frequency divider will be a part of the loop gain, changing N will alter the phase and gain margins of the loop. This must be taken into consideration to make sure that the PLL is stable over the whole frequency range of operation.

4.3.7 Loop Dynamics

The transient response of the phase-locked loops is in general nonlinear and cannot be formulated easily. Nevertheless, a linear approximation can be used to understand the trade-offs in PLL design. Figure 4.3.6 shows the linear model of the PLL with the transfer function. The overall transfer function is

( )

( )

_{( )}

(

)

K s K s s K s s s H data clk + + + = Φ Φ = τ τ 2 1 , where K = K_PFDK_VCO. 4.1

∑

Data

Φ

Clk

Φ

PFD

K

τ s _s+ 1

s

K

_VCO

/

input VCO

+

−

Figure 4.3.6 Linear model of PLL.

The system is of second order where the quantity K = K_PFDK_VCO is the loop gain. The magnitude of the transfer function H

( )

s , which is also called jitter transfer function, exceeds unity over some frequency range due to the closed-loop zero at a frequency lower than that of the poles. This gain in excess of unity is undesirable in systems that employ many clock recovery units in cascade because of the resulting exponential growth of the jitter. The solution is to increase the damping factor ξ to reduce the spacing between the zero and the lowest pole. This can be seen in a locus analyze of the system. In the root-locus there are two poles at the origin when K is zero. When it starts increasing, both poles depart from the origin and move on a circle in the left half plane eventually returning to the real axis for sufficiently high gain (see figure 4.3.7).

τ

/ 1 − τ / 2 − Arrows in direction of increasing K

ω

j

σ

Figure 4.3.7 Root locus for a second-order PLL [12].

However, the amount of jitter peaking can be reduced but never completely eliminated since the zero always occurs at a lower frequency than the poles. The problem of jitter peaking can be eliminated if the necessary loop-stabilizing zero can be moved to a frequency higher than that of the lowest frequency pole. One possibility is to move the necessary loop-stabilizing zero out of the forward path so that there is no closed-loop zero.

Another possibility is to employ a loop of a different order, as in figure 4.3.8. This third order loop allows placement of the zero as desired but the conditional stability of such loops makes them difficult to use [9, 11, 12].

Figure 4.3.8 One possible root locus for a third order PLL [12].

4.3.8 Delay-Locked Loop Based Clock Generators

As mentioned in the previous chapter the PLL is a higher order system and it is difficult to design. Delay locked loop (DLL) based clock generators have several advantages over conventional PLL based clock generators. The DLL is a first order system and, thus, easier to design. Although they have this advantage, they are seldom used. The main reason is the difficulty of frequency multiplication using a voltage controlled delay line. The delay locked loop system is shown in figure 4.3.9 [9].

Figure 4.3.9 Delay locked loop.

The phase detector compares the desired input delay D with the delay through _in

output of the loop filter is V_C =ω_in

(

D_in −D_out

)

K_PDL

( )

s . Only one single pole is needed to stabilize the DLL. The loop filter is in the form of 1/sRC. The transfer function is 1 / 1 1 ω s D D in out + = , where RC K K_{PD VCDL}ω_In ω₁ = . (4.2)

5. Design

In the design part an algorithm which can size the non-overlapping clock generator circuits is implemented. The design specifications for that algorithm are the frequency of the input clock signal and transistor technology models for the 0.18 µmor 0.35 µm technologies.

The netlist of the circuit was created using Cadence affirma analog design environment for each technology since every technology has different transistor models. When the OCEAN (Open Command Environment for Analysis) script runs, circuit variables are sent to the Spectre simulator and the simulation results are sent back. This continues until the output meets with the requirements.

The OCEAN script program starts by choosing CMOS technology. Available CMOS technologies are a 0.35 µm CMOS technology and a 0.18 µm CMOS technology. After that input clock signal is defined by the user. Model files are called from library. The maximum delay between two output clock signals is defined depending upon the chosen input clock frequency. This is 1/5 of the input clock signal pulse width. Variables of the circuit, such as channel width and channel length of the transistors are initialized. These variables are in the netlists of the circuits which the Spectre simulator uses for simulation. When sizing the transistors in each circuit element, first proper aspect ratio is found, then the propagation delay of the transistors is decreased below 100 ps. This is applied to every circuit element. The channel widths of each transistor are sized in this order, INV-in (inverter before the NAND gates), buffer, NAND gate, INV-out (inverter after the buffers). The channel lengths of the transistors in the buffers are sized last since the delay is obtained by this part of the program (see figure 5.2).

5.1 Sizing Algorithm

5.1.1 Finding the Proper Aspect Ratio

The aspect ratio of the MOS inverters and the other digital gates differs from technology to technology. In order to have identical rise and fall time the proper aspect ratio (W_p/W_n) must be found. The generated circuit netlist is simulated the first time with minimum sizes and the measured rise and fall times are compared. If the rise time t_pLH is longer than the fall time t_pHL the current through the PMOS transistor charging the parasitic capacitances of the transistor is smaller than the discharge current through the NMOS transistor. Hence the size of the PMOS transistor is increased and the circuit is simulated again using the OCEAN script. If the fall time is longer than the rise time the current through the NMOS transistor is smaller than the current charging the parasitic capacitances of the transistor. In this case the size of the NMOS transistor is increased. The measured rise and fall times coming from the simulator are rounded to the integer with the accuracy of 1/100 before they are compared. This iteration continues until the rounded values of t_pHL and t_pLH is equal. This algorithm is applied to every circuit element in the topology to get identical rounded rise and fall times.

The ratio of the NAND gates W_p/W computed by the OCEAN script is _n

different from the expected, since the NAND gate’s inputs have two signals with different propagation delays. One is the input clock signal and the other is propagated through the delay buffers. The difference between the propagation delays of these signals directly effects the rise and fall times of the output of the NAND gate. The size of the PMOS and NMOS transistors affects the aspect ratio of the NAND gate as well.

5.1.2 Reducing the Propagation Delay

When the circuit is working for higher frequencies the propagation delay t_p

introduced by the circuit elements, except the delay introduced by the delay buffer, must be minimized. There is a certain time when both the clock signals are low, which is given by the delay of the signal through the NAND gate, the delay buffers and inverters. This dead time between the clock signals is defined as 1/5 of the input clock signal pulse width. For instance when the input signal is higher than 1 GHz this time will be less than 100 ps. Even without any delay buffers this time will be exceeded by the delay of the other circuit elements which will distort the output clock signals. The maximum operating frequency differs from technology to technology.

As expected the inverter having minimum channel width and minimum channel length has larger propagation delay than an inverter having larger channel width and minimum channel length. The rise and fall times of the signal is reduced by increasing the channel widths of both the NMOS and PMOS transistors. Above some certain channel width the rise and fall times are not reduced anymore. In fact increasing the channel width increases the propagation delay due to an increase of the parasitic capacitances. Hence the channel width of the transistors should be optimized. The maximum propagation delay introduced by the circuit elements is defined to 100 ps. 100 ps is chosen because it is a moderate propagation delay for a simple inverter using the 0.35 µm technology but there is no strict rule what it should be. The channel width of the transistors is increased until the propagation delay is reduced below 100 ps. When the delay goes below 100 ps the channel width is not increased anymore. This algorithm is applied to every circuit element in the circuit to have a propagation delay smaller than 100 ps. The transistors of the 0.18 µm technology can meet with this criterion with the minimum channel width. This is not the case for the 0.35

µm technology, since the 0.18 µm technology allows designing faster circuits than 0.35 µm technology.

5.1.3 Sizing the Delay Buffers

To get sufficient delay from the buffer, the channel lengths of the inverters are increased. In section 5.1.2 the propagation delay is reduced by increasing the channel width but after the channel width reaches a certain value further increase increases the propagation delay t_p. However this channel width is too big for the layout of the circuit. Hence, it is not efficient if it is compared to increasing the channel length. This can be explained by the following equations,

(

)

_       + = + ≈ ⇒ =

_∫

n p DD L pLH pHL p v v L p k k V C t t t v i dv C t 1 1 2 2 1 ) ( 2 1         ′ + ′ × =         + n n p p DD L n p DD L W k W k V L C k k V C 1 1 2 1 1 2 5.1

Increase of the channel width increases the total capacitance C (using a simple _L

capacitance model which combines all parasitic capacitances, see chapter 2.3) of the inverter which increases the propagation delay t_p. However, it also increases the gain factors k_p and k of both NMOS and PMOS which decreases the delay _n

(see the equation above). The increase of channel length increases the total capacitance C and which is proportional to the delay _L t in the equation above. _p

Hence it is much more efficient to increase the channel length than increasing the channel width. Until the defined delay is met, which is 1/5 of the input clock signal pulse width, the channel length is increased by the OCEAN script.

5.2 Results

In order to get the desired delay from the circuit shown in figure 5.3 the channel lengths of the delay buffers are increased until the defined delay is reached. It is noticed the channel length of the delay buffers are the same for both technologies when the circuits are running at the same clock frequency. However, the channel widths are different and they have different aspect ratios. For the 0.18 µm technology the channel widths are the same for different frequencies but for the 0.35 µm technology they are not. For higher frequencies the channel widths of the devices using the 0.35 µm technology need to be larger. Larger channel widths reduce the propagation delay (see section 5.1.2). In turn, it means that the transistors with larger channel widths can work at higher frequencies. These results show that transistors in the 0.18 µm technology can work for higher frequencies than the transistors in the 0.35 µm technology.

Figure 5.3 Sized circuit.

The algorithm is working if the initial channel widths are chosen properly. The initial channel widths are (expressed as the ratio W_p/W_n) for the 0.18 µm technology for buffers and inverters 3 µm / 1 µm and for NAND gates 3 µm / 2 µm and for the 0.35 µm technology for buffers and inverters 30 µm / 10 µm and for the NAND gates 30 µm / 20 µm. For the same number of inverters in the buffer the circuit for the 0.18 µm technology is working for frequencies up to

1.5 GHz. Above this the delay introduced by the buffers distorts the output signal. However the circuit for the 0.35 µm technology is working for frequencies up to 800 MHz. Above this the delay introduced by the buffers distorts the output signal as well. In order to make the circuit work for higher frequencies the number of inverters in the delay buffers should be decreased.

Table 5.1 Results of the sizing algorithm for the 0.18 µm technology. 0.18 µm CMOS Technology INV-in (W_p/ W_n) INV-out (W_p/ W_n) NAND (W_p/ W_n) Buffer (W_p/ W_n) Lenght 3.1 µm /1.3 µm 100 MHz 3 µm / 1.4 µm 3.6 µm / 1.8 µm 2.2 µm / 1.7 µm L=1.05 µm 3.1 µm / 1.3 µm 500 MHz 3 µm / 1.4 µm 3.6 µm / 1.8 µm 2.2 µm / 1.7 µm L=0.35 µm 3.1 µm /1.3 µm 1 GHz 3 µm / 1.4 µm 3.6 µm / 1.8 µm 2.2 µm / 1.7 µm L=0.18 µm

Table 5.2 Results of the sizing algorithm for the 0.35 µm technology. 0.35 µm CMOS Technology INV-in (W_p/ W_n) INV-out (W_p/ W_n) NAND (W_p/ W_n) Buffer (W_p/ W_n) Lenght 39.6 µm / 11 µm 100 MHz 40.4 µm / 10 µm 49.1 µm / 10 µm 30.7 µm / 20 µm L=1.05 µm 50.83 µm / 13 µm 500 MHz 37.3 µm /10 µm 48.2 µm / 10 µm 36 µm / 24 µm L=0.35 µm 60.8 µm /16 µm 800 MHz 38.2 µm / 10 µm 45 µm / 10 µm 43.3 µm / 29.3 µm L=0.35 µm

58

6. Conclusions

The clock signals for switched capacitor circuits are different according to the requirements of the switched capacitor circuits. There are two main clock signals and all other signals are derived from these by using the flip-flops and delay elements (see section 4.1).

Modeling the delay in CMOS inverters requires a set of analytical equations, which were presented in chapter 3. They were used to predict the delay as close as possible to the values computed by the SPICE models or other simulation tools.

The Ocean script sizes the the transistors in non-overlapping clock signal generator circuits depending on the design specifications. The sizing algorithm is working for the 0.35 µm CMOS technology and the 0.18 µm CMOS technology. In order to make the OCEAN script work for the new technologies the initial size of the transistor must be chosen properly and step size to increment the channel widths or the channel lengths of the transistors in the OCEAN script must be defined accurately depending on the chosen technology. When switching from the 0.35 µm technology to the 0.18 µm technology the highest frequency that the circuit can work at is increased. The delay of the signal is much higher for the 0.35 µm technology than the 0.18 µm technology. The channel width of the transistors is approximately scaled down by ten. It is observed that increasing the channel length in order to increase the delay is much more efficient than increasing the channel width.