Fault current injection from power electronic interfaced devices

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IN

DEGREE PROJECT

ELECTRICAL ENGINEERING,

SECOND CYCLE, 30 CREDITS

,

STOCKHOLM SWEDEN 2020

Fault current injection from power

electronic interfaced devices

SANDRA THENGIUS

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Fault current injection from power

electronic interfaced devices

Sandra Thengius

Master’s thesis in electrical power engineering

Date: September 20th, 2020

Svenska Kraftnät supervisors: Robert Rogersten & Viktor Weidenmo

KTH supervisor: Robert Eriksson

Examiner: Nathaniel Taylor

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Abstract

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Sammanfattning

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Acknowledgements

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Abbreviations

AC Alternating Current

CIG Converter Interfaced Generation

DC Direct Current

DFIG Doubley-fed Induction Generator

ENTSO-E European Network of Transmission System Operators for Electricity

EU European Union

HVDC High Voltage Direct Current IGBT Insulated Gate Bipolar Transistor LCC Line-commutated Converters Transistor MMC Modular Multilevel Converters

PCC Point of Common Coupling

PEID Power Electronics Interfaced Devices

PLL Phase-Locked Loop

RfG Requirements for Generators

RMS Root Mean Square

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Introduction

1.1 Background

Increased penetration of renewable energy sources (RES) and HVDC links leads to a decreased share of synchronous generators in the power system. It is expected that synchronous generators will gradually be replaced by RES in the future [1], particularly in some areas and during some hours. RES such as wind power and solar power, and HVDC links, usually include power electronic interfaced devices (PEIDs). Generation based PEID are sometimes called converter interfaced gen-eration (CIG). Having more synchronous generators replaced by PEIDs results in a changed power system behaviour. As a result, power system protection challenges, power quality issues and effects on transient stability arise. These effects are related to the lower contribution of short circuit power from PEIDs compared to the short circuit power from synchronous generators. During a fault in the power system, synchronous generators respond inherently by injecting a fault current into the system. The injected fault current is typically 3-6 p.u. (sometimes around 10 p.u.) [2] for low impedance faults at the terminals of the synchronous generator. Based on data from Svenska Kraft-nät, converters are usually capable of injecting a current up to 1.1 p.u. during a low impedance fault. The injected current from a PEID is dependent on requirements in grid codes, manufacturer’s design principle, type of fault, initial operating conditions, and voltage limits.

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fault current injection from power park modules and HVDC links in the regulations “establishing a

network code on requirements for grid connection of generators” (NC RfG) in articles 20.2 (b) and

(c) [3] and “establishing a network code on requirements for grid connection of high voltage direct

current systems and direct current-connected power park modules” (NC HVDC) in article 19 [4].

The European Network of Transmission System Operators for Electricity (ENTSO-E) recommends TSOs to define requirements concerning fault current injection from generating modules [5]. Still, requirements in national grid codes concerning fault current injection may not be detailed enough or non-existent.

Unknown effects of increasing share PEIDs in the power system and unclear grid codes are the reasons why it is important to investigate the characteristics of the fault current injection from PEIDs.

1.2 Objectives

The aim of this thesis is to increase the knowledge about fault current injection from PEIDs. This thesis compiles and analyses information about fault current injection from PEIDs with the purpose of giving a better comprehension of the subject. Also, this thesis intends to describe how a larger share of PEIDs in the future can affect the power system performance. The main objectives are:

• To describe and highlight the differences between fault current injection from synchronous generators and PEIDs during 3-phase faults and single line-to-ground faults.

• With respect to fault current levels in the power system, to describe potential consequences of decreased penetration of synchronous generators, i.e. increased penetration of PEID.

• To illustrate with results from simulations, how power system issues can be mitigated by fault current injection from PEIDs.

• To propose general requirements concerning fault current injection from PEIDs that can help to mitigate identified issues. The requirements are intended to give guidance and suggestions when formulating grid code requirements.

1.3 Motivation and problem description

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is described in section 3.1. Also, the weaker power system leads to deeper voltage sags during a fault. For some industrial consumers, voltage sags are the most important power quality issue [6]. Sensitive equipment commonly used in semiconductor industry, paper industry and steel industry can experience sustained interruption due to voltage sags. This can lead to economic losses due to production stoppage, damaged equipment and processes, faulty products, delayed deliveries and less satisfied customers [7]. Other effects of increasing share of PEIDs which are related to short circuit faults are overvoltages during unbalanced faults, cascade effects and decreased transient stability.

The described effects of having more synchronous generators replaced by PEIDs can be mitigated by formulating suitable requirements in the national grid code. However, today’s requirements in national grid codes concerning fault current injection are generally not detailed enough or non-existent. One reason for this is insufficient knowledge about the system behaviour of a PEID-dominated grid. Traditionally, synchronous generation dominates in the power system. Hence, the power system is better adapted for grids with high share of synchronous generators. The aim of this thesis is therefore to increase the knowledge about fault current injection from PEIDs by achieving the goals mentioned in section 1.2. This thesis also discusses if requirements in national grid codes concerning fault current injection are necessary.

1.4 Scope and Limitations

This thesis focuses on fault current injection from PEIDs and the effects of increased number of syn-chronous generators replaced by PEIDs. Only low impedance faults are considered. High impedance faults are out of the scope. In simulations, the faults last for 100 ms. Faults lasting for very short or prolonged periods can affect the result and conclusions. These faults are out of the scope. For exam-ple, faults lasting for shorter time than the response time of the control system of the synchronous generator and the PEID can affect the result.

The effects described in this thesis are related to short circuit faults which occur during short time intervals. Other effects related to decreased inertia, frequency stability issues, less damping and effects on small signal stability are therefore out of the scope of this thesis. However, these effects are encouraged to be included in future works as mentioned in section 7.2.

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of the VSC-HVDC is described.

Effects of higher share PEIDs are discussed in the thesis. However, the scenario of 100 % PEIDs is out of the scope. Synchronous generators establish stable voltage and frequency. This allows PEIDs to remain synchronized to the power system. In other words, the PEIDs are characterized as “grid-following”. Having a grid operating with 100 % PEIDs require “grid-forming” converters. Grid forming converters are capable of generating AC voltage of a defined magnitude and frequency [8]. This thesis only describes grid-following PEIDs. Consequently, the scenario of 100 % PEIDs is out of the scope.

1.5 Outline

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Chapter 2

Fault currents in a power system

2.1 Voltage sags caused by short circuit faults

Voltage sags, also called voltage dips, are characterized by a RMS voltage reduction during a short time. According to the IEEE 1346-1998 Standard [9], voltage sags last around 0.5 cycle to 1 minute. Voltage sags are caused by starting of motors, overloads, short circuit faults [10] and energization of large transformers. The duration of a voltage sag caused by a short circuit fault depends on how fast the power system protection clears the fault. In this thesis, only voltage sags due to short circuit faults are investigated.

The magnitude of the voltage sag is determined by the lowest measured RMS value. However, no prevalent agreements on how to quantify the magnitude exist. One common method is to express the magnitude as the percentage of the nominal voltage [10]. For example, a 60 % sag in a 400 kV system implies that the voltage has dropped by 40 % (to 240 kV), not that it has dropped by 60 % (to 160 kV).The voltage sag is also characterized by its duration. The duration of the voltage sag is the time measured when the RMS voltage is below a determined threshold. This is shown in Figure 2.1.

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Figure 2.1: Terms related to voltage sags

at the distribution level.

Analysis of voltage sags is of interest because voltage sags are the most critical power quality issue for some industrial consumers [6]. Voltage sags can lead to malfunction of equipment and subsequently lead to sustained interruptions [7]. This results in problems for both consumers and producers which is discussed more in section 3.2.

2.1.1 Computation of voltage sags in meshed systems

The voltage can be computed by using U = I · Z. Ideally, the impedance of the short circuit fault is zero which results in zero voltage at the fault point. The voltage sag at a bus during a fault is dependent on the impedance between the fault and the bus, and the fault current. Figure 2.2 illustrates in a simplified way how the voltage sag varies in a 400 kV system.

Computation of voltage sags in a meshed system can be done by matrix calculation and applying Thevenin’s superposition theorem. According to Thevenin’s superposition theorem, the sum of the voltage at node n before the fault and the change in voltage and current during the fault gives the voltage sag at node n.

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V = IZ (2.1)

Figure 2.2: How voltage sag varies with impedance and type of generator

According to Thevenin’s superposition theorem, the voltage at node n, Vn, during the fault can be

written as the sum of the voltage before the fault, Vpre

n and the voltage change due to the fault,

∆Vn.

Vn= Vnpre+ ∆Vn (2.2)

If the fault occured at node f, then a fault current If exist. All other currents are zero since they

did not come from “outside the system”. The impedance that relates If and ∆Vn is Znf. Hence,

∆Vn= ZnfIf. If can be expressed in terms of V pre

f and Zff since ∆Vf= −V pre

f is true at the fault

point. The expression for If is shown in eq. (2.3).

If= −

V_fpre Zff

(2.3)

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Vn= Vnpre+ ZnfIf= Vnpre−

Zkf

Zff

V_fpre (2.4)

Usually, the pre-fault voltages, V_fpreand Vpre

n are equal to 1 p.u.. In conclusion, the voltage at bus

n during the fault only depends on Zffand Zkf.

2.2 Fault currents from synchronous generators

Traditionally, synchronous generators play a huge role of the fault response in the power system. During a low impedance fault, synchronous generators inject fault currents which are typically 3-6 p.u. (sometimes around 10 p.u.) [2]. The general transient response of the synchronous generator can be obtained by first studying the current in a RL circuit as shown in Figure 2.3.

Figure 2.3: RL circuit

Let α define the angle of the voltage wave at the instant of the fault. Then, the voltage source in Figure 2.3 has the voltage e described as,

e = Emsin(ωt + α) (2.5)

To model the fault event, the switch should be closed. By using KVL, following equation is obtained,

e = Ri + Ldi

dt (2.6)

Solving the differential equation for current i gives,

i = Ke−RLt+Em

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where, Z =pR2_{+ ω}2_L2 _(2.8) Φ = tan−1ωL R (2.9)

and K is obtained by fulfilling the criteria i(0+_{) = i(0}−_{). Hence,}

K = i(0−) −Em

Z sin(α − Φ) (2.10)

Eq. (2.7) shows that the short circuit current i can be divided into two components: a transient component and a steady-state component. For large values of t, e−RLt becomes small. Hence, i is characterized by the term sin(ωt + α − Φ) during steady-state.

2.2.1 Short circuit at the terminals of a synchronous generator

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Figure 2.4: Short circuit currents of a synchronous generator at its terminals during a continuing 3-phase fault starting at 3 s at 24 kV. The synchronous generator has rated power 384 MVA.

In many power system performance computations, it is preferable to neglect or separately treat the dc offset component. Presence of both components can make calculations and analysis more difficult [11]. Elimination of the DC offset component gives the waveform of the fundamental frequency component which is shown in Figure 2.5. The amplitude of the fundamental frequency component will not be constant due to changing rotor flux linkages. Instead, parameters of the synchronous generator vary between different periods. Commonly, the current can be divided into three periods: subtransient, transient and steady-state period [12]. A reactance is defined for each period to describe the current. Following reactances determine the current,

• subtransient reactance X_d00 - Determines current during the subtransient period

• transient reactance X_d0 - Determines current during the transient period

• synchronous reactance Xd- Determines current during the steady-state period

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Figure 2.5: Fundamental frequency component of armature current

For synchronous generators, the dq reference frame is commonly used. The transformation between the phasor reference frame and dq reference frame is shown in Appendix A. dq transformation allows simplified equations [13]. In dq-frame, the d-axis are aligned with the magnetic flux from rotor field excitation. The q-axis are aligned with the armature magnetic flux. X00

d, Xd0 and Xd denote the

d-axis synchronous reactance for each period [14].

During a short circuit fault at the terminals of a synchronous generator, the open circuit terminal voltage is E. The fault current from the synchronous generator is modeled differently between the subtransient, transient and steady-state period. Iq is small and negligible. The currents only depend

on the d-axis reactances.

I_d00= E X_d00 (2.11) I_d0 = E X0 d (2.12) Id= E Xd (2.13)

To obtain one expression of the fundamental frequency component current IAC, the envelope of the

waveform is defined. The envelope of IACis mathematically expressed with the sum of several terms.

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As seen in Figure 2.5, the subtransient component decays faster than the other components. The subtransient current envelope is expressed in eq. 2.14. Hence, the time constant T00

d is small, around 2-3 cycles [13]. ∆i00_d− i0 d= √ 2(I_d00− I0 d)e − t T 00 d (2.14)

The transient current envelope is expressed in eq. 2.15. During the transient period, the envelope decays slower than the subtransient period. This gives T_d0 > T_d00.

∆I0= i0_d− id= √ 2 (I_d0 − Id) e − t T 0 d (2.15)

The total ac component of the envelope iac-env is,

iac-env = √ 2 (Id+ ∆I0+ ∆I00) = √ 2 Id+ (Id0 − Id)e − t T 0 d + (I_d00− I_d0)e − t T 00 d (2.16)

From eq. 2.16, the fundamental frequency component current can be defined.

IAC≈ E 1 Xd + 1 X_d0 − 1 Xd e− t T 0 d + 1 X_d00 − 1 X_d0 e− t T 00 d (2.17)

Finally, the fault fault current injection from the synchronous generator is described as the sum of

IAC and IDC. The DC component current IDC is given by [13],

IDC= √ 2E cos α X00 d e−Tat _(2.18) Values of X_d00, X_d0, Xd, Td00, T 0

d and Ta are usually constant for a particular type of synchronous

machine. Therefore, these values can be found in tables [13]. T_d00 is always the smallest of all the time constants. T_d00 is typically 0.01 - 0.05 s. T_d0 is typically 0.4 - 3 s. Ta is typically 0.04 - 0.3 s.

[13], [15].

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2.3 Fault current injection from PEID

As opposed to the fault current injection from a synchronous generator, the fault current injection from a PEID is fully controlled. Examination of the fault current injection from the synchronous generator can give an understanding of how the fault current injection from the PEID should be controlled. Figure 2.6 shows the typical fault response of a synchronous generator during a low impedance fault divided into three distinct time intervals A, B and C. In Figure 2.6, the fault starts at the beginning of interval A. The fault is cleared at the end of interval B.

Figure 2.6: Three time periods of the typical response of a synchronous generator during a balanced fault. Figure from [5].

In Figure 2.6, period A lasts around 60 ms. During the initial period A, a fast fault current injection is required for the electrical protection system to be able to recognize, locate, and initiate fault clearance [16]. However, PEIDs cannot contribute to an instant fault response. The fault response is partly limited by the controller computation time of dq-components. According to Svenska Kraftnät’s experience, computations of dq-components takes around 20 ms in 50 Hz power systems. Time consuming processes of the PEID controller should be avoided. For example, the process of distinction between real and reactive fault current injection is unpractical [5].

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initial operating conditions, and voltage limits. Figure 2.7 shows the phase voltages and phase currents of a PEID during a 3-phase fault in a 400 kV power system. The plot was obtained from a project conducted by Svenska Kraftnät. Figure 2.7 shows a larger steady state current compared to the current during the 3-phase to ground fault. The fault current injection is limited by some of the factors mentioned earlier.

Figure 2.7: Phase voltages and phase currents of a PEID during a 3-phase-to-ground fault in a 400 kV power system. The fault lasts for 90 ms. The figure was obtained from Svenska Kraftnät

In Figure 2.6, period C shows the response of a synchronous generator after the fault has cleared. During this period, delivery of active power is important. This is connected to frequency deviations which are not discussed in this thesis. Mainly period A and B are of interest in this thesis.

2.3.1 Fault current injection during an unbalanced fault

During unbalanced faults, the converter should consider positive and negative sequence components. To avoid voltage support in the healthy phases, both positive and negative sequence fault currents should be injected [16]. According to Svenska Kraftnät’s experience, enabling capability of PEIDs to inject negative sequence current can be expensive. On the other hand, overvoltages in healthy phases can result in larger costs in the long run. It can therefore be worth to apply negative sequence current injection capability for PEIDs.

2.3.2 Conclusions regarding fault current injection from PEID

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PEIDs is also limited by other factors. Examining the fault current injection from the synchronous generator can give an understanding of how the fault current injection from the PEID should be controlled. With detailed requirements on fast response and voltage support, and appropriate control settings, it is possible to achieve the desired effects of each interval A and B. Chapter 4 describes some controller settings to achieve fast current injection during period A. Chapter 4 also describes how suitable control settings can improve voltage support during interval B. The impact on the voltage support from PEIDs in a grid with a large share of PEIDs is shown with simulations presented in chapter 6.

2.4 Network requirements on fault current injection

Since PEIDs’ performance are fully dependent on its controllers, suitable requirements in grid codes concerning fault current injection are necessary. Synchronous generators on the other hand, will inherently inject a fault current. Therefore, highly detailed requirements in grid codes concerning its fault current injection are not required. The EU Commission supports European TSOs to es-tablish Grid Code requirements on fault current injection in the Commission regulations RfG [3] and requirements for grid connection of HVDC and DC-connected power park modules [4]. Article 20.2b in RfG [3], requirements for type B power park modules, states that “the relevant system

operator in coordination with the relevant TSO shall have the right to specify that a power park mod-ule should be capable of providing fast fault current at the connection point in case of symmetrical (3-phase) faults...”. Article 20.2c in RfG has a similar statement but concerns asymmetrical faults.

The Commission regulations provide harmonized rules for grid connections to ensure common under-standing in the interconnected transmission system. The regulations allow ranges of parameters to be determined based on national choices. This allows requirements that reflect national differences [3].

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Fault ride through capability

Fault ride through (FRT) capability requirement is not directly connected to the characteristics of the fault current injection. However, FRT implies that a device should have the capability to remain connected to the grid during temporarily low voltages at the connection point. The FRT capability is specified with a voltage-time curve. The curve shows when the PEID is allowed to disconnect [16]. Being above the curve implies that the PEID is required to stay connected to the grid. The voltage-time curve is related to the fault clearing time of the protection system and the voltage recovery of the power system after fault clearing. Since different protection schemes are adopted in different countries, the FRT voltage-time curve varies between countries [17].

Active or reactive current

The TSO together with the relevant system operator has the possibility to determine priority between active or reactive fault current injection. During a fault, the magnitude of the fault current injection from a converter is partly limited by the converter rating. Therefore, it is important to specify whether active or reactive current is prioritized [18]. Not all TSOs in Europe have requirement on priority of active or reactive fault current injection. Between the TSOs with requirement on priority of active/reactive current, reactive current prioritization is more common [16]. In [16], only 1 of the 7 investigated European countries required priority of active current during a fault. Reactive fault current injection provides better voltage support. However, when determining the priority, factors such as system inertia, frequency sensitivity and whether the network is weak or strong play a role [18][16].

In addition, some national grid codes include requirements on the injection of additional reactive current during large voltage deviations. The required additional reactive current is usually defined as proportional to voltage deviation from the nominal system voltage. Therefore the additional reactive current can be described with the proportional “K-factor”. According to [16], the K-factor is described as shown in eq. (4.12). Usually, K is around 3 [16]. There seems to be a lack of clear guidelines for determining the optimal K-factor [19]. It should also be mentioned that not all national grid codes in Europe include requirements on the magnitude of the additional reactive current.

Step response requirements

Rise time and settling time need to be specified since the fault response of PEID is fully controlled. The rise time is the time required until the step response has reached a certain percentage of the desired value [5]. For example, the Finnish TSO, Finngrid , requires that “fault current’s injection

mode shall rise to the target value within 30–50 ms” with a tolerance +20% - -10% [20]. Hence, the

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voltage support should last for 20 - 30 ms after the voltage is within the dead band [21]. The dead band defines at which voltage deviation the PEID should inject a fast fault current. It is typically around 10 % of the nominal voltage. It is also possible to determine which voltage deviation the fault current’s injection mode should be disabled when returning to the nominal voltage again. [16]

The settling time is the time required until the step response has entered the desired tolerance for the last time [5]. Usually, the settling time is 60 ms [16] with a tolerance of around 10 %. For example, in [20] it is stated that the fault current’s injection mode should settle to the desired tolerance level within 60 - 80 ms.

Requirements in case of an unbalanced fault

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Chapter 3

Short circuit fault related effects

with increasing share of PEIDs in

the power system

This chapter describes the effects of increasing share of PEIDs in the power system. The effects are related to short circuit faults which exist for short time intervals. Other effects including decreased inertia, frequency stability issues, less damping and effects on small signal stability are therefore not included.

3.1 Power system protection

Existing protection schemes are developed for grids dominated by synchronous generators. With an increasing share of PEIDs in the grid, the traditional protection system may neither be able to operate selectively nor with safety. A well functioning protection scheme is important to ensure the safety of personnel, avoid prolonged outages, provide a good level of reliability for customers [24] and ensure system stability. The fault current injection in interval A as shown in Figure 2.6 is especially important for the protection system to be able to recognize, locate, and initiate fault clearance [16].

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sub-stantial difference between the steady-state and fault current. However, having a PEID-dominated power system results in a small difference between the steady-state and fault current. Particularly overcurrent protection and some differential protection are affected by lower fault currents. In con-sequence, using these protection schemes in a PEID-dominated grid can lead to undetected faults causing damage to equipment and compromised safety. Also, not considering the short circuit cur-rents from PEIDs (only considering the short circuit curcur-rents from other generators) when choosing the settings for the protection can cause unselective tripping. Today, Svenska Kraftnät excludes fault current injections from PEIDs in the models used for protection setting calculations. This simplification is reasonable with the existing levels of PEIDs, but complications can arise in when increasing the share of PEIDs in the grid.

Distance protection are not significantly affected by a higher share of PEIDs in the grid. Distance protection does not solely depend on the magnitude of the fault current. Instead, the distance protection depends on the the ratio between the voltage and the current, i.e. the impedance [24]. Therefore, distance protection can be suitable in a PEID-dominated grid. This is concluded both at Svenska Kraftnät and in [2]. Maloperation of distance protection relays in a PEID-dominated grid can still occur under some circumstances. This is discussed more in [25] and [26]. Besides distance protection relays, voltage measuring relays can be relevant in a PEID-dominated grid. A voltage sag is a good fault indicator. However, as opposed to using a combination of voltage and current, the direction cannot be determined with a protection method based on voltage only. Hence selectivity cannot be obtained in a meshed grid with voltage measurement based protections. In addition, more conventional protection principles, such as impedance measurement, transient based principles e.g. travelling wave could be considered. All do not depend on the steady-state fundamental fault quantities. Therefore, the principles are expected to function accurately in a PEID-dominated grid. Further investigation in protection challenges and solutions are out of the scope of this thesis. But, it is evident that an increasing share of PEIDs in the grid results in new challenges for the protection system.

To sum up, an increasing share of PEIDs in the grid leads to a changed system behavior during a fault. Not considering the changed level of short circuit power in the system can cause maloperation of protection devices. New protection scheme solutions are required to ensure a selective, reliable and safe protection system.

3.2 Power Quality issues for customers

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Current Variation” and “Events”. “Voltage and Current Variation” concerns small deviations from the desired value. This includes frequency variations, magnitude variations and harmonic voltage distortion. “Events” concern a significant deviation of the voltage or current from its ideal wave shape, e.g. when the voltage drops to zero [10].

For some industrial costumers, voltage sags are the most important power quality issue [6]. Today, modern equipment have become more sensitive to voltage sags. For example, equipments used in the semiconductor industry, paper industry and steel industry are especially sensitive to voltage sags. Voltage sags can lead to malfunction of equipment and subsequently lead to sustained interruptions [7]. An employee at Svenska Kraftnät has confirmed that some factories will experience a stoppage due to a > 65 ms, 15-20 % voltage sag. The production stoppage varies considerably within a factory and between different factories. In [7], it is mentioned that disruption can cause a 24-hour production stoppage in paper and pulp factory. Data from Svenska Kraftnät show that the stoppage time mostly varies between a few minutes to 12 hours. Production stoppage leads to huge costs including costs of damaged equipment and processes, faulty products, delayed deliveries and less satisfied customers [7].

Many industries do not face any problems. Also, the sensitive industries may not always be affected by a voltage dip. Large voltage deviations lasting for a longer time gives a higher chance that the industry is affected. One project [27], analyzing disruptions of forest, pulp and paper industry, concluded that earth faults gives the least disruptions. It is also evident that deeper voltage sags lasting for a longer time caused more sustained interruptions.

Replacing more synchronous generators with PEIDs results in lower fault current If. As a

conse-quence, deeper voltage sags are observed during a low impedance fault. As mentioned earlier, deeper voltage sags leads to a higher probability of sustained interruptions of sensitive equipment. Efficient voltage support from PEIDs is necessary to avoid large costs related to stoppage of equipment. How to achieve efficient voltage support in a PEID dominated grid is discussed in Chapter 7.

3.3 Overvoltages during unbalanced faults

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overvoltages should be minimized.

Synchronous generators will naturally inject positive and negative sequence currents during unbal-anced faults. The voltage unbalance is therefore naturally diminished [18]. Fault current injection in negative sequence from PEIDs requires more advanced control strategies. Control strategies that also track and control the negative sequence currents are necessary for the PEID to inject a negative sequence current during unbalanced faults. Control strategies for negative sequence current injection is presented in section 4.7.

3.4 Cascade effects regarding disconnection of generators

Requirements on FRT capability implies that generators should remain connected to the grid during a voltage sag as a function of time. In section 2.4.1, requirement on FRT capability is discussed in detail. Today, with more PEIDs connected to the power system, FRT capability is important to avoid large loss of generation after a fault. Loss of generation due to a fault affects frequency and voltage stability [?] and can cause cascade effects [28].

The cascade effect occurs when disconnection of one generator leads to a chain reaction where more generators starts to disconnect [29]. When several PEIDs disconnects from the power system during a short circuit fault, the voltages in the system drops further [30]. When the remaining synchronous generators and PEIDs has reached its limits, it is not possible to support the voltage further which causes the voltages to continue to drop. In worst case, undervoltage and underfrequency protection can cause the remaining generators to disconnect. The cascade effect eventually leads to a blackout [31] or abnormally low voltages in the power system, in other words, a voltage collapse occurs [?]. Without requirements on FRT capability, PEIDs are allowed to disconnect from the power system due to a temporarily low voltage caused by a short circuit fault. This can lead to other devices including transmission lines tripping off due to overload caused by unexpected power flows [32].

When more PEIDs replace synchronous generators, the short circuit power decreases. Consequently, deeper voltage sags can be expected during a fault which exposes more PEIDs to disconnect during low voltages [?]. FRT capability are necessary for PEIDs to “ride-through" voltage sags during faults in the power system [29]. In effect, cascade effects are avoided.

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angle δ [33]. The transient stability is determined by the power system’s ability of decelerating the rotor angle [34] and the synchronous generator’s ability to stay synchronized.

Increasing share of PEIDs leading to replacement of more synchronous generators affects the tran-sient stability negatively. Understanding the effect on trantran-sient stability due to more PEIDs in the grid requires a theoretical background about transient stability. Firstly, the relationship between the rotor angle and transmitted power to the power system is established in a simple system. Sec-ondly, an approach for validating the stability is presented. The simple system as shown in Figure 3.1 consists of a synchronous generator feeding a larger power system through a line. The line has reactance Xs. The electrical power transmitted between the synchronous generator and grid is [34],

Pe=

EU Xs

sin δ = Pmaxsin δ (3.1)

Figure 3.1: A simple system consiting of a synchronous generator and an infinite bus

In steady-state, the electrical power Pe is equal to the mechanical power from the synchronous

generator Pm. However, a disturbance in the grid affects Pe which causes the rotor to accelerate

with power Pa[34]. The relation between Pe, Pm and Pa is shown in eq. (3.2).

Pe= Pm− Pa (3.2)

The relation between power and rotor angle is obtained by first realizing that the accelerating torque

Ta is the product of the total moment of the inertia J and the angular acceleration as shown in eq.

(3.3). As with eq. (3.2), the accelerating torque can be described with the mechanical torque Tm

and electrical torque Te [35].

Jd

2_θ m

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Power is given by the product of torque and angular velocity. Therefore, eq. (3.3) can be expressed with power as shown in eq. (3.4).

J ωm

d2_θ m

dt2 = Pa= Pm− Pe (3.4)

ωm is the angular velocity of the rotor. J ωm gives the inertia constant M. By using M, eq. (3.4)

and (3.1), the swing equation for transient stability is obtained,

Md

2_θ m

dt2 = Pm− Pmaxsin δ (3.5)

To evaluate the transient stability, the time dependent rotor angle δ is considered. A formal solution of eq. (3.5) cannot be found since eq. (3.5) is non-linear. However, it is known that if δ passes through a maximum, the system is considered as stable. If δ increases with time, the system is considered as unstable. By using the criterion dδ_dt = 0, it can be derived that the stability can be evaluated by using the equal-area criterion [35].

3.5.1 Equal-area criterion of stability

When a nearby 3-phase fault occurs at time t0, Pe drops to 0. Pe moves from a to b as shown in

Figure 3.2. The acceleration area A1 increases until the fault has cleared at time tc. At time tc

the rotor angle is δc. When the fault has cleared, Pe increases to d. According to the equal-area

criterion, the rotor slows down and the decelerating area A2 begins to increase until areas A1= A2.

As seen in Figure 3.2, this occurs when Pe has moved to e. Derivation of equal-area criterion is

shown in [36].

By observing Figure 3.2, it is evident that the transient stability is determined by a maximum clearing time and clearing angle that ensures that it is possible to satisfy A1 = A2. Hence, the

maximum clearing time and clearing angle is given by the critical clearing time tcr and critical

clearing angle δcr[35]. If the clearing time is too long, it will not be possible to achieve a sufficiently

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Figure 3.2: Equal area criterion

3.5.2 Effect on transient stability due to increased share of PEIDs

Although the equal-area criterion is only applicable for a simple system as shown in Figure 3.1, general conclusions about the transient stability concerning synchronous generators can still be drawn. From Figure 3.2, it can be understood that tcr is dependent on Pmax. Having a low Pmax

results in a lower tcr. Hence, less A2, decelerating energy [36], is available to ensure that δ reaches

a maximum. When more synchronous generators are replaced by PEIDs it can be interpreted as increased impedance between the synchronous generator and grid. In consequence, Pmaxdecreases.

When a fault occurs in a system with large share of PEIDs, there will be less energy to decelerate

δ. Hence, a faster fault clearing time is necessary. In other words, the time interval B of the current

injection as shown in Figure 2.6 should be minimized.

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Chapter 4

Control of Power Electronics

Converters

This chapter describes the basic functions of the PEID control system, especially the control system of a VSC-HVDC. Parts of the control system which mainly affect the fault current injection are described more thoroughly. The chapter mainly focuses on faults during balanced conditions. Only section 4.7 describes the control system during unbalanced conditions.

4.1 Introduction

Advancements in power electronics converters are one of the main factors of enabling integration of RES into the power system. The introduction of controllable power semiconductor switches, such as the insulated gate bipolar transistor (IGBT) led to development of voltage source converters for HVDC, VSC-HVDC [37]. Different converter configurations are used for VSC-HVDC, both two and three level converters as well as multilevel converters. An example of a multilevel converter is the modular multilevel converter (MMC) used in full converter based wind turbine generators.

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describe how the control system of the PEID support the fault current injection.

4.2 Vector current control during balanced conditions

Common control methods for grid-connected VSCs are vector current control and power-angle con-trol. Power-angle control aims to control the active power by varying the phase-angle shift between the AC network and the VSC system. Further description about the power-angle control is presented in [40]. Today, vector current control is commonly used in many applications such as VSC-HVDC and doubly-fed induction generator (DFIG) wind turbines. Because of the successful and popular implementation of vector current control, it is investigated further in this thesis.

Vector current control consists of a fast inner current control loop and outer control loops. The inner current control loop regulates the current to control the instantaneous active and reactive power respectively. The vector current control processes vectors rather than per-phase components. The controller is performed in a αβ-frame or a dq-frame. This implies that two signals paths are treated rather than three signal paths [37]. A typical control loop using vector current control is shown in Figure 4.1. As seen in Figure 4.1, three-phase voltages and three-phase currents are measured at point of common coupling (PCC) and subsequently transformed into a dq system. By regulating the current magnitudes id and iq, it is possible to control the voltage output from the

controller, Vc.

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4.3 Inner control loop

Figure 4.2: Model of a VSC component connected to an equivalent ac system

Figure 4.2 shows a simplified model of a VSC component connected to an equivalent AC system. Inductance L and resistance R models the total inductance and resistance from the transformer and phase reactor. The injected line-to-neutral voltages from the VSC are included in vector Vc. The

AC system line-to-neutral voltages are included in vector Vabc. The three-phase currents in vector

Iabc are flowing from the AC system to the VSC. From the figure, the relationship between the

voltage from converter to the AC-grid is obvious. With dq components, this gives,

" vd vq # = Ld dt " id iq # + " vc,d vc,q # + R " id iq # + ωL " 0 1 −1 0 # " id iq # (4.1)

As shown in eq. (A.5) in Appendix A, differentiation in the dq-frame leads to an additional term jω. The inner current controller regulates the magnitude of the currents idand iq with a PI regulator.

By examining eq. (4.1), it is evident that the currents idand iq are coupled. It is desired to control

the components independently. Therefore, the controller must be able to decouple the components. The cross coupling is cancelled by adding the gain ωL in an inner positive feedback loop.

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Vldq= RIdq+ jωLIdq+ Vdq (4.2)

Since the AC voltage is aligned with the d-axis, the q part of the ac voltage is zero. This facilitates computations. Hence,

Vdq= Vd+ j · Vq= Vd+ j · 0 (4.3)

The current is assumed to flow from the AC grid to the VSC. The exchanged active and reactive power between the grid and the converter is denoted Pac and Qac. When computing Pacand Qac, it

should be noted that K = 1, which implies that the amplitudes of phase voltages and phase currents will be the same in three-phase and dq-frame. However, computing power gives K = 3/2. This is proven in [37]. From eq. (4.3) it is possible to obtain Pac and Qac. Pac and Qac are obtained in eq.

(4.4) Sac= Pac+ jQac= 3 2VdqI*dq= 3 2 Vd(id− jiq) = 3 2(Vdid− jVdiq) (4.4)

The inner current control loop regulates idand iq with PI controllers. From eq. (4.4) it is evident

that id and iq can control Pac and Qac. Also, since the active power Pac is only dependent on id

and the reactive power Qac is only dependent on iq, it can be concluded that idcontrols the active

power and iq controls the reactive power.

4.4 Phase-Locked Loop

Traditionally, synchronous generators are responsible for an acceptable voltage and frequency level by controlling its rotational speed and excitation current. Converters adjust to these quantities through a Phase-Locked Loop (PLL) in order to remain synchronized to the grid. In other words, converters has a grid-following behaviour [41]. The output of the PLL is the angle θ, which is used when transforming between the 3-phase-frame and the rotating dq-frame.

The block diagram of a PLL can vary. Synchronous reference frame PLL (SRF-PLL) is commonly used in three-phase systems [42]. A block diagram of a typical SRF-PLL is shown in Figure 4.3. The measured voltage in the dq-frame Vdq is used to obtain the phase tracking error ∆ϕ. This is

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Figure 4.3: Block diagram of PLL

∆ϕ is fed to the PI controller in order to obtain the angular frequency deviation ∆ω. Integrating the sum of ∆ω and the nominal ωl gives the angle θ. It is shown in eq. (A.3), that the angle θ is

necessary when transforming to the dq-frame.

4.5 Outer controller

The outer control loops computes the reference values i∗_d and i∗_q. i∗_d and i∗_q are fed to the inner control loops. i∗_d is obtained from either active power controller (APC) or DC voltage controller (DCC). i∗q is obtained from either reactive power controller (RPC) or AC voltage controller (ACC).

4.5.1 APC and RPC

By rewriting eq. 4.4, the relationship between id, iq, reactive power and active power is evident. eq.

4.6 shows that the active power exchanged between the grid and the converter is dependent on id.

eq. 4.7 shows that the reactive power exchanged between the grid and the converter is dependent on iq [38]. In other words, P and Q can be controlled by regulating idand iq respectively.

P = 3

2Vd· id (4.6)

Q = −3

2Vd· iq (4.7)

The outputs of the APC and RPC are the reference values i∗_d and i∗q respectively. The constant

active and reactive power controllers are shown in figures 4.4 and 4.5. A closed loop controller is adopted in order to satisfy that the measured P and Q is equal to the reference values P∗ and Q∗ [43]. This means for example, if P∗> P , then idshould be increased. id is adjusted until P = P∗

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Figure 4.4: Block diagram of an APC

Figure 4.5: Block diagram of a RPC

The block diagram of the APC and RPC also includes a saturation block. The saturation block intends to limit the current. Section 4.5.3 describes the current limiter further.

4.5.2 DCC and ACC

The DC voltage controller aims to keep the DC voltage constant by regulating the current id. In the

VSC-HVDC, at least one VSC needs a DCC. The DCC will act as a “slack”, meaning that it will absorb any power in order to keep the DC voltage constant [43]. The other end will usually adopt the APC which follows an active power reference. In order to achieve a power balance, the converter in DCC will import (or export) as much power that came from the other end. A block diagram of the constant DCC is shown in Figure 4.6. It looks similar to the block diagram of the APC and the RPC. However, the DC voltage is used as reference instead of power. The DCC controls the DC voltage measured on the HVDC line.

The AC voltage controller (ACC) aims to keep the AC voltage constant by regulating the current

iq. The ACC is more common than RPC. A block diagram of the constant ACC is shown in Figure

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Figure 4.6: Block diagram of a DCC

Figure 4.7: Block diagram of an ACC

4.5.3 Current limitation

The current limiting function was introduced in the block diagram of APC, RPC, DCC and ACC. The current limiters are essential during disturbed conditions, eg. in order to avoid unnecessary trips. Since overheating can cause damage to the converter, the current is limited to a maximum allowable magnitude with a saturation block. Allowing a higher maximum current would require larger semiconductors including larger costs. Current limitations are also applied due to other criterion for example, manufacturer’s design principle. In addition, limitations downstream in the inner controls, e.g. internal voltage references, are normally applied by the control to ensure that valve voltage stays within the limits at all times, and to ensure stability margins of the converters.

Besides the principle of the saturation block, adding a virtual impedance is another well known method of limiting the current. The virtual impedance is added such that the input reference values of the outer controller are decreased during a fault. A high measured current will trigger the virtual impedance. As a consequence, the output currents i∗_dand i∗_q of the outer controller become limited. The principle of virtual impedance is described more thoroughly in [45].

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this thesis. The idea of the saturation scheme is by simply adding upper and lower limits of the d-axis and q-axis current. The upper and lower limits depends on the d/q prioritization.

d/q prioritization

The upper and lower current limit applied to the saturation block is determined based on the priority between the d-axis and q-axis current. As mentioned in section 2.4, some TSOs require active current prioritization during a fault while other TSOs require reactive current prioritization. However, some studies, [46] and [47], argue that prioritizing reactive current during a fault give similar voltage drops compared to the case when reactive current is not prioritized. [46] also claims that a purely reactive current injection gives better results with respect to the voltage drop. But, still not marginally better. Additionally, i∗_dand i∗_qmay be limited by other functions before applying d/q prioritization. These limitations can be based on other criteria besides current capability limitations. For example, the supplier’s design principle. How these limitations are implemented have an important impact on the dynamics on voltage support during the fault.

Figure 4.8 illustrates prioritization of reactive and active current. The circle in the figure defines values of the maximum current capacity imax

dq . During a fault, the measured current transformed

into the dq-frame imeas_dq can lie outside the circle. It is then necessary to decide the magnitude of the limits for each current component. Figure 4.8 can be translated into formulas in order to obtain the upper and lower limits of the d-axis and q-axis current. In case of q-axis current prioritization when imax_dq lies outside the circle, the q-axis current is limited as follows [48],

i*max_q = ( |imeas q |, if |imeasq | < imaxdq imax dq , otherwise (4.8)

Where |imeasq | is the q-component of the measured current imeasdq . Note that i *max

q is the upper limit

and −i*max

q is the lower limit of the q-axis current. The limit of the d-axis current is then defined

as,

i*max_d = q

(imax

dq )2− (i*maxq )2 (4.9)

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i*max

d is the upper limit and −i*maxd is the lower limit of the d-axis current. Subsequently, the limit

of the q-axis current can be defined,

i*max_q = q (imax dq )2− (i *max d )2 (4.11)

(a) d-axis current prioritization (b) q-axis current prioritization

Figure 4.8: d/q prioritization. When the d-axis current is prioritised, the d-component of the current becomes larger. The maximum value of the total current Idq is given by the circle. Observe that

the measured current imeas

dq is equal in the both cases (a) and (b).

Equations (4.8)-(4.11) are only two strategies of current limitation. Other methods exist. As men-tioned earlier, it is possible to only inject a reactive current. Then the active current component is blocked [46]. In some cases, particularly for VSC-HVDC, one approach assumes that the VSC can withstand currents which are above imax

dq for a limited time. Then, the limits can be set to

i*max dq = i

*max

q = i*maxd which implies that the total current I *max

dq lies outside the circle [48]. This

approach implies that the converter contributes to a larger fault current injection compared to the strategy presented in eq. (4.8)-(4.11).

4.5.4 K-factor

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current is based on the K-factor. As shown in eq. (4.12), the additional reactive short circuit current ∆Iq is proportional to the K-factor and the voltage during and before the fault. According to [16]

the K-factor can be described as,

∆Iq In = KU f ault_{− U}pre Un (4.12)

Unis the nominal voltage and Inis the nominal current at the generating facility. Upreis the voltage

before the fault and Uf ault_{is the voltage during the fault. I}

qis the injected reactive current. Hence,

Iq= ∆Iq+ Iqpre (4.13)

The K-factor depends on the gain of the PEID controller. The gain of the PI-controller in the ACC and RPC is equal to the K-factor. Tuning of the K-factor can lead to better voltage support during a fault. The K-factor ranges between 0 - 10 [19]. As presented in section 2.4, requirements on the value of K differ between TSOs in Europe. Studies have shown that a high K-factor leads to a lower voltage drop during a fault [46], [19]. However, a too high K-factor will sometimes not result in a better voltage support than a lower K-factor because of the current limiter of the converter. For example, having K=6 and a voltage change of ∆U = −0.30 p.u. during a fault, gives K · ∆U = 1.8 p.u. which seems a bit too high for some converters. Since d/q prioritization also affects the limit of ∆Iq, it is necessary that TSOs specify whether active och reactive current should be prioritised

during faults.

Deadband

The dead-band defines an interval where additional reactive current injection is not required. In most cases, the dead-band is 10 % of the nominal voltage. Figure 4.8 illustrates a curve of additional reactive current for voltage support including and excluding the dead-band respectively. The figure shows a grey area, the dead-band. When the voltage at PCC, UPCC is 0.90Un < UPCC < 1.1Un,

then additional reactive current is zero. If no dead-band is included, the curve would also consists of the dashed line.

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Figure 4.9: Relation between ∆Iq and voltage drop with and without dead-band

4.6 Step response requirements

As mentioned in section 2.4, some European TSOs require a certain rise time and settling time of the current injection from PEIDs. The converter plays a crucial role of the fault response where the fault response is defined by rise time, settling time and overshoot. Rise time is the time taken for the output signal to reach a certain percentage of the desired value. Settling time is the time taken for the output signal to enter the desired tolerance band for the last time [5].

Controller gains affect the fault response. For HVDC converters and full converter wind turbines, PI controllers are usually adopted. Therefore, the proportional gain Kc and integral time constant

τI of the PI controller are of interest when a certain fault response is desired. The PI controller

output u(t) is usually described as,

u(t) = Kc+

Kc

τI

Z

e(t)du (4.14)

Tuning of Kc and τI results in different fault responses. For example, increasing Kc gives a faster

response, in other words, a reduced rise time [49]. To eliminate the steady-state error, integral control is introduced. Increasing the integral time constant τI gives a slower response, an increased

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Table 4.1: Effect on rise time and settling time when increasing Kc and τI

Control tuning Rise time Settling time Increasing Kc Reduces Small change

Increasing τI Increases Reduces

4.7 Controls during unbalanced faults

During balanced situations in the power system, only positive-sequence components are of interest. The currents and voltages are equal in all phases. This means that the magnitude of the fault current injection is equal in all phases during a balanced fault. In contrast, when a converter injects a positive-sequence fault current during an unbalanced fault, also healthy phases are affected. This leads to increased unbalance and overvoltages in healthy phases [16]. By controlling negative-sequence fault current injection, overvoltages in healthy phases can be avoided. Therefore, it is desired to control the positive and negative sequence current injection independently [37].

As mentioned in section 2.4, most TSOs have not specified requirements on negative sequence fault current injection. Not until recently, some European TSOs have stated requirements of negative sequence K factor. The K− factor is determined by the magnitude of the negative sequence reactive

fault current contribution in relation to the negative sequence voltage deviation. This is shown in eq. (4.15) which should be compared to eq. (4.12).

∆Iq− In = K− ∆U− Un (4.15)

It is assumed that all transformers between the grid and the generator terminals has a delta-star connection. Therefore, the zero sequence components can be disregarded.

4.7.1 Positive/Negative sequence tracking

It is important to track the positive and negative sequence currents and voltages at the PCC during unbalanced faults in order to achieve effective control [37]. Two established methods to track the positive and negative sequence components are 1. Decoupled double synchronous reference frame (DDSRF) and 2. Double second-order generalized integrator (DSOGI). DSOGI is usually performed in the αβ-frame. In consequence, no decoupling network is required as in the case of DDSRF. DSOGI is out of the scope in this thesis, but is discussed in [37].

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positive rotating direction reference axes, dq+1 _{and the negative rotating direction reference axes,}

dq−1_{. The dq}+1 _{axes have the angular position θ with regard to the αβ-frame. The dq}−1 _{axes have}

the angular position −θ. The reference axes are shown in fig. 4.10. dq+n, denotes that it is rotating with nω frequencies.

Figure 4.10: Axes of DDSRF

The three-phase measurements at PCC have to be transformed into the dq-frame. As shown in Appendix A, the dq-frame is based on transformation from the αβ-frame. The measured voltages in the αβ-frame with respect to the positive and negative sequence components are shown in eq. (4.17). V+ _{and V}− _{denote the magnitude of the positive and negative voltage. For example, the}

phase voltage in phase a, va, can be expressed as,

va= V+cos (ωt) + V−cos (−ωt) (4.16) Then, " vα vβ # = v+_αβ+ v−_αβ= V+ " cos (ωlt + ϕ+1) sin (ωlt + ϕ+1) # + V− " cos (−ωlt + ϕ−1) sin (−ωlt + ϕ−1) # (4.17)

As mentioned in section 4.4 Phase-Locked Loop, the constant phase angle ϕ+1 is obtained from the

PLL. However, in order to support negative sequence current injection, the PLL should be able to obtain ϕ−1. ϕ−1is computed from the negative sequence space vectors [51], in a similar way as ϕ+1

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Finally, transforming eq. (4.17) to dq−1- and dq+1_{-frame using the transformation matrix}_T dq+1 gives, " v_d+1 vq+1 # = vdq+1=T_dq+1v_αβ= V+ " 1 0 # + V− " cos (−2ωlt) sin (−2ωlt) # (4.18) " v_d−1 vq−1 # = vdq−1 =T_dq−1vαβ= V+ " cos (2ωlt) sin (2ωlt) # + V− " cos (ϕ−1) sin (ϕ−1) # (4.19)

As shown in eq. (4.18), the negative sequence term is an oscillating ac component with frequency -2ωl in the dq+1-frame. As shown in eq. (4.20), the positive sequence term is an oscillating ac

component with frequency 2ωl in the dq−1-frame. In other words, there is a coupling between the

positive and negative sequences. In order to achieve better control, it is desired to decouple the positive and negative sequence components. The decoupling network of the DDSRF is shown in fig. 4.11.

Figure 4.11: Block diagram of DDSRF

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reference currents, i∗_d+1, i∗_q+1, i∗_d−1 and i∗_q−1. Computation of the reference currents are explained in the subsequent section.

Figure 4.12: Control system with decoupled positive and negative sequence components

4.7.2 Control strategies

Injecting unbalanced currents are desired during unbalanced faults. As mentioned earlier, injecting a symmetric current during an unbalanced fault can lead to overvoltages. Therefore, the control system should inject negative sequence currents during unbalanced faults. In order to regulate the current, the controller must be able to define the current references. In this case, four current references must be defined, i∗_d+1, i∗_q+1, i∗_d−1 and i∗_q−1. The current references can be achieved from various control strategies which affect the voltage support in different ways.

This thesis is limited to only give an overview of some common control strategies. In short, control strategies can be divided into two categories, 1. Power characteristic oriented control strategies and 2. Voltage-support-oriented control strategies. Both types will be approached.

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and q can be written as,

p = P + P1cos(2ωlt) + P2sin(2ωt) (4.20)

q = Q + Q1cos(2ωlt) + Q2sin(2ωt) (4.21)

In eq. (4.20), P is the average instantaneous active power. P1 and P2 are the magnitudes of

the oscillating terms which are oscillating at double frequency. In eq. (4.21), Q is the average instantaneous reactive power. Q1and Q2are the magnitudes of the oscillating terms. The oscillating

terms are a result of interaction between different sequences. This is shown in eq. (4.22) - (4.27)

P = 3 2(id+1vd+1+ iq+1vq+1+ id−1vd−1+ iq−1vq−1) (4.22) Q = 3 2(id+1vq+1− iq+1vd+1+ id−1vq−1− iq−1vd−1) (4.23) P1= 3 2(id+1vd−1+ iq+1vq−1+ id−1vd+1+ iq−1vq+1) (4.24) P2= 3 2(id+1vq−1− iq+1vd−1− id−1vq+1+ iq−1vd+1) (4.25) Q1= 3 2(id+1vq−1− iq+1vd−1+ id−1vq+1− iq−1vd+1) (4.26) Q2= 3 2(−id+1vd−1− iq+1vd−1+ id−1vd+1+ iq−1vq+1) (4.27)

Fault current injection from power electronic interfaced devices

IN

DEGREE PROJECT

ELECTRICAL ENGINEERING,

SECOND CYCLE, 30 CREDITS

,

STOCKHOLM SWEDEN 2020

Fault current injection from power

electronic interfaced devices

SANDRA THENGIUS

Fault current injection from power

electronic interfaced devices

Sandra Thengius

Master’s thesis in electrical power engineering

Date: September 20th, 2020

Svenska Kraftnät supervisors: Robert Rogersten & Viktor Weidenmo

KTH supervisor: Robert Eriksson

Examiner: Nathaniel Taylor

Abstract

Sammanfattning

Acknowledgements

Abbreviations

Contents

Chapter 1

Introduction

1.1

Background

1.2

Objectives

1.3

Motivation and problem description

1.4

Scope and Limitations

1.5

Outline

Chapter 2

Fault currents in a power system

2.1

Voltage sags caused by short circuit faults

2.1.1

Computation of voltage sags in meshed systems

2.2

Fault currents from synchronous generators

2.2.1

Short circuit at the terminals of a synchronous generator

2.3

Fault current injection from PEID

2.3.1

Fault current injection during an unbalanced fault

2.3.2

Conclusions regarding fault current injection from PEID

2.4

Network requirements on fault current injection

Chapter 3

Short circuit fault related effects

with increasing share of PEIDs in

the power system

3.1

Power system protection

3.2

Power Quality issues for customers

3.3

Overvoltages during unbalanced faults

3.4

Cascade effects regarding disconnection of generators

3.5.1

Equal-area criterion of stability

3.5.2

Effect on transient stability due to increased share of PEIDs

Chapter 4

Control of Power Electronics

Converters

4.1

Introduction

4.2

Vector current control during balanced conditions

4.3

Inner control loop

4.4

Phase-Locked Loop