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Page 1 of 6

ESKI - MODULE DOCUMENTATION EQ

CLK

Ki_1<7:0>

PIXO<7:0>

EQ

PIXI Ki<7:0>

RESET DVI

DVO

Module responsible _______________________

Specification responsible Bengt Oelmann/Mattias O’Nils

Designers ____________________________________________

General description: This module equalizes the image based on histogram information.

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CONTENTS

Page

1. SPECIFICATION...3

1.1 INTERFACEDESCRIPTIONDIGITALSIGNALS...3

1.2 HIERARCHY...4

1.3 FUNCTIONALITY...4

1.4 DESIGNGOALS...4

DESCRIPTION OF IMPLEMENTATION...5

2. VERIFICATION...5

3. DELIVERABLES...6

3.1 DIGITALMODULES...6

Rev Date Description of modification Sign

0 Initial issue

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1. Specification

1.1 Interface description digital signals Inputs and outputs in alphabetic order.

Input signals

Signal name From Input delay Description

CLK External - Clock

Ki<7:0> Internal 20 ns Histogram data Ki_1<7:0> Internal 20 ns Histogram data

PIXI CamIF 20 ns Image data

RESET External 20 ns System reset

DVI CamIF 20 ns Input data valid

Output signals

Signal name To Output delay Description

PIXO<7:0> CamIF 20 ns Image data output

DVO CamIF 20 ns Image data output valid

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1.2 Hierarchy Hierarchy of module -

1.3 Functionality

The module computes new pixel values for adjusting the contrast in the image. We propose following function:

1 256i

i

PIXI K K

PIXO  

1.4 Design goals Frequency: 15 MHz

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Description of implementation

The implementation strategy should be described here. If special techniques have been used to fulfill the Design goal demands, this should be pointed out.

2. Verification

Describe the strategy used for verifying that the module works according to specification.

 How is the module simulated?

 Which functions and parameters are covered and which are not covered by the simulations? (referred to specification)

 How is the other functions and parameters verified?

 What are the results compared to (Matlab model, C-program, Behavioral model, manually from specification, other)

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3. Deliverables

3.1 Digital modules

The following documents should be included in the module documentation:

 RTL-code(s)

 Schematics

 Test bench(es)

The following documents may be included in the module documentation (optional):

 Result from simulation

 Synthesis script

 Synthesis constraints (if other than project common constraints)

 Synthesis report(s)

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References

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