K10 Sub-Family Reference Manual
Supports: MK10DN512VLK10, MK10DN512VMB10
Document Number: K10P81M100SF2V2RM
Rev. 2 Jun 2012
Contents
Section number Title Page
Chapter 1
About This Document
1.1 Overview...53
1.1.1 Purpose...53
1.1.2 Audience...53
1.2 Conventions...53
1.2.1 Numbering systems...53
1.2.2 Typographic notation...54
1.2.3 Special terms...54
Chapter 2 Introduction
2.1 Overview...552.2 Module Functional Categories...55
2.2.1 ARM Cortex-M4 Core Modules...56
2.2.2 System Modules...57
2.2.3 Memories and Memory Interfaces...58
2.2.4 Clocks...58
2.2.5 Security and Integrity modules...59
2.2.6 Analog modules...59
2.2.7 Timer modules...60
2.2.8 Communication interfaces...61
2.2.9 Human-machine interfaces...61
2.3 Orderable part numbers...62
Chapter 3
Chip Configuration
3.1 Introduction...63Section number Title Page
3.2 Core modules...63
3.2.1 ARM Cortex-M4 Core Configuration...63
3.2.2 Nested Vectored Interrupt Controller (NVIC) Configuration...65
3.2.3 Asynchronous Wake-up Interrupt Controller (AWIC) Configuration...71
3.2.4 JTAG Controller Configuration...73
3.3 System modules...73
3.3.1 SIM Configuration...73
3.3.2 System Mode Controller (SMC) Configuration...74
3.3.3 PMC Configuration...75
3.3.4 Low-Leakage Wake-up Unit (LLWU) Configuration...75
3.3.5 MCM Configuration...77
3.3.6 Crossbar Switch Configuration...78
3.3.7 Memory Protection Unit (MPU) Configuration...80
3.3.8 Peripheral Bridge Configuration...83
3.3.9 DMA request multiplexer configuration...84
3.3.10 DMA Controller Configuration...87
3.3.11 External Watchdog Monitor (EWM) Configuration...88
3.3.12 Watchdog Configuration...89
3.4 Clock modules...90
3.4.1 MCG Configuration...90
3.4.2 OSC Configuration...91
3.4.3 RTC OSC configuration...92
3.5 Memories and memory interfaces...92
3.5.1 Flash Memory Configuration...92
3.5.2 Flash Memory Controller Configuration...95
3.5.3 SRAM Configuration...96
3.5.4 SRAM Controller Configuration...99
Section number Title Page
3.5.5 System Register File Configuration...100
3.5.6 VBAT Register File Configuration...100
3.5.7 EzPort Configuration...101
3.5.8 FlexBus Configuration...102
3.6 Security...105
3.6.1 CRC Configuration...105
Section number Title Page
3.7 Analog...106
3.7.1 16-bit SAR ADC with PGA Configuration...106
3.7.2 CMP Configuration...114
3.7.3 12-bit DAC Configuration...116
3.7.4 VREF Configuration...117
3.8 Timers...118
3.8.1 PDB Configuration...118
3.8.2 FlexTimer Configuration...121
3.8.3 PIT Configuration...125
3.8.4 Low-power timer configuration...126
3.8.5 CMT Configuration...128
3.8.6 RTC configuration...129
3.9 Communication interfaces...130
3.9.1 CAN Configuration...130
3.9.2 SPI configuration...132
3.9.3 I2C Configuration...136
3.9.4 UART Configuration...136
3.9.5 SDHC Configuration...139
3.9.6 I2S configuration...141
3.10 Human-machine interfaces...143
3.10.1 GPIO configuration...143
3.10.2 TSI Configuration...144
Chapter 4 Memory Map
4.1 Introduction...1474.2 System memory map...147
4.2.1 Aliased bit-band regions...148
4.3 Flash Memory Map...149
4.3.1 Alternate Non-Volatile IRC User Trim Description...150
Section number Title Page
4.4 SRAM memory map...150
4.5 Peripheral bridge (AIPS-Lite0 and AIPS-Lite1) memory maps...150
4.5.1 Peripheral Bridge 0 (AIPS-Lite 0) Memory Map...151
4.5.2 Peripheral Bridge 1 (AIPS-Lite 1) Memory Map...154
4.6 Private Peripheral Bus (PPB) memory map...158
Chapter 5 Clock Distribution
5.1 Introduction...1595.2 Programming model...159
5.3 High-Level device clocking diagram...159
5.4 Clock definitions...160
5.4.1 Device clock summary...161
5.5 Internal clocking requirements...163
5.5.1 Clock divider values after reset...164
5.5.2 VLPR mode clocking...164
5.6 Clock Gating...165
5.7 Module clocks...165
5.7.1 PMC 1-kHz LPO clock...166
5.7.2 WDOG clocking...167
5.7.3 Debug trace clock...167
5.7.4 PORT digital filter clocking...168
5.7.5 LPTMR clocking...168
5.7.6 FlexCAN clocking...169
5.7.7 UART clocking...169
5.7.8 SDHC clocking...169
5.7.9 I2S/SAI clocking...170
5.7.10 TSI clocking...170
Section number Title Page
Chapter 6 Reset and Boot
6.1 Introduction...173
6.2 Reset...174
6.2.1 Power-on reset (POR)...174
6.2.2 System reset sources...174
6.2.3 MCU Resets...178
6.2.4 Reset Pin ...180
6.2.5 Debug resets...180
6.3 Boot...181
6.3.1 Boot sources...181
6.3.2 Boot options...182
6.3.3 FOPT boot options...182
6.3.4 Boot sequence...183
Chapter 7 Power Management
7.1 Introduction...1857.2 Power modes...185
7.3 Entering and exiting power modes...187
7.4 Power mode transitions...188
7.5 Power modes shutdown sequencing...189
7.6 Module Operation in Low Power Modes...189
7.7 Clock Gating...192
Chapter 8 Security
8.1 Introduction...1938.2 Flash Security...193
8.3 Security Interactions with other Modules...194
8.3.1 Security interactions with FlexBus...194
8.3.2 Security Interactions with EzPort...194
Section number Title Page
8.3.3 Security Interactions with Debug...194
Chapter 9 Debug
9.1 Introduction...1979.1.1 References...199
9.2 The Debug Port...199
9.2.1 JTAG-to-SWD change sequence...200
9.2.2 JTAG-to-cJTAG change sequence...200
9.3 Debug Port Pin Descriptions...201
9.4 System TAP connection...201
9.4.1 IR Codes...201
9.5 JTAG status and control registers...202
9.5.1 MDM-AP Control Register...203
9.5.2 MDM-AP Status Register...205
9.6 Debug Resets...206
9.7 AHB-AP...207
9.8 ITM...208
9.9 Core Trace Connectivity...208
9.10 Embedded Trace Macrocell v3.5 (ETM)...209
9.11 Coresight Embedded Trace Buffer (ETB)...210
9.11.1 Performance Profiling with the ETB...210
9.11.2 ETB Counter Control...211
9.12 TPIU...211
9.13 DWT...211
9.14 Debug in Low Power Modes...212
9.14.1 Debug Module State in Low Power Modes...213
9.15 Debug & Security...213
Section number Title Page
Chapter 10
Signal Multiplexing and Signal Descriptions
10.1 Introduction...215
10.2 Signal Multiplexing Integration...215
10.2.1 Port control and interrupt module features...216
10.2.2 PCRn reset values for port A...216
10.2.3 Clock gating...216
10.2.4 Signal multiplexing constraints...216
10.3 Pinout...217
10.3.1 K10 Signal Multiplexing and Pin Assignments...217
10.3.2 K10 Pinouts...221
10.4 Module Signal Description Tables...223
10.4.1 Core Modules...224
10.4.2 System Modules...224
10.4.3 Clock Modules...225
10.4.4 Memories and Memory Interfaces...225
10.4.5 Analog...228
10.4.6 Timer Modules...230
10.4.7 Communication Interfaces...231
10.4.8 Human-Machine Interfaces (HMI)...234
Chapter 11 Port control and interrupts (PORT)
11.1 Introduction...23711.2 Overview...237
11.2.1 Features...237
11.2.2 Modes of operation...238
11.3 External signal description...239
11.4 Detailed signal description...239
Section number Title Page
11.5 Memory map and register definition...239
11.5.1 Pin Control Register n (PORTx_PCRn)...245
11.5.2 Global Pin Control Low Register (PORTx_GPCLR)...248
11.5.3 Global Pin Control High Register (PORTx_GPCHR)...248
11.5.4 Interrupt Status Flag Register (PORTx_ISFR)...249
11.6 Functional description...249
11.6.1 Pin control...249
11.6.2 Global pin control...250
11.6.3 External interrupts...250
Chapter 12 System Integration Module (SIM)
12.1 Introduction...25312.1.1 Features...253
12.2 Memory map and register definition...254
12.2.1 System Options Register 1 (SIM_SOPT1)...255
12.2.2 System Options Register 2 (SIM_SOPT2)...257
12.2.3 System Options Register 4 (SIM_SOPT4)...259
12.2.4 System Options Register 5 (SIM_SOPT5)...261
12.2.5 System Options Register 7 (SIM_SOPT7)...263
12.2.6 System Device Identification Register (SIM_SDID)...265
12.2.7 System Clock Gating Control Register 1 (SIM_SCGC1)...266
12.2.8 System Clock Gating Control Register 2 (SIM_SCGC2)...267
12.2.9 System Clock Gating Control Register 3 (SIM_SCGC3)...268
12.2.10 System Clock Gating Control Register 4 (SIM_SCGC4)...270
12.2.11 System Clock Gating Control Register 5 (SIM_SCGC5)...272
12.2.12 System Clock Gating Control Register 6 (SIM_SCGC6)...274
12.2.13 System Clock Gating Control Register 7 (SIM_SCGC7)...276
12.2.14 System Clock Divider Register 1 (SIM_CLKDIV1)...277
12.2.15 System Clock Divider Register 2 (SIM_CLKDIV2)...279
Section number Title Page
12.2.16 Flash Configuration Register 1 (SIM_FCFG1)...280
12.2.17 Flash Configuration Register 2 (SIM_FCFG2)...282
12.2.18 Unique Identification Register High (SIM_UIDH)...283
12.2.19 Unique Identification Register Mid-High (SIM_UIDMH)...284
12.2.20 Unique Identification Register Mid Low (SIM_UIDML)...284
12.2.21 Unique Identification Register Low (SIM_UIDL)...285
12.3 Functional description...285
Chapter 13 Reset Control Module (RCM)
13.1 Introduction...28713.2 Reset memory map and register descriptions...287
13.2.1 System Reset Status Register 0 (RCM_SRS0)...287
13.2.2 System Reset Status Register 1 (RCM_SRS1)...289
13.2.3 Reset Pin Filter Control register (RCM_RPFC)...290
13.2.4 Reset Pin Filter Width register (RCM_RPFW)...291
13.2.5 Mode Register (RCM_MR)...293
Chapter 14 System Mode Controller
14.1 Introduction...29514.2 Modes of operation...295
14.3 Memory map and register descriptions...297
14.3.1 Power Mode Protection register (SMC_PMPROT)...298
14.3.2 Power Mode Control register (SMC_PMCTRL)...299
14.3.3 VLLS Control register (SMC_VLLSCTRL)...300
14.3.4 Power Mode Status register (SMC_PMSTAT)...301
14.4 Functional description...302
14.4.1 Power mode transitions...302
Section number Title Page
14.4.2 Power mode entry/exit sequencing...305
14.4.3 Run modes...307
14.4.4 Wait modes...309
14.4.5 Stop modes...310
14.4.6 Debug in low power modes...313
Chapter 15 Power Management Controller
15.1 Introduction...31515.2 Features...315
15.3 Low-voltage detect (LVD) system...315
15.3.1 LVD reset operation...316
15.3.2 LVD interrupt operation...316
15.3.3 Low-voltage warning (LVW) interrupt operation...316
15.4 I/O retention...317
15.5 Memory map and register descriptions...317
15.5.1 Low Voltage Detect Status And Control 1 register (PMC_LVDSC1)...318
15.5.2 Low Voltage Detect Status And Control 2 register (PMC_LVDSC2)...319
15.5.3 Regulator Status And Control register (PMC_REGSC)...320
Chapter 16 Low-Leakage Wakeup Unit (LLWU)
16.1 Introduction...32316.1.1 Features...323
16.1.2 Modes of operation...324
16.1.3 Block diagram...325
16.2 LLWU signal descriptions...326
16.3 Memory map/register definition...327
16.3.1 LLWU Pin Enable 1 register (LLWU_PE1)...328
16.3.2 LLWU Pin Enable 2 register (LLWU_PE2)...329
16.3.3 LLWU Pin Enable 3 register (LLWU_PE3)...330
Section number Title Page
16.3.4 LLWU Pin Enable 4 register (LLWU_PE4)...331
16.3.5 LLWU Module Enable register (LLWU_ME)...332
16.3.6 LLWU Flag 1 register (LLWU_F1)...334
16.3.7 LLWU Flag 2 register (LLWU_F2)...335
16.3.8 LLWU Flag 3 register (LLWU_F3)...337
16.3.9 LLWU Pin Filter 1 register (LLWU_FILT1)...339
16.3.10 LLWU Pin Filter 2 register (LLWU_FILT2)...340
16.3.11 LLWU Reset Enable register (LLWU_RST)...341
16.4 Functional description...342
16.4.1 LLS mode...342
16.4.2 VLLS modes...342
16.4.3 Initialization...343
Chapter 17 Miscellaneous Control Module (MCM)
17.1 Introduction...34517.1.1 Features...345
17.2 Memory map/register descriptions...345
17.2.1 Crossbar Switch (AXBS) Slave Configuration (MCM_PLASC)...346
17.2.2 Crossbar Switch (AXBS) Master Configuration (MCM_PLAMC)...347
17.2.3 Control Register (MCM_CR)...347
17.2.4 Interrupt Status Register (MCM_ISR)...349
17.2.5 ETB Counter Control register (MCM_ETBCC)...350
17.2.6 ETB Reload register (MCM_ETBRL)...351
17.2.7 ETB Counter Value register (MCM_ETBCNT)...351
17.2.8 Process ID register (MCM_PID)...352
Section number Title Page
17.3 Functional description...352
17.3.1 Interrupts...352
Chapter 18 Crossbar Switch (AXBS)
18.1 Introduction...35518.1.1 Features...355
18.2 Memory Map / Register Definition...356
18.2.1 Priority Registers Slave (AXBS_PRSn)...357
18.2.2 Control Register (AXBS_CRSn)...360
18.2.3 Master General Purpose Control Register (AXBS_MGPCRn)...362
18.3 Functional Description...362
18.3.1 General operation...362
18.3.2 Register coherency...364
18.3.3 Arbitration...364
18.4 Initialization/application information...367
Chapter 19 Memory Protection Unit (MPU)
19.1 Introduction...36919.2 Overview...369
19.2.1 Block diagram...369
19.2.2 Features...370
19.3 Memory map/register definition...371
19.3.1 Control/Error Status Register (MPU_CESR)...375
19.3.2 Error Address Register, slave port n (MPU_EARn)...376
19.3.3 Error Detail Register, slave port n (MPU_EDRn)...377
19.3.4 Region Descriptor n, Word 0 (MPU_RGDn_WORD0)...378
19.3.5 Region Descriptor n, Word 1 (MPU_RGDn_WORD1)...378
19.3.6 Region Descriptor n, Word 2 (MPU_RGDn_WORD2)...379
19.3.7 Region Descriptor n, Word 3 (MPU_RGDn_WORD3)...382
Section number Title Page
19.3.8 Region Descriptor Alternate Access Control n (MPU_RGDAACn)...383
19.4 Functional description...385
19.4.1 Access evaluation macro...385
19.4.2 Putting it all together and error terminations...386
19.4.3 Power management...387
19.5 Initialization information...387
19.6 Application information...387
Chapter 20 Peripheral Bridge (AIPS-Lite)
20.1 Introduction...39120.1.1 Features...391
20.1.2 General operation...392
20.2 Memory map/register definition...392
20.2.1 Master Privilege Register A (AIPSx_MPRA)...394
20.2.2 Peripheral Access Control Register (AIPSx_PACRn)...397
20.2.3 Peripheral Access Control Register (AIPSx_PACRn)...402
20.3 Functional description...407
20.3.1 Access support...407
Chapter 21 Direct Memory Access Multiplexer (DMAMUX)
21.1 Introduction...40921.1.1 Overview...409
21.1.2 Features...410
21.1.3 Modes of operation...410
21.2 External signal description...411
21.3 Memory map/register definition...411
21.3.1 Channel Configuration register (DMAMUX_CHCFGn)...412
21.4 Functional description...413
21.4.1 DMA channels with periodic triggering capability...413
Section number Title Page
21.4.2 DMA channels with no triggering capability...415
21.4.3 "Always enabled" DMA sources...415
21.5 Initialization/application information...416
21.5.1 Reset...417
21.5.2 Enabling and configuring sources...417
Chapter 22 Direct Memory Access Controller (eDMA)
22.1 Introduction...42122.1.1 Block diagram...421
22.1.2 Block parts...422
22.1.3 Features...423
22.2 Modes of operation...425
22.3 Memory map/register definition...425
22.3.1 Control Register (DMA_CR)...436
22.3.2 Error Status Register (DMA_ES)...438
22.3.3 Enable Request Register (DMA_ ERQ )...440
22.3.4 Enable Error Interrupt Register (DMA_ EEI )...442
22.3.5 Clear Enable Error Interrupt Register (DMA_CEEI)...445
22.3.6 Set Enable Error Interrupt Register (DMA_SEEI)...446
22.3.7 Clear Enable Request Register (DMA_CERQ)...447
22.3.8 Set Enable Request Register (DMA_SERQ)...448
22.3.9 Clear DONE Status Bit Register (DMA_CDNE)...449
22.3.10 Set START Bit Register (DMA_SSRT)...450
22.3.11 Clear Error Register (DMA_CERR)...451
22.3.12 Clear Interrupt Request Register (DMA_CINT)...452
22.3.13 Interrupt Request Register (DMA_ INT )...453
22.3.14 Error Register (DMA_ ERR )...455
22.3.15 Hardware Request Status Register (DMA_ HRS )...458
22.3.16 Channel n Priority Register (DMA_DCHPRIn)...460
Section number Title Page
22.3.17 TCD Source Address (DMA_TCDn_SADDR)...461
22.3.18 TCD Signed Source Address Offset (DMA_TCDn_SOFF)...461
22.3.19 TCD Transfer Attributes (DMA_TCDn_ATTR)...462
22.3.20 TCD Minor Byte Count (Minor Loop Disabled) (DMA_TCDn_NBYTES_MLNO)...463
22.3.21 TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled) (DMA_TCDn_NBYTES_MLOFFNO)...463
22.3.22 TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled) (DMA_TCDn_NBYTES_MLOFFYES)...464
22.3.23 TCD Last Source Address Adjustment (DMA_TCDn_SLAST)...466
22.3.24 TCD Destination Address (DMA_TCDn_DADDR)...466
22.3.25 TCD Signed Destination Address Offset (DMA_TCDn_DOFF)...467
22.3.26 TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) (DMA_TCDn_CITER_ELINKYES)...467
22.3.27 TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) (DMA_TCDn_CITER_ELINKNO)...468
22.3.28 TCD Last Destination Address Adjustment/Scatter Gather Address (DMA_TCDn_DLASTSGA)...469
22.3.29 TCD Control and Status (DMA_TCDn_CSR)...470
22.3.30 TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) (DMA_TCDn_BITER_ELINKYES)...472
22.3.31 TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) (DMA_TCDn_BITER_ELINKNO)...473
22.4 Functional description...474
22.4.1 eDMA basic data flow...474
22.4.2 Error reporting and handling...477
22.4.3 Channel preemption...479
22.4.4 Performance...479
22.5 Initialization/application information...484
22.5.1 eDMA initialization...484
22.5.2 Programming errors...486
Section number Title Page
22.5.3 Arbitration mode considerations...486
22.5.4 Performing DMA transfers (examples)...487
22.5.5 Monitoring transfer descriptor status...491
22.5.6 Channel Linking...492
22.5.7 Dynamic programming...494
Chapter 23 External Watchdog Monitor (EWM)
23.1 Introduction...49923.1.1 Features...499
23.1.2 Modes of Operation...500
23.1.3 Block Diagram...501
23.2 EWM Signal Descriptions...502
23.3 Memory Map/Register Definition...502
23.3.1 Control Register (EWM_CTRL)...502
23.3.2 Service Register (EWM_SERV)...503
23.3.3 Compare Low Register (EWM_CMPL)...503
23.3.4 Compare High Register (EWM_CMPH)...504
23.3.5 Clock Prescaler Register (EWM_CLKPRESCALER)...505
23.4 Functional Description...505
23.4.1 The EWM_out Signal...505
23.4.2 The EWM_in Signal...506
23.4.3 EWM Counter...507
23.4.4 EWM Compare Registers...507
23.4.5 EWM Refresh Mechanism...507
23.4.6 EWM Interrupt...508
23.4.7 Counter clock prescaler...508
Chapter 24
Watchdog Timer (WDOG)
24.1 Introduction...509Section number Title Page
24.2 Features...509
24.3 Functional overview...511
24.3.1 Unlocking and updating the watchdog...512
24.3.2 Watchdog configuration time (WCT)...513
24.3.3 Refreshing the watchdog...514
24.3.4 Windowed mode of operation...514
24.3.5 Watchdog disabled mode of operation...514
24.3.6 Low-power modes of operation...515
24.3.7 Debug modes of operation...515
24.4 Testing the watchdog...516
24.4.1 Quick test...516
24.4.2 Byte test...517
24.5 Backup reset generator...518
24.6 Generated resets and interrupts...518
24.7 Memory map and register definition...519
24.7.1 Watchdog Status and Control Register High (WDOG_STCTRLH)...520
24.7.2 Watchdog Status and Control Register Low (WDOG_STCTRLL)...521
24.7.3 Watchdog Time-out Value Register High (WDOG_TOVALH)...522
24.7.4 Watchdog Time-out Value Register Low (WDOG_TOVALL)...522
24.7.5 Watchdog Window Register High (WDOG_WINH)...523
24.7.6 Watchdog Window Register Low (WDOG_WINL)...523
24.7.7 Watchdog Refresh register (WDOG_REFRESH)...524
24.7.8 Watchdog Unlock register (WDOG_UNLOCK)...524
24.7.9 Watchdog Timer Output Register High (WDOG_TMROUTH)...524
24.7.10 Watchdog Timer Output Register Low (WDOG_TMROUTL)...525
24.7.11 Watchdog Reset Count register (WDOG_RSTCNT)...525
24.7.12 Watchdog Prescaler register (WDOG_PRESC)...526
24.8 Watchdog operation with 8-bit access...526
24.8.1 General guideline...526
Section number Title Page
24.8.2 Refresh and unlock operations with 8-bit access...526
24.9 Restrictions on watchdog operation...527
Chapter 25 Multipurpose Clock Generator (MCG)
25.1 Introduction...53125.1.1 Features...531
25.1.2 Modes of Operation...534
25.2 External Signal Description...535
25.3 Memory Map/Register Definition...535
25.3.1 MCG Control 1 Register (MCG_C1)...536
25.3.2 MCG Control 2 Register (MCG_C2)...537
25.3.3 MCG Control 3 Register (MCG_C3)...538
25.3.4 MCG Control 4 Register (MCG_C4)...539
25.3.5 MCG Control 5 Register (MCG_C5)...540
25.3.6 MCG Control 6 Register (MCG_C6)...541
25.3.7 MCG Status Register (MCG_S)...543
25.3.8 MCG Status and Control Register (MCG_SC)...544
25.3.9 MCG Auto Trim Compare Value High Register (MCG_ATCVH)...546
25.3.10 MCG Auto Trim Compare Value Low Register (MCG_ATCVL)...546
25.3.11 MCG Control 7 Register (MCG_C7)...546
25.3.12 MCG Control 8 Register (MCG_C8)...547
25.3.13 MCG Control 9 Register (MCG_C9)...548
25.3.14 MCG Control 10 Register (MCG_C10)...548
25.4 Functional Description...549
25.4.1 MCG mode state diagram...549
25.4.2 Low Power Bit Usage...553
25.4.3 MCG Internal Reference Clocks...553
25.4.4 External Reference Clock...554
25.4.5 MCG Fixed frequency clock ...554
Section number Title Page
25.4.6 MCG PLL clock ...555 25.4.7 MCG Auto TRIM (ATM)...555 25.5 Initialization / Application information...556 25.5.1 MCG module initialization sequence...556 25.5.2 Using a 32.768 kHz reference...559 25.5.3 MCG mode switching...559
Chapter 26 Oscillator (OSC)
26.1 Introduction...569 26.2 Features and Modes...569 26.3 Block Diagram...570 26.4 OSC Signal Descriptions...570 26.5 External Crystal / Resonator Connections...571 26.6 External Clock Connections...572 26.7 Memory Map/Register Definitions...573 26.7.1 OSC Memory Map/Register Definition...573 26.8 Functional Description...574 26.8.1 OSC Module States...574 26.8.2 OSC Module Modes...576 26.8.3 Counter...578 26.8.4 Reference Clock Pin Requirements...578 26.9 Reset...578 26.10 Low Power Modes Operation...579 26.11 Interrupts...579
Chapter 27 RTC Oscillator
27.1 Introduction...581 27.1.1 Features and Modes...581 27.1.2 Block Diagram...581
Section number Title Page
27.2 RTC Signal Descriptions...582 27.2.1 EXTAL32 — Oscillator Input...582 27.2.2 XTAL32 — Oscillator Output...582 27.3 External Crystal Connections...583 27.4 Memory Map/Register Descriptions...583 27.5 Functional Description...583 27.6 Reset Overview...584 27.7 Interrupts...584
Chapter 28
Flash Memory Controller (FMC)
28.1 Introduction...585 28.1.1 Overview...585 28.1.2 Features...586 28.2 Modes of operation...586 28.3 External signal description...586 28.4 Memory map and register descriptions...587 28.4.1 Flash Access Protection Register (FMC_PFAPR)...593 28.4.2 Flash Bank 0 Control Register (FMC_PFB0CR)...596 28.4.3 Flash Bank 1 Control Register (FMC_PFB1CR)...599 28.4.4 Cache Tag Storage (FMC_TAGVDW0Sn)...601 28.4.5 Cache Tag Storage (FMC_TAGVDW1Sn)...602 28.4.6 Cache Tag Storage (FMC_TAGVDW2Sn)...603 28.4.7 Cache Tag Storage (FMC_TAGVDW3Sn)...604 28.4.8 Cache Data Storage (upper word) (FMC_DATAW0SnU)...604 28.4.9 Cache Data Storage (lower word) (FMC_DATAW0SnL)...605 28.4.10 Cache Data Storage (upper word) (FMC_DATAW1SnU)...605 28.4.11 Cache Data Storage (lower word) (FMC_DATAW1SnL)...606 28.4.12 Cache Data Storage (upper word) (FMC_DATAW2SnU)...606 28.4.13 Cache Data Storage (lower word) (FMC_DATAW2SnL)...607
Section number Title Page
28.4.14 Cache Data Storage (upper word) (FMC_DATAW3SnU)...607 28.4.15 Cache Data Storage (lower word) (FMC_DATAW3SnL)...608 28.5 Functional description...608 28.5.1 Default configuration...608 28.5.2 Configuration options...609 28.5.3 Wait states...609 28.5.4 Speculative reads...610 28.6 Initialization and application information...611
Chapter 29
Flash Memory Module (FTFL)
29.1 Introduction...613 29.1.1 Features...614 29.1.2 Block Diagram...615 29.1.3 Glossary...615 29.2 External Signal Description...617 29.3 Memory Map and Registers...617 29.3.1 Flash Configuration Field Description...617 29.3.2 Program Flash IFR Map...617 29.3.3 Register Descriptions...618 29.4 Functional Description...627 29.4.1 Program Flash Memory Swap...627 29.4.2 Flash Protection...628 29.4.3 Interrupts...628 29.4.4 Flash Operation in Low-Power Modes...629 29.4.5 Functional Modes of Operation...629 29.4.6 Flash Reads and Ignored Writes...630 29.4.7 Read While Write (RWW)...630 29.4.8 Flash Program and Erase...630
Section number Title Page
29.4.9 Flash Command Operations...630 29.4.10 Margin Read Commands...636 29.4.11 Flash Command Description...637 29.4.12 Security...659 29.4.13 Reset Sequence...661
Chapter 30
External Bus Interface (FlexBus)
30.1 Introduction...663 30.1.1 Definition...663 30.1.2 Features...664 30.2 Signal descriptions...664 30.3 Memory Map/Register Definition...667 30.3.1 Chip Select Address Register (FB_CSARn)...669 30.3.2 Chip Select Mask Register (FB_CSMRn)...669 30.3.3 Chip Select Control Register (FB_CSCRn)...670 30.3.4 Chip Select port Multiplexing Control Register (FB_CSPMCR)...673 30.4 Functional description...674 30.4.1 Modes of operation...675 30.4.2 Address comparison...675 30.4.3 Address driven on address bus...675 30.4.4 Connecting address/data lines...675 30.4.5 Bit ordering...676 30.4.6 Data transfer signals...676 30.4.7 Signal transitions...676 30.4.8 Data-byte alignment and physical connections...676 30.4.9 Address/data bus multiplexing...677 30.4.10 Data transfer states...678
Section number Title Page
30.4.11 FlexBus Timing Examples...679 30.4.12 Burst cycles...698 30.4.13 Extended Transfer Start/Address Latch Enable...706 30.4.14 Bus errors...707 30.5 Initialization/Application Information...708 30.5.1 Initializing a chip-select...708 30.5.2 Reconfiguring a chip-select...708
Chapter 31 EzPort
31.1 Overview...709 31.1.1 Introduction...709 31.1.2 Features...710 31.1.3 Modes of operation...710 31.2 External signal description...711 31.2.1 EzPort Clock (EZP_CK)...711 31.2.2 EzPort Chip Select (EZP_CS)...711 31.2.3 EzPort Serial Data In (EZP_D)...712 31.2.4 EzPort Serial Data Out (EZP_Q)...712 31.3 Command definition...712 31.3.1 Command descriptions...713 31.4 Flash memory map for EzPort access...717
Chapter 32
Cyclic Redundancy Check (CRC)
32.1 Introduction...719 32.1.1 Features...719 32.1.2 Block diagram...720 32.1.3 Modes of operation...720 32.2 Memory map and register descriptions...720 32.2.1 CRC Data register (CRC_CRC)...721
Section number Title Page
32.2.2 CRC Polynomial register (CRC_GPOLY)...722 32.2.3 CRC Control register (CRC_CTRL)...723 32.3 Functional description...724 32.3.1 CRC initialization/reinitialization...724 32.3.2 CRC calculations...724 32.3.3 Transpose feature...725 32.3.4 CRC result complement...727
Chapter 33
Analog-to-Digital Converter (ADC)
33.1 Introduction...729 33.1.1 Features...729 33.1.2 Block diagram...730 33.2 ADC Signal Descriptions...731 33.2.1 Analog Power (VDDA)...732 33.2.2 Analog Ground (VSSA)...732 33.2.3 Voltage Reference Select...732 33.2.4 Analog Channel Inputs (ADx)...733 33.2.5 Differential Analog Channel Inputs (DADx)...733 33.3 Register definition...733 33.3.1 ADC Status and Control Registers 1 (ADCx_SC1n)...736 33.3.2 ADC Configuration Register 1 (ADCx_CFG1)...739 33.3.3 ADC Configuration Register 2 (ADCx_CFG2)...741 33.3.4 ADC Data Result Register (ADCx_Rn)...742 33.3.5 Compare Value Registers (ADCx_CVn)...743 33.3.6 Status and Control Register 2 (ADCx_SC2)...744 33.3.7 Status and Control Register 3 (ADCx_SC3)...746 33.3.8 ADC Offset Correction Register (ADCx_OFS)...748 33.3.9 ADC Plus-Side Gain Register (ADCx_PG)...748 33.3.10 ADC Minus-Side Gain Register (ADCx_MG)...749
Section number Title Page
33.3.11 ADC Plus-Side General Calibration Value Register (ADCx_CLPD)...749 33.3.12 ADC Plus-Side General Calibration Value Register (ADCx_CLPS)...750 33.3.13 ADC Plus-Side General Calibration Value Register (ADCx_CLP4)...750 33.3.14 ADC Plus-Side General Calibration Value Register (ADCx_CLP3)...751 33.3.15 ADC Plus-Side General Calibration Value Register (ADCx_CLP2)...751 33.3.16 ADC Plus-Side General Calibration Value Register (ADCx_CLP1)...752 33.3.17 ADC Plus-Side General Calibration Value Register (ADCx_CLP0)...752 33.3.18 ADC PGA Register (ADCx_PGA)...753 33.3.19 ADC Minus-Side General Calibration Value Register (ADCx_CLMD)...754 33.3.20 ADC Minus-Side General Calibration Value Register (ADCx_CLMS)...755 33.3.21 ADC Minus-Side General Calibration Value Register (ADCx_CLM4)...755 33.3.22 ADC Minus-Side General Calibration Value Register (ADCx_CLM3)...756 33.3.23 ADC Minus-Side General Calibration Value Register (ADCx_CLM2)...756 33.3.24 ADC Minus-Side General Calibration Value Register (ADCx_CLM1)...757 33.3.25 ADC Minus-Side General Calibration Value Register (ADCx_CLM0)...757 33.4 Functional description...757 33.4.1 PGA functional description...758 33.4.2 Clock select and divide control...759 33.4.3 Voltage reference selection...759 33.4.4 Hardware trigger and channel selects...760 33.4.5 Conversion control...761 33.4.6 Automatic compare function...768 33.4.7 Calibration function...769 33.4.8 User-defined offset function...771 33.4.9 Temperature sensor...772 33.4.10 MCU wait mode operation...773 33.4.11 MCU Normal Stop mode operation...773 33.4.12 MCU Low-Power Stop mode operation...774
Section number Title Page
33.5 Initialization information...775 33.5.1 ADC module initialization example...775 33.6 Application information...777 33.6.1 External pins and routing...777 33.6.2 Sources of error...779
Chapter 34 Comparator (CMP)
34.1 Introduction...785 34.2 CMP features...785 34.3 6-bit DAC key features...786 34.4 ANMUX key features...787 34.5 CMP, DAC and ANMUX diagram...787 34.6 CMP block diagram...788 34.7 Memory map/register definitions...790 34.7.1 CMP Control Register 0 (CMPx_CR0)...790 34.7.2 CMP Control Register 1 (CMPx_CR1)...791 34.7.3 CMP Filter Period Register (CMPx_FPR)...793 34.7.4 CMP Status and Control Register (CMPx_SCR)...793 34.7.5 DAC Control Register (CMPx_DACCR)...794 34.7.6 MUX Control Register (CMPx_MUXCR)...795 34.8 CMP functional description...796 34.8.1 CMP functional modes...796 34.8.2 Power modes...805 34.8.3 Startup and operation...806 34.8.4 Low-pass filter...807 34.9 CMP interrupts...809 34.10 CMP DMA support...809 34.11 Digital-to-analog converter block diagram...810
Section number Title Page
34.12 DAC functional description...810 34.12.1 Voltage reference source select...810 34.13 DAC resets...811 34.14 DAC clocks...811 34.15 DAC interrupts...811
Chapter 35
12-bit Digital-to-Analog Converter (DAC)
35.1 Introduction...813 35.2 Features...813 35.3 Block diagram...814 35.4 Memory map/register definition...815 35.4.1 DAC Data Low Register (DACx_DATnL)...816 35.4.2 DAC Data High Register (DACx_DATnH)...816 35.4.3 DAC Status Register (DACx_SR)...817 35.4.4 DAC Control Register (DACx_C0)...817 35.4.5 DAC Control Register 1 (DACx_C1)...818 35.4.6 DAC Control Register 2 (DACx_C2)...819 35.5 Functional description...820 35.5.1 DAC data buffer operation...820 35.5.2 DMA operation...821 35.5.3 Resets...821 35.5.4 Low-Power mode operation...821
Chapter 36
Voltage Reference (VREFV1)
36.1 Introduction...823 36.1.1 Overview...824 36.1.2 Features...824 36.1.3 Modes of Operation...825 36.1.4 VREF Signal Descriptions...825
Section number Title Page
36.2 Memory Map and Register Definition...826 36.2.1 VREF Trim Register (VREF_TRM)...826 36.2.2 VREF Status and Control Register (VREF_SC)...827 36.3 Functional Description...828 36.3.1 Voltage Reference Disabled, SC[VREFEN] = 0...828 36.3.2 Voltage Reference Enabled, SC[VREFEN] = 1...829 36.4 Initialization/Application Information...830
Chapter 37
Programmable Delay Block (PDB)
37.1 Introduction...831 37.1.1 Features...831 37.1.2 Implementation...832 37.1.3 Back-to-back acknowledgment connections...833 37.1.4 DAC External Trigger Input Connections...833 37.1.5 Block diagram...833 37.1.6 Modes of operation...835 37.2 PDB signal descriptions...835 37.3 Memory map and register definition...835 37.3.1 Status and Control Register (PDBx_SC)...837 37.3.2 Modulus Register (PDBx_MOD)...839 37.3.3 Counter Register (PDBx_CNT)...840 37.3.4 Interrupt Delay Register (PDBx_IDLY)...840 37.3.5 Channel n Control Register 1 (PDBx_CHnC1)...841 37.3.6 Channel n Status Register (PDBx_CHnS)...842 37.3.7 Channel n Delay 0 Register (PDBx_CHnDLY0)...842 37.3.8 Channel n Delay 1 Register (PDBx_CHnDLY1)...843 37.3.9 DAC Interval Trigger n Control Register (PDBx_DACINTCn)...843 37.3.10 DAC Interval n Register (PDBx_DACINTn)...844 37.3.11 Pulse-Out n Enable Register (PDBx_POEN)...844
Section number Title Page
37.3.12 Pulse-Out n Delay Register (PDBx_POnDLY)...845 37.4 Functional description...845 37.4.1 PDB pre-trigger and trigger outputs...845 37.4.2 PDB trigger input source selection...847 37.4.3 DAC interval trigger outputs...847 37.4.4 Pulse-Out's...848 37.4.5 Updating the delay registers...848 37.4.6 Interrupts...850 37.4.7 DMA...850 37.5 Application information...850 37.5.1 Impact of using the prescaler and multiplication factor on timing resolution...850
Chapter 38
FlexTimer Module (FTM)
38.1 Introduction...853 38.1.1 FlexTimer philosophy...853 38.1.2 Features...854 38.1.3 Modes of operation...855 38.1.4 Block diagram...856 38.2 FTM signal descriptions...858 38.3 Memory map and register definition...858 38.3.1 Memory map...858 38.3.2 Register descriptions...859 38.3.3 Status And Control (FTMx_SC)...865 38.3.4 Counter (FTMx_CNT)...866 38.3.5 Modulo (FTMx_MOD)...867 38.3.6 Channel (n) Status And Control (FTMx_CnSC)...868 38.3.7 Channel (n) Value (FTMx_CnV)...870 38.3.8 Counter Initial Value (FTMx_CNTIN)...871 38.3.9 Capture And Compare Status (FTMx_STATUS)...871
Section number Title Page
38.3.10 Features Mode Selection (FTMx_MODE)...873 38.3.11 Synchronization (FTMx_SYNC)...875 38.3.12 Initial State For Channels Output (FTMx_OUTINIT)...878 38.3.13 Output Mask (FTMx_OUTMASK)...879 38.3.14 Function For Linked Channels (FTMx_COMBINE)...881 38.3.15 Deadtime Insertion Control (FTMx_DEADTIME)...886 38.3.16 FTM External Trigger (FTMx_EXTTRIG)...887 38.3.17 Channels Polarity (FTMx_POL)...888 38.3.18 Fault Mode Status (FTMx_FMS)...891 38.3.19 Input Capture Filter Control (FTMx_FILTER)...893 38.3.20 Fault Control (FTMx_FLTCTRL)...894 38.3.21 Quadrature Decoder Control And Status (FTMx_QDCTRL)...896 38.3.22 Configuration (FTMx_CONF)...898 38.3.23 FTM Fault Input Polarity (FTMx_FLTPOL)...899 38.3.24 Synchronization Configuration (FTMx_SYNCONF)...901 38.3.25 FTM Inverting Control (FTMx_INVCTRL)...903 38.3.26 FTM Software Output Control (FTMx_SWOCTRL)...904 38.3.27 FTM PWM Load (FTMx_PWMLOAD)...906 38.4 Functional description...907 38.4.1 Clock source...908 38.4.2 Prescaler...909 38.4.3 Counter...909 38.4.4 Input Capture mode...914 38.4.5 Output Compare mode...917 38.4.6 Edge-Aligned PWM (EPWM) mode...918 38.4.7 Center-Aligned PWM (CPWM) mode...920 38.4.8 Combine mode...922 38.4.9 Complementary mode...930
Section number Title Page
38.4.10 Registers updated from write buffers...931 38.4.11 PWM synchronization...933 38.4.12 Inverting...949 38.4.13 Software output control...950 38.4.14 Deadtime insertion...952 38.4.15 Output mask...955 38.4.16 Fault control...956 38.4.17 Polarity control...959 38.4.18 Initialization...960 38.4.19 Features priority...960 38.4.20 Channel trigger output...961 38.4.21 Initialization trigger...962 38.4.22 Capture Test mode...964 38.4.23 DMA...965 38.4.24 Dual Edge Capture mode...966 38.4.25 Quadrature Decoder mode...973 38.4.26 BDM mode...978 38.4.27 Intermediate load...979 38.4.28 Global time base (GTB)...981 38.5 Reset overview...982 38.6 FTM Interrupts...984 38.6.1 Timer Overflow Interrupt...984 38.6.2 Channel (n) Interrupt...984 38.6.3 Fault Interrupt...984
Chapter 39
Periodic Interrupt Timer (PIT)
39.1 Introduction...985 39.1.1 Block diagram...985 39.1.2 Features...986
Section number Title Page
39.2 Signal description...986 39.3 Memory map/register description...987 39.3.1 PIT Module Control Register (PIT_MCR)...988 39.3.2 Timer Load Value Register (PIT_LDVALn)...988 39.3.3 Current Timer Value Register (PIT_CVALn)...989 39.3.4 Timer Control Register (PIT_TCTRLn)...989 39.3.5 Timer Flag Register (PIT_TFLGn)...990 39.4 Functional description...991 39.4.1 General operation...991 39.4.2 Interrupts...992 39.4.3 Chained timers...993 39.5 Initialization and application information...993 39.6 Example configuration for chained timers...994
Chapter 40
Low-Power Timer (LPTMR)
40.1 Introduction...997 40.1.1 Features...997 40.1.2 Modes of operation...997 40.2 LPTMR signal descriptions...998 40.2.1 Detailed signal descriptions...998 40.3 Memory map and register definition...999 40.3.1 Low Power Timer Control Status Register (LPTMRx_CSR)...999 40.3.2 Low Power Timer Prescale Register (LPTMRx_PSR)...1001 40.3.3 Low Power Timer Compare Register (LPTMRx_CMR)...1002 40.3.4 Low Power Timer Counter Register (LPTMRx_CNR)...1003 40.4 Functional description...1003 40.4.1 LPTMR power and reset...1003 40.4.2 LPTMR clocking...1003
Section number Title Page
40.4.3 LPTMR prescaler/glitch filter...1004 40.4.4 LPTMR compare...1005 40.4.5 LPTMR counter...1005 40.4.6 LPTMR hardware trigger...1006 40.4.7 LPTMR interrupt...1006
Chapter 41
Carrier Modulator Transmitter (CMT)
41.1 Introduction...1009 41.2 Features...1009 41.3 Block diagram...1010 41.4 Modes of operation...1011 41.4.1 Wait mode operation...1012 41.4.2 Stop mode operation...1013 41.5 CMT external signal descriptions...1013 41.5.1 CMT_IRO — Infrared Output...1013 41.6 Memory map/register definition...1014 41.6.1 CMT Carrier Generator High Data Register 1 (CMT_CGH1)...1015 41.6.2 CMT Carrier Generator Low Data Register 1 (CMT_CGL1)...1016 41.6.3 CMT Carrier Generator High Data Register 2 (CMT_CGH2)...1016 41.6.4 CMT Carrier Generator Low Data Register 2 (CMT_CGL2)...1017 41.6.5 CMT Output Control Register (CMT_OC)...1017 41.6.6 CMT Modulator Status and Control Register (CMT_MSC)...1018 41.6.7 CMT Modulator Data Register Mark High (CMT_CMD1)...1020 41.6.8 CMT Modulator Data Register Mark Low (CMT_CMD2)...1021 41.6.9 CMT Modulator Data Register Space High (CMT_CMD3)...1021 41.6.10 CMT Modulator Data Register Space Low (CMT_CMD4)...1022 41.6.11 CMT Primary Prescaler Register (CMT_PPS)...1022 41.6.12 CMT Direct Memory Access Register (CMT_DMA)...1023
Section number Title Page
41.7 Functional description...1024 41.7.1 Clock divider...1024 41.7.2 Carrier generator...1024 41.7.3 Modulator...1027 41.7.4 Extended space operation...1031 41.8 CMT interrupts and DMA...1033
Chapter 42 Real Time Clock (RTC)
42.1 Introduction...1035 42.1.1 Features...1035 42.1.2 Modes of operation...1035 42.1.3 RTC Signal Descriptions...1036 42.2 Register definition...1037 42.2.1 RTC Time Seconds Register (RTC_TSR)...1038 42.2.2 RTC Time Prescaler Register (RTC_TPR)...1038 42.2.3 RTC Time Alarm Register (RTC_TAR)...1039 42.2.4 RTC Time Compensation Register (RTC_TCR)...1039 42.2.5 RTC Control Register (RTC_CR)...1040 42.2.6 RTC Status Register (RTC_SR)...1042 42.2.7 RTC Lock Register (RTC_LR)...1043 42.2.8 RTC Interrupt Enable Register (RTC_IER)...1044 42.2.9 RTC Write Access Register (RTC_WAR)...1045 42.2.10 RTC Read Access Register (RTC_RAR)...1047 42.3 Functional description...1048 42.3.1 Power, clocking, and reset...1048 42.3.2 Time counter...1049 42.3.3 Compensation...1050 42.3.4 Time alarm...1050 42.3.5 Update mode...1051
Section number Title Page
42.3.6 Register lock...1051 42.3.7 Access control...1051 42.3.8 Interrupt...1051
Chapter 43 CAN (FlexCAN)
43.1 Introduction...1053 43.1.1 Overview...1054 43.1.2 FlexCAN module features...1055 43.1.3 Modes of operation...1056 43.2 FlexCAN signal descriptions...1058 43.2.1 CAN Rx ...1058 43.2.2 CAN Tx ...1058 43.3 Memory map/register definition...1058 43.3.1 FlexCAN memory mapping...1058 43.3.2 Module Configuration Register (CANx_MCR)...1063 43.3.3 Control 1 register (CANx_CTRL1)...1068 43.3.4 Free Running Timer (CANx_TIMER)...1071 43.3.5 Rx Mailboxes Global Mask Register (CANx_RXMGMASK)...1072 43.3.6 Rx 14 Mask register (CANx_RX14MASK)...1073 43.3.7 Rx 15 Mask register (CANx_RX15MASK)...1074 43.3.8 Error Counter (CANx_ECR)...1074 43.3.9 Error and Status 1 register (CANx_ESR1)...1076 43.3.10 Interrupt Masks 1 register (CANx_IMASK1)...1080 43.3.11 Interrupt Flags 1 register (CANx_IFLAG1)...1081 43.3.12 Control 2 register (CANx_CTRL2)...1083 43.3.13 Error and Status 2 register (CANx_ESR2)...1086 43.3.14 CRC Register (CANx_CRCR)...1087 43.3.15 Rx FIFO Global Mask register (CANx_RXFGMASK)...1088 43.3.16 Rx FIFO Information Register (CANx_RXFIR)...1089
Section number Title Page
43.3.17 Rx Individual Mask Registers (CANx_RXIMRn)...1090 43.3.50 Message buffer structure...1091 43.3.51 Rx FIFO structure...1096 43.4 Functional description...1098 43.4.1 Transmit process...1099 43.4.2 Arbitration process...1100 43.4.3 Receive process...1103 43.4.4 Matching process...1105 43.4.5 Move process...1110 43.4.6 Data coherence...1112 43.4.7 Rx FIFO...1115 43.4.8 CAN protocol related features...1117 43.4.9 Clock domains and restrictions...1123 43.4.10 Modes of operation details...1124 43.4.11 Interrupts...1127 43.4.12 Bus interface...1128 43.5 Initialization/application information...1129 43.5.1 FlexCAN initialization sequence...1129
Chapter 44
Serial Peripheral Interface (SPI)
44.1 Introduction...1133 44.1.1 Block Diagram...1133 44.1.2 Features...1134 44.1.3 SPI Configuration...1135 44.1.4 Modes of Operation...1136 44.2 Module signal descriptions...1138 44.2.1 PCS0/SS — Peripheral Chip Select/Slave Select...1138 44.2.2 PCS1 – PCS3 — Peripheral Chip Selects 1 – 3...1138 44.2.3 PCS4 — Peripheral Chip Select 4...1138
Section number Title Page
44.2.4 SIN — Serial Input...1139 44.2.5 SOUT — Serial Output...1139 44.2.6 SCK — Serial Clock...1139 44.3 Memory Map/Register Definition...1139 44.3.1 Module Configuration Register (SPIx_MCR)...1142 44.3.2 Transfer Count Register (SPIx_TCR)...1145 44.3.3 DSPI Clock and Transfer Attributes Register (In Master Mode) (SPIx_CTARn)...1145 44.3.4 Clock and Transfer Attributes Register (In Slave Mode) (SPIx_CTARn_SLAVE)...1150 44.3.5 DSPI Status Register (SPIx_SR)...1151 44.3.6 DMA/Interrupt Request Select and Enable Register (SPIx_RSER)...1154 44.3.7 PUSH TX FIFO Register In Master Mode (SPIx_PUSHR)...1156 44.3.8 PUSH TX FIFO Register In Slave Mode (SPIx_PUSHR_SLAVE)...1158 44.3.9 POP RX FIFO Register (SPIx_POPR)...1158 44.3.10 DSPI Transmit FIFO Registers (SPIx_TXFRn)...1159 44.3.11 DSPI Receive FIFO Registers (SPIx_RXFRn)...1159 44.4 Functional description...1160 44.4.1 Start and Stop of module transfers...1161 44.4.2 Serial Peripheral Interface (SPI) configuration...1161 44.4.3 Module baud rate and clock delay generation...1165 44.4.4 Transfer formats...1167 44.4.5 Continuous Serial Communications Clock...1172 44.4.6 Slave Mode Operation Constraints...1174 44.4.7 Interrupts/DMA requests...1174 44.4.8 Power saving features...1177 44.5 Initialization/application information...1178 44.5.1 How to manage queues...1178 44.5.2 Switching Master and Slave mode...1179 44.5.3 Initializing Module in Master/Slave Modes...1179 44.5.4 Baud rate settings...1179
Section number Title Page
44.5.5 Delay settings...1180 44.5.6 Calculation of FIFO pointer addresses...1181
Chapter 45
Inter-Integrated Circuit (I2C)
45.1 Introduction...1185 45.1.1 Features...1185 45.1.2 Modes of operation...1186 45.1.3 Block diagram...1186 45.2 I2C signal descriptions...1187 45.3 Memory map and register descriptions...1187 45.3.1 I2C Address Register 1 (I2Cx_A1)...1188 45.3.2 I2C Frequency Divider register (I2Cx_F)...1189 45.3.3 I2C Control Register 1 (I2Cx_C1)...1190 45.3.4 I2C Status register (I2Cx_S)...1192 45.3.5 I2C Data I/O register (I2Cx_D)...1193 45.3.6 I2C Control Register 2 (I2Cx_C2)...1194 45.3.7 I2C Programmable Input Glitch Filter register (I2Cx_FLT)...1195 45.3.8 I2C Range Address register (I2Cx_RA)...1196 45.3.9 I2C SMBus Control and Status register (I2Cx_SMB)...1196 45.3.10 I2C Address Register 2 (I2Cx_A2)...1198 45.3.11 I2C SCL Low Timeout Register High (I2Cx_SLTH)...1198 45.3.12 I2C SCL Low Timeout Register Low (I2Cx_SLTL)...1199 45.4 Functional description...1199 45.4.1 I2C protocol...1199 45.4.2 10-bit address...1204 45.4.3 Address matching...1206 45.4.4 System management bus specification...1206 45.4.5 Resets...1209
Section number Title Page
45.4.6 Interrupts...1209 45.4.7 Programmable input glitch filter...1211 45.4.8 Address matching wakeup...1212 45.4.9 DMA support...1212 45.5 Initialization/application information...1213
Chapter 46
Universal Asynchronous Receiver/Transmitter (UART)
46.1 Introduction...1217 46.1.1 Features...1217 46.1.2 Modes of operation...1219 46.2 UART signal descriptions...1220 46.2.1 Detailed signal descriptions...1221 46.3 Memory map and registers...1222 46.3.1 UART Baud Rate Registers: High (UARTx_BDH)...1232 46.3.2 UART Baud Rate Registers: Low (UARTx_BDL)...1233 46.3.3 UART Control Register 1 (UARTx_C1)...1233 46.3.4 UART Control Register 2 (UARTx_C2)...1235 46.3.5 UART Status Register 1 (UARTx_S1)...1237 46.3.6 UART Status Register 2 (UARTx_S2)...1240 46.3.7 UART Control Register 3 (UARTx_C3)...1242 46.3.8 UART Data Register (UARTx_D)...1243 46.3.9 UART Match Address Registers 1 (UARTx_MA1)...1244 46.3.10 UART Match Address Registers 2 (UARTx_MA2)...1245 46.3.11 UART Control Register 4 (UARTx_C4)...1245 46.3.12 UART Control Register 5 (UARTx_C5)...1246 46.3.13 UART Extended Data Register (UARTx_ED)...1247 46.3.14 UART Modem Register (UARTx_MODEM)...1248 46.3.15 UART Infrared Register (UARTx_IR)...1249 46.3.16 UART FIFO Parameters (UARTx_PFIFO)...1250
Section number Title Page
46.3.17 UART FIFO Control Register (UARTx_CFIFO)...1251 46.3.18 UART FIFO Status Register (UARTx_SFIFO)...1252 46.3.19 UART FIFO Transmit Watermark (UARTx_TWFIFO)...1253 46.3.20 UART FIFO Transmit Count (UARTx_TCFIFO)...1254 46.3.21 UART FIFO Receive Watermark (UARTx_RWFIFO)...1254 46.3.22 UART FIFO Receive Count (UARTx_RCFIFO)...1255 46.3.23 UART 7816 Control Register (UARTx_C7816)...1255 46.3.24 UART 7816 Interrupt Enable Register (UARTx_IE7816)...1257 46.3.25 UART 7816 Interrupt Status Register (UARTx_IS7816)...1258 46.3.26 UART 7816 Wait Parameter Register (UARTx_WP7816T0)...1259 46.3.27 UART 7816 Wait Parameter Register (UARTx_WP7816T1)...1260 46.3.28 UART 7816 Wait N Register (UARTx_WN7816)...1260 46.3.29 UART 7816 Wait FD Register (UARTx_WF7816)...1261 46.3.30 UART 7816 Error Threshold Register (UARTx_ET7816)...1261 46.3.31 UART 7816 Transmit Length Register (UARTx_TL7816)...1262 46.3.32 UART CEA709.1-B Control Register 6 (UARTx_C6)...1263 46.3.33 UART CEA709.1-B Packet Cycle Time Counter High (UARTx_PCTH)...1263 46.3.34 UART CEA709.1-B Packet Cycle Time Counter Low (UARTx_PCTL)...1264 46.3.35 UART CEA709.1-B Interrupt Enable Register 0 (UARTx_IE0)...1264 46.3.36 UART CEA709.1-B Secondary Delay Timer High (UARTx_SDTH)...1265 46.3.37 UART CEA709.1-B Secondary Delay Timer Low (UARTx_SDTL)...1265 46.3.38 UART CEA709.1-B Preamble (UARTx_PRE)...1266 46.3.39 UART CEA709.1-B Transmit Packet Length (UARTx_TPL)...1266 46.3.40 UART CEA709.1-B Interrupt Enable Register (UARTx_IE)...1267 46.3.41 UART CEA709.1-B WBASE (UARTx_WB)...1268 46.3.42 UART CEA709.1-B Status Register (UARTx_S3)...1268 46.3.43 UART CEA709.1-B Status Register (UARTx_S4)...1270 46.3.44 UART CEA709.1-B Received Packet Length (UARTx_RPL)...1271
Section number Title Page
46.3.46 UART CEA709.1-B Collision Pulse Width (UARTx_CPW)...1271 46.3.47 UART CEA709.1-B Receive Indeterminate Time High (UARTx_RIDTH)...1272 46.3.48 UART CEA709.1-B Receive Indeterminate Time Low (UARTx_RIDTL)...1272 46.3.49 UART CEA709.1-B Transmit Indeterminate Time High (UARTx_TIDTH)...1273 46.3.50 UART CEA709.1-B Transmit Indeterminate Time Low (UARTx_TIDTL)...1273 46.3.51 UART CEA709.1-B Receive Beta1 Timer High (UARTx_RB1TH)...1273 46.3.52 UART CEA709.1-B Receive Beta1 Timer Low (UARTx_RB1TL)...1274 46.3.53 UART CEA709.1-B Transmit Beta1 Timer High (UARTx_TB1TH)...1274 46.3.54 UART CEA709.1-B Transmit Beta1 Timer Low (UARTx_TB1TL)...1275 46.3.55 UART CEA709.1-B Programmable register (UARTx_PROG_REG)...1275 46.3.56 UART CEA709.1-B State register (UARTx_STATE_REG)...1276 46.4 Functional description...1276 46.4.1 CEA709.1-B...1276 46.4.2 Transmitter...1287 46.4.3 Receiver...1293 46.4.4 Baud rate generation...1302 46.4.5 Data format (non ISO-7816)...1304 46.4.6 Single-wire operation...1307 46.4.7 Loop operation...1308 46.4.8 ISO-7816/smartcard support...1308 46.4.9 Infrared interface...1313 46.5 Reset...1314 46.6 System level interrupt sources...1314 46.6.1 RXEDGIF description...1315 46.7 DMA operation...1316 46.8 Application information...1316 46.8.1 Transmit/receive data buffer operation...1316 46.8.2 ISO-7816 initialization sequence...1317 46.8.3 Initialization sequence (non ISO-7816)...1319
Section number Title Page
46.8.4 Overrun (OR) flag implications...1320 46.8.5 Overrun NACK considerations...1321 46.8.6 Match address registers...1322 46.8.7 Modem feature...1322 46.8.8 IrDA minimum pulse width...1323 46.8.9 Clearing 7816 wait timer (WT, BWT, CWT) interrupts...1323 46.8.10 Legacy and reverse compatibility considerations...1324
Chapter 47
Secured digital host controller (SDHC)
47.1 Introduction...1325 47.2 Overview...1325 47.2.1 Supported types of cards...1325 47.2.2 SDHC block diagram...1326 47.2.3 Features...1327 47.2.4 Modes and operations...1328 47.3 SDHC signal descriptions...1329 47.4 Memory map and register definition...1330 47.4.1 DMA System Address register (SDHC_DSADDR)...1331 47.4.2 Block Attributes register (SDHC_BLKATTR)...1332 47.4.3 Command Argument register (SDHC_CMDARG)...1333 47.4.4 Transfer Type register (SDHC_XFERTYP)...1334 47.4.5 Command Response 0 (SDHC_CMDRSP0)...1338 47.4.6 Command Response 1 (SDHC_CMDRSP1)...1338 47.4.7 Command Response 2 (SDHC_CMDRSP2)...1339 47.4.8 Command Response 3 (SDHC_CMDRSP3)...1339 47.4.9 Buffer Data Port register (SDHC_DATPORT)...1340 47.4.10 Present State register (SDHC_PRSSTAT)...1341 47.4.11 Protocol Control register (SDHC_PROCTL)...1346 47.4.12 System Control register (SDHC_SYSCTL)...1350
Section number Title Page
47.4.13 Interrupt Status register (SDHC_IRQSTAT)...1353 47.4.14 Interrupt Status Enable register (SDHC_IRQSTATEN)...1358 47.4.15 Interrupt Signal Enable register (SDHC_IRQSIGEN)...1361 47.4.16 Auto CMD12 Error Status Register (SDHC_AC12ERR)...1363 47.4.17 Host Controller Capabilities (SDHC_HTCAPBLT)...1367 47.4.18 Watermark Level Register (SDHC_WML)...1369 47.4.19 Force Event register (SDHC_FEVT)...1370 47.4.20 ADMA Error Status register (SDHC_ADMAES)...1372 47.4.21 ADMA System Addressregister (SDHC_ADSADDR)...1374 47.4.22 Vendor Specific register (SDHC_VENDOR)...1375 47.4.23 MMC Boot register (SDHC_MMCBOOT)...1376 47.4.24 Host Controller Version (SDHC_HOSTVER)...1377 47.5 Functional description...1378 47.5.1 Data buffer...1378 47.5.2 DMA crossbar switch interface...1384 47.5.3 SD protocol unit...1390 47.5.4 Clock and reset manager...1392 47.5.5 Clock generator...1393 47.5.6 SDIO card interrupt...1393 47.5.7 Card insertion and removal detection...1395 47.5.8 Power management and wakeup events...1396 47.5.9 MMC fast boot...1397 47.6 Initialization/application of SDHC...1399 47.6.1 Command send and response receive basic operation...1399
Section number Title Page
47.6.2 Card Identification mode...1400 47.6.3 Card access...1405 47.6.4 Switch function...1416 47.6.5 ADMA operation...1418 47.6.6 Fast boot operation...1419 47.6.7 Commands for MMC/SD/SDIO/CE-ATA...1423 47.7 Software restrictions...1429 47.7.1 Initialization active...1429 47.7.2 Software polling procedure...1429 47.7.3 Suspend operation...1430 47.7.4 Data length setting...1430 47.7.5 (A)DMA address setting...1430 47.7.6 Data port access...1430 47.7.7 Change clock frequency...1430 47.7.8 Multi-block read...1431
Chapter 48
Integrated Interchip Sound (I2S) / Synchronous Audio Interface (SAI)
48.1 Introduction...1433 48.1.1 Features...1433 48.1.2 Block diagram...1433 48.1.3 Modes of operation...1434 48.2 External signals...1435 48.3 Memory map and register definition...1435 48.3.1 SAI Transmit Control Register (I2Sx_TCSR)...1437 48.3.2 SAI Transmit Configuration 1 Register (I2Sx_TCR1)...1440 48.3.3 SAI Transmit Configuration 2 Register (I2Sx_TCR2)...1440 48.3.4 SAI Transmit Configuration 3 Register (I2Sx_TCR3)...1442 48.3.5 SAI Transmit Configuration 4 Register (I2Sx_TCR4)...1443 48.3.6 SAI Transmit Configuration 5 Register (I2Sx_TCR5)...1444
Section number Title Page
48.3.7 SAI Transmit Data Register (I2Sx_TDRn)...1445 48.3.8 SAI Transmit FIFO Register (I2Sx_TFRn)...1445 48.3.9 SAI Transmit Mask Register (I2Sx_TMR)...1446 48.3.10 SAI Receive Control Register (I2Sx_RCSR)...1447 48.3.11 SAI Receive Configuration 1 Register (I2Sx_RCR1)...1450 48.3.12 SAI Receive Configuration 2 Register (I2Sx_RCR2)...1450 48.3.13 SAI Receive Configuration 3 Register (I2Sx_RCR3)...1452 48.3.14 SAI Receive Configuration 4 Register (I2Sx_RCR4)...1453 48.3.15 SAI Receive Configuration 5 Register (I2Sx_RCR5)...1454 48.3.16 SAI Receive Data Register (I2Sx_RDRn)...1455 48.3.17 SAI Receive FIFO Register (I2Sx_RFRn)...1455 48.3.18 SAI Receive Mask Register (I2Sx_RMR)...1456 48.3.19 SAI MCLK Control Register (I2Sx_MCR)...1456 48.3.20 SAI MCLK Divide Register (I2Sx_MDR)...1457 48.4 Functional description...1458 48.4.1 SAI clocking...1458 48.4.2 SAI resets...1459 48.4.3 Synchronous modes...1460 48.4.4 Frame sync configuration...1461 48.5 Data FIFO...1461 48.5.1 Data alignment...1461 48.5.2 FIFO pointers...1462 48.5.3 Word mask register...1463 48.5.4 Interrupts and DMA requests...1463
Chapter 49
General-Purpose Input/Output (GPIO)
49.1 Introduction...1467 49.1.1 Features...1467 49.1.2 Modes of operation...1468
Section number Title Page
49.1.3 GPIO signal descriptions...1468 49.2 Memory map and register definition...1469 49.2.1 Port Data Output Register (GPIOx_PDOR)...1471 49.2.2 Port Set Output Register (GPIOx_PSOR)...1472 49.2.3 Port Clear Output Register (GPIOx_PCOR)...1472 49.2.4 Port Toggle Output Register (GPIOx_PTOR)...1473 49.2.5 Port Data Input Register (GPIOx_PDIR)...1473 49.2.6 Port Data Direction Register (GPIOx_PDDR)...1474 49.3 Functional description...1474 49.3.1 General-purpose input...1474 49.3.2 General-purpose output...1474
Chapter 50
Touch sense input (TSI)
50.1 Introduction...1477 50.2 Features...1477 50.3 Overview...1478 50.3.1 Electrode capacitance measurement unit...1479 50.3.2 Electrode scan unit...1480 50.3.3 Touch detection unit...1480 50.4 Modes of operation...1481 50.4.1 TSI disabled mode...1482 50.4.2 TSI active mode...1482 50.4.3 TSI low-power mode...1482 50.4.4 Block diagram...1482 50.5 TSI signal descriptions...1483 50.5.1 TSI_IN[15:0]...1483 50.6 Memory map and register definition...1484 50.6.1 General Control and Status register (TSIx_GENCS)...1485 50.6.2 SCAN Control register (TSIx_SCANC)...1488
Section number Title Page
50.6.3 Pin Enable register (TSIx_PEN)...1490 50.6.4 Wake-Up Channel Counter Register (TSIx_WUCNTR)...1492 50.6.5 Counter Register (TSIx_CNTRn)...1493 50.6.6 Low-Power Channel Threshold register (TSIx_THRESHOLD)...1493 50.7 Functional description...1493 50.7.1 Capacitance measurement...1494 50.7.2 TSI measurement result...1497 50.7.3 Electrode scan unit...1498 50.7.4 Touch detection unit...1501 50.8 Application information...1502 50.8.1 TSI module sensitivity...1502 50.9 TSI module initialization...1502 50.9.1 Initialization sequence...1503
Chapter 51
JTAG Controller (JTAGC)
51.1 Introduction...1505 51.1.1 Block diagram...1505 51.1.2 Features...1506 51.1.3 Modes of operation...1506 51.2 External signal description...1508 51.2.1 TCK—Test clock input...1508 51.2.2 TDI—Test data input...1508 51.2.3 TDO—Test data output...1508 51.2.4 TMS—Test mode select...1508 51.3 Register description...1509 51.3.1 Instruction register...1509 51.3.2 Bypass register...1509 51.3.3 Device identification register...1509 51.3.4 Boundary scan register...1510
Section number Title Page
51.4 Functional description...1511 51.4.1 JTAGC reset configuration...1511 51.4.2 IEEE 1149.1-2001 (JTAG) Test Access Port...1511 51.4.3 TAP controller state machine...1511 51.4.4 JTAGC block instructions...1513 51.4.5 Boundary scan...1516 51.5 Initialization/Application information...1516
Chapter 1
About This Document
1.1 Overview
1.1.1 Purpose
This document describes the features, architecture, and programming model of the Freescale K10 microcontroller.
1.1.2 Audience
This document is primarily for system architects and software application developers who are using or considering using the K10 microcontroller in a system.
1.2 Conventions
1.2.1 Numbering systems
The following suffixes identify different numbering systems:
This suffix Identifies a
b Binary number. For example, the binary equivalent of the
number 5 is written 101b. In some cases, binary numbers are shown with the prefix 0b.
d Decimal number. Decimal numbers are followed by this suffix
only when the possibility of confusion exists. In general, decimal numbers are shown without a suffix.
h Hexadecimal number. For example, the hexadecimal
equivalent of the number 60 is written 3Ch. In some cases, hexadecimal numbers are shown with the prefix 0x.
1.2.2 Typographic notation
The following typographic notation is used throughout this document:
Example Description
placeholder, x Items in italics are placeholders for information that you provide. Italicized text is also used for the titles of publications and for emphasis. Plain lowercase letters are also used as
placeholders for single letters and numbers.
code Fixed-width type indicates text that must be typed exactly as shown. It is used for instruction mnemonics, directives, symbols, subcommands, parameters, and operators. Fixed-width type is also used for example code. Instruction mnemonics and directives in text and tables are shown in all caps; for example, BSR.
SR[SCM] A mnemonic in brackets represents a named field in a register. This example refers to the Scaling Mode (SCM) field in the Status Register (SR).
REVNO[6:4], XAD[7:0] Numbers in brackets and separated by a colon represent either:
• A subset of a register's named field
For example, REVNO[6:4] refers to bits 6–4 that are part of the COREREV field that occupies bits 6–0 of the REVNO register.
• A continuous range of individual signals of a bus
For example, XAD[7:0] refers to signals 7–0 of the XAD bus.
1.2.3 Special terms
The following terms have special meanings:
Term Meaning
asserted Refers to the state of a signal as follows:
• An active-high signal is asserted when high (1).
• An active-low signal is asserted when low (0).
deasserted Refers to the state of a signal as follows:
• An active-high signal is deasserted when low (0).
• An active-low signal is deasserted when high (1).
In some cases, deasserted signals are described as negated.
reserved Refers to a memory space, register, or field that is either
reserved for future use or for which, when written to, the module or chip behavior is unpredictable.
Conventions
Chapter 2 Introduction
2.1 Overview
This chapter provides high-level descriptions of the modules available on the devices covered by this document.
2.2 Module Functional Categories
The modules on this device are grouped into functional categories. The following sections describe the modules assigned to each category in more detail.
Table 2-1. Module functional categories
Module category Description
ARM Cortex-M4 core • 32-bit MCU core from ARM’s Cortex-M class adding DSP instructions, 1.25 DMIPS/MHz, based on ARMv7 architecture
System • System integration module
• Power management and mode controllers
• Multiple power modes available based on run, wait, stop, and power- down modes
• Low-leakage wakeup unit
• Miscellaneous control module
• Crossbar switch
• Memory protection unit
• Peripheral bridge
• Direct memory access (DMA) controller with multiplexer to increase available DMA requests
• External watchdog monitor
• Watchdog
Memories • Internal memories include:
• Program flash memory
• Programming acceleration RAM
• SRAM
• External memory or peripheral bus interface: FlexBus
• Serial programming interface: EzPort Table continues on the next page...
Table 2-1. Module functional categories (continued)
Module category Description
Clocks • Multiple clock generation options available from internally- and externally- generated clocks
• System oscillator to provide clock source for the MCU
• RTC oscillator to provide clock source for the RTC Security • Cyclic Redundancy Check module for error detection
Analog • High speed analog-to-digital converter with integrated programmable gain amplifier
• Comparator
• Digital-to-analog converter
• Internal voltage reference
Timers • Programmable delay block
• FlexTimers
• Periodic interrupt timer
• Low power timer
• Carrier modulator transmitter
• Independent real time clock
Communications • CAN
• Serial peripheral interface
• Inter-integrated circuit (I2C)
• UART
• Secured Digital host controller
• Integrated interchip sound (I2S) Human-Machine Interfaces (HMI) • General purpose input/output controller
• Capacitive touch sense input interface enabled in hardware
2.2.1 ARM Cortex-M4 Core Modules
The following core modules are available on this device.
Table 2-2. Core modules
Module Description
ARM Cortex-M4 The ARM Cortex-M4 is the newest member of the Cortex M Series of processors targeting microcontroller cores focused on very cost sensitive, deterministic, interrupt driven environments. The Cortex M4 processor is based on the ARMv7 Architecture and Thumb®-2 ISA and is upward compatible with the Cortex M3, Cortex M1, and Cortex M0 architectures. Cortex M4 improvements include an ARMv7 Thumb-2 DSP (ported from the ARMv7-A/R profile architectures) providing 32-bit instructions with SIMD (single instruction multiple data) DSP style multiply- accumulates and saturating arithmetic.
Table continues on the next page...
Module Functional Categories
