Design six layers of PCB VIA for 2.4 and 5 GHz

HALMSTAD

UNIVERSITY

Master's program in Electronics Design, 60 Credits

Design six layers of PCB VIA for 2.4 and 5 GHz

Electronics Design, 15 Credits

Halmstad 2019-11-05

Leza Hlele, Darshil B Shripal

i

Preface

We would like to express our sincere gratitude to Halmstad University and HMS Networks AB, Halmstad for giving us such a wonderful opportunity to do this Master Thesis. A study on PCB VIAs for 2.4 GHz and 5 GHz frequencies for six-layers PCB which was full of interesting scientific research coupled with design and simulation using the latest software tools.

This report has been written in October 2019 for a seven-week project under the supervision of Christofer Bengtsson. We thank Christofer for his advice which has always correctly put us. We thank also Per Sandrop for assistance with the simulation part using ADS software.

We are also grateful for our academic supervisor Mohammad Karimi for giving us proper guidance for writing the final report and for moral support, and thanks from the depths of our heart to our examiner Dr. Pererik Andersson who provided us with the required software to complete our scientific research.

Finally, we are thankful to our classmates who supported us and encouraged us throughout the year.

ii

Abstract

Printed circuit boards are getting increasingly more complicated, as the electronics industry seeks methods to stay leading in modern technology. The competition to attain more economical solutions in terms of increasing complexity, integrity, optimum functionality, impose on design engineers to look for new horizons of solutions, then simulating and testing them theoretically and practically, before putting them into the labor market.

In multi-layer boards, the issue of maintaining signal quality while transmitting it between different layers arises, it is a big deal, especially when dealing with RF signals, where each component through which the signal passes must be handled and designed with extreme accuracy to be received at output with a maximum matching with the input signal.

Vertical Interconnect Access (VIA) is the purpose of this thesis. The effect of geometrical shape and the dimensions such as pad, hole and clearance on the impedance due to parasitic capacitance and inductance, consequently on the reflection and attenuation of the passing RF signal passing through was investigated. Besides, a minimized reflection and attenuation was the aim of this project when signals with the frequencies of 2.4 and 5 GHz would pass through the VIA.

iii

List of Abbreviation

PCB - Printed Circuit Board

S parameters - Scattering parameter ADS - Advanced Design System CAD - Computer-Aided Design

FEKO - FEIdbrechnung fur Korper mit Beliebiger Oberflache FR4 - Flame Retardant 4

VIA - Vertical Interconnect Access EMC - Electromagnetic Compatibility EMI - Electromagnetic Interference PTH - Plated Through Hole

VNA – Vector Network Analyzer

SMA – SubMiniature version A (Connector)

iv

List of Figures

Figure 1 HMS Circuit without using VIAs ... 3

Figure 2: Types of VIAs [2] ... 5

Figure 3:3D View of different VIA parts ... 6

Figure 4: Equivalent Model of VIAs [2] ... 7

Figure 5: Return current in multilayer PCB [6] ... 10

Figure 6: Reflection coefficient [11]... 12

Figure 7: Two-port Network: voltages, currents, input and output waves.[2] ... 13

Figure 8: VIA calculators [13] ... 14

Figure 9: Three-dimensional view of six-layer PCB(ADS) ... 16

Figure 10: Impedance of the VIA for various anti-pad diameter ... 18

Figure 11: S11 of the VIA for anti-pad diameter ... 19

Figure 12: Loop area (ADS) ... 20

Figure 13: VIA Pad in 3D(ADS)... 20

Figure 14: VIA Impedance for various Pad-diameters(Z1) ... 21

Figure 15: S11 for various Pad-diameters ... 22

Figure 16: coplanar waveguide on the outer layer [3] ... 23

Figure 17: coplanar waveguide calculator [13]... 24

Figure 18: Ground VIA offset (ADS) ... 24

Figure 19: impedance at 0.915mm for ground VIA offset ... 25

Figure 20: various values for the impedance for different ground VIAs offset ... 26

Figure 21: S21 for different frequencies ... 27

Figure 22: S11 for different frequency ... 27

Figure 23: S11 various ground VIAs offset ... 28

Figure 24: Measurement setup: PCB testing on VNA ... 30

Figure 25: S11 for all test from test 1 to test 6 ... 31

Figure 26: Smith-chart for all test from test 1 to test 6 ... 31

Figure 27: S21 for all test from test 1 to test 6 ... 32

Figure 28: S11 for all test from test 2b ... 32

Figure 29: S21 for all test from test 2b ... 33

Figure 30: VIA’s SMA connector and its pad ... 34

v Figure 31: Cross-section of PCB layers ... 35

vi

List of Tables

Table 1: Structure of six-layer PCB (HMS Networks PCB Design) ... 17

vii

Table of Contents

Preface ... i

Abstract ... ii

List of Abbreviation ... iii

List of Figures ... iv

List of Tables ... vi

Table of Contents ... vii

1 INTRODUCTION ... 2

1.1 Background ... 2

1.2 About HMS NETWORKS AB, Halmstad, Sweden ... 2

1.3 Problem statement ... 2

2 Theory of PCB VIAs (Vertical Interconnect Access) ... 5

2.1 What is VIAs (Vertical Interconnect Access) ... 5

2.1.1 Types of VIA ... 5

2.1.2 Parts of a VIA ... 6

2.1.3 VIA circuit theory ... 7

2.2 Characteristic Impedance of a VIA ... 8

2.3 Return current near VIA Signal and propagation on Packages ... 9

2.4 Skin Depth ... 10

2.5 Reflection Coefficient ... 11

2.5.1 Scattering parameters ... 12

2.6 VIA parameters calculation ... 14

3 Simulation: Result and Analysis ... 16

3.1 Simulation Tool ... 16

3.1.1 3D Electromagnetic Field Simulators: ... 17

3.2 Simulation Results ... 17

3.2.1 The impedance of the VIA with various anti-pad diameters. ... 18

3.2.2 S11 for various anti-pad diameters. ... 19

viii

3.3 Various values for Via pads: ... 20

3.3.1 Impedance ... 21

3.3.2 S11 ... 22

3.4 PCB with coplanar waveguide ... 23

3.5 Various values for ground VIAs offset ... 24

3.5.1 Impedance ... 25

3.5.2 S21 ... 26

3.5.3 S11 ... 27

3.5.4 Various vales of S11 ... 28

4 Experimental: Test result ... 30

4.1 PCB testing S11 for all test: ... 31

4.1.1 PCB testing Smith-chart for all test: ... 31

4.1.2 PCB testing S21 for all test: ... 32

4.1.3 S11 for 2b test ... 32

4.1.4 S21 for test 2b ... 33

5 Conclusion and future work ... 38

6 REFERENCES ... 40

1

2

1 INTRODUCTION

1.1 Background

VIA (vertical interconnect access) is a connection which electrically connects two different layers or traces within the multi-layered PCBs (Printed Circuit Board) to simplify trace routing around other components or when a high density of interconnections is needed. VIA usually exhibits some characteristic impedance determined by its geometry, which causes a change in the impedance through the signal path. This change in impedance is referred to as a discontinuity, which causes a portion of the signal to be reflected at the point of change; such reflections represent a distortion of the signal. Discontinuities can be capacitive or inductive and have the effect of more time delay, degrading signal integrity (the quality of the signal), and generation of electromagnetic radiation. This is maybe not a big issue at low frequencies designs. However, it could become a critical issue in high speed printed circuit board design.

Therefore, each hardware designer should carefully design the VIAs to minimize these radiations and reflections as much as possible to transit a high-quality signal.

1.2 About HMS NETWORKS AB, Halmstad, Sweden

HMS Networks AB is the Swedish company that was founded in 1988 by Staffan Dahlstrom and Nicolas Hassbjer. HMS is the leading supplier of products of industrial communication.

HMS stands for Hardware meets Software, which is the foundation for industrial communication and automation as well as industrial internet of things. Their main goal is to deliver communication solutions that connect industrial devices and machines to different industrial networks, control systems, and IoT software [1].

1.3 Problem statement

HMS Networks AB intends to design their new products with an IoT device. The Anybus Wireless Bridge is a product developed by HMS Networks AB to achieve a new and smart

3 network infrastructure. The Anybus Wireless Bridge supports up to 400 meters of reliable wireless communication and can communicate VIA both Bluetooth and WLAN (wireless local area network). It is ideal for replacing Ethernet cabling in hard-to-reach or hazardous locations.

The PCB for this product is shown in the down figure (PCB of Anybus Wireless Bridge)

Figure 1 HMS Circuit without using VIAs

In the current version of this product, coaxial cables are used to route the RF (radio frequency) signals through the PCB shown in figure 1. For the next generation of this product, HMS intends to do some optimizations like routing the RF signals through PCB traces with a possibility to let an RF signal switch the PCB side through a VIA. The presence of an impedance-matched VIA will give increased design flexibility and lower cost [1].

4

5

2 Theory of PCB VIAs (Vertical Interconnect Access) 2.1 What is VIAs (Vertical Interconnect Access)

A VIA hole in a PCB provides a path for electrical and thermal energy to move from one layer to another on a circuit board. This hole is made conductive by electroplating.

2.1.1 Types of VIA

There are three types of VIAs for multilayer PCB.

1)PTH (Plated Through Hole): VIAs are generally the least expensive for a circuit design that connects two exterior layers. It is open from both ends.

2)Blind VIAs: Blind VIAs connect an exterior layer to an interior layer. It is open at one end so the plating solution cannot get through the hole.

3)Buried VIAs: Buried VIAs connect two interior PCB layers.

Figure 2 displays PCB surfaces. During the manufacturing of PCB, these types of layers can be assembled. In this figure, considering in different four layers of PCB and different materials.

This is just an example of how segments and material are explained [2].

Figure 2: Types of VIAs [2]

6

2.1.2 Parts of a VIA

VIAs consist of three different parts,

1)Barrel: The conductive tube filling the drilled hole of the main signal VIA is called barrel.

2) Pad: It connects each end of the barrel to the component, plane, and trace.

3) Antipad: Clearance hole between barrel and no connect metal layer.

Figure 3 shows a three-dimensional cross-section of two coplanar waveguides [3] connected using a VIA that passes through the ground plane and inner layers. The RF signal is surrounded by ground VIAs to secure the way for the return current. The ground VIAs also can be through- hole or buried VIAs. The VIA signal impedance is influenced by the location, type and number of ground VIAs [4].

Figure 3:3D View of different VIA parts

7

2.1.3 VIA circuit theory

The electrical model of a VIA consists of three segments, upper pad, cylinder, and lower pad.

Each segment comes in the form of a capacitance and an inductance, these add more time delay, longer rise and fall time of the signal and degradation of signal integrity which is a critical issue in high-frequency circuit design. These inductances and capacitances are a function of the geometrical shape of the VIA and contribute to a mismatch in the impedance between the VIA and the transmission lines connected by it. As frequency increases, the pads section will continue to behave more capacitive and the barrel tends to behave more inductive or higher impedance. This VIA circuit doesn't include any coupling elements.

The PCB acts as a passive network where an inductor is formed by long trace and anti-pad, and a capacitor is formed by a pad to trace and pad diameter.

Here is the basic component of the transmission line model [4] shown in figure 4.

Figure 4: Equivalent Model of VIAs [2]

The capacitance of a VIA hole [5] is defined as:

C= ^1.41𝜀

^𝑇𝐷

𝐷

−𝐷

8 Εr: the dielectric constant

T: the thickness of the PCB D1: pad diameter

D2: anti-pad diameter(clearance)

Use a simple coaxial approximation to obtain capacitance formula. A distance equal to the total transit height is determined by the coaxial approximation. The coaxial approximation underestimates the actual VIA capacitance by ignoring fringe-field effects at the ends (top and bottom) of the through [6].

The inductance of VIA Hole [5] is defined as:

L = 5.08h [ ln ( ^4ℎ

𝑑 )+1]

h: the height of VIA-hole d: hole diameter

The above equation derived from the magnetic field lines of force due to signal current from the concentric circle of signal VIA. This is a two-dimensional integration of the magnetic field expression. In metric units of MKS (h, s, and r in meters, L in Henries), the constant μ/2π works at 2·10-7 H / m (assuming a dielectric non-magnetic). The constant μ/2π equals 5.08 nH / in in English units (h, s, and r in inches, L in nH) [4].

2.2 Characteristic Impedance of a VIA

In this thesis, we will ignore the losses produced by the transmission lines, therefore we will consider them as lossless transmission lines and we focus more on the losses produced by the discontinuity in impedance because of the VIA. In this paper, we are investigating the impact of VIA's physical geometric shape on electrical parameters, capacitance, and inductance. A VIA's impedance characteristic [7] is defined as:

9

Z

=√ ^𝐿

𝐶

L: the inductance of the VIA C: the capacitance of the VIA

2.3 Return current near VIA Signal and propagation on Packages

In general, the return current refers to the ground current in the system which must find a low impedance path to go back to the source. For high-speed traces on PCB layers, signals change layers to reach the output and return current also changes the layers in the opposite direction.

The return current crosses from the bottom ground (reference) layer to the top reference layer.

To secure a path for the return current is using ground VIAs. Because of skin effect this return current flows around the VIA opening hole from the bottom surface to the upper surface of the bottom ground layer, then through the Ground VIA outer surface to reach the upper ground plane ends at the source [8] as shown in figure 5. The ground reference plane usually is unbroken and provides a good return current path. Return current cannot flow across a split in the reference plane. In this case, the return current will try to take the path with lower impedance to go back to the source. In many cases this path is the air, which means the radiation of the RF signal out of the PCB, thus, losing a fraction of the signal [8].

In six-layer PCB, ground planes lie next to the layers where the trace carrying RF signal is traveling vertically, Ground VIAs which will be added surrounded and close to the Signal- VIA to secure the path for the return current, [4] affect the impedance of the signal VIA [6].

10 Figure 5: Return current in multilayer PCB [6]

2.4 Skin Depth

Definition of Skin depth: “When an AC current is applied to a conductor, the current concentrates near the surface of the conductor and its strength decreases as you go towards the center of the conductor. The depth till which current flows in a conductor is called as Skin Depth” [9].

The skin effect is where AC current avoids traveling through the center of the conductor. The copper on PCB in the case of High-frequency circuit, current experience changing energy density as current flows through PCB's conductors and prefers to flow near the surface. This effectively decreases the cross-sectional conductor area available to transfer alternating electron flow, increasing the resistance of the conductor above the supposed resistance of the same conductor for the DC current.

The mathematical expression of Skin effect [10]:

11

𝛿 = √ 2𝜌 𝜔𝜇

Where

ω = Angular frequency of Current ρ = Resistivity of the conductor µ = µrµ0

µr = Relative magnetic permeability µ0 = The permeability of free space ɛ = ɛrɛ0

ɛr = Relative permittivity of the material ɛ0 = The permittivity of free space

2.5 Reflection Coefficient

The reflection coefficient is described in figure 6 that quantifies how much of an electromagnetic wave is reflected by an impedance discontinuity in the transmission medium.

The reflection coefficient is equal to the ratio of the amplitude of the reflected wave to the incident wave [11].

There are many ways for calculating the reflection coefficient. From the above definition of the reflection coefficient, it can be calculated from the incident and reflected voltages.

12 Figure 6: Reflection coefficient [11]

Г= ^𝑉

𝑉

Where

Г = Reflection coefficient VRef = Reflected Voltage VFwd = Forward Voltage

2.5.1 Scattering parameters

The Scattering matrix is a mathematical expression that explains the RF (Radio Frequency) energy propagates through input and output relation between different ports.

When a signal incident at one port, some fraction of that signal gets reflected out from the incident port and some enter incident port then scatters into different ports and somewhat power disappears as heat or electromagnetic radiation. This S(scattering) parameters represent possible input and output path. [12]. We consider the two-port network that is connected to a voltage source with impedance ZG and load impedance ZL that shown below figure 7. Here the variables a1, b1 at port 1 and a2, b2 at port 2 are defined in terms of V1, I1, and V2, I2, and reference impedance Z0 commonly choose 50Ω [2].

13 Figure 7: Two-port Network: voltages, currents, input and output waves.[2]

S11=

𝑎1

, S12=

𝑎2 ^;

a

=

2√𝑍₀

, a

=

2√𝑍₀

,

S21=

𝑎1

, S22=

𝑎2

b

=

2√𝑍₀

, b

=

2√𝑍₀

Where a1 is the incident wave at port 1, a2 is the incident wave at port 2, b1 is the reflected wave at port 1 and b2 is the reflected wave at port 2.

In S(Scattering)-parameter response for N(number)-port network, consider input and output as a two-port network so that only S11 and S21 important. Here S21 means response at port 2 due to signal at port 1 that refers to incident port and for S11 response at port 1 due to signal at port 1. This scattering matrix describes accurately different properties of radiofrequency in mathematical construction. For an RF signal incident on one port and reflected from the incident port that means attenuation or power dissipation as heat or electromagnetic radiation.

The value of a and b is expressed as complex numbers with real and imaginary quantities, but we find only the part of magnitude for the simplicity of math. VNA (Vector Network Analyzer) can be used to calculate it. Magnitudes can be expressed linearly and logarithmically in decibels (dB) in two different ways. S-parameter is a complex voltage ratio, the formula of representing is and phase of the changed by the network [2].

Sij(dB) = 20*log [Sij(magnitude)]

The following two parameters are considered in this paper:

14

S

= ^𝑉

𝑉

=Г

S

= ^𝑉

𝑉

= Τ

Where Γ is the Reflection Coefficient and Τ is the Transmission Coefficient. By extracting these two parameters, the response of an element can be determined.

2.6 VIA parameters calculation

An online calculator has been used to calculate the initial values for hole diameter, pad diameter and the Clarence of the VIA to get an approximate 50 Ω impedance. This Saturn PCB Toolkit is the best way to calculate impedance and current capacity [13]. We calculate VIA capacitance and inductance from the above equation, added material permittivity average consideration as 3.9, adding VIA hole and internal pad diameter and from this all calculation overall result around 50Ω impedance. Most of the people have suggested this calculator while using VIA on PCB for calculating VIA current and impedance matching [14].

Figure 8: VIA calculators [13]

15

16

3 Simulation: Result and Analysis

3.1 Simulation Tool

In the work preceding this thesis, we develop a PCB in the Advanced Design System ADS as a simulation tool. Figure 9 shows a three-dimensional view of a six-layer PCB where the signal VIA is surrounded by two types of ground VIAs through-hole and blind.

Figure 9: Three-dimensional view of six-layer PCB(ADS)

The model is a six-layered PCB with 1612 µm total thickness. Table 1 shows the thicknesses, materials, and the values of dielectric constants of the different layers in the PCB.

17 Table 1: Structure of six-layer PCB (HMS Networks PCB Design)

3.1.1 3D Electromagnetic Field Simulators:

The electrical parameters of VIA are extracted using a 3D electromagnetic field simulator (ADS). The simulator allows physical geometry's to be described, (pad, cylinder, ground plane, etc...) and then solve for the capacitance and inductance at any point or between any two conductors. Capacitance and inductance are extracted by solving Poisson’s equation. It is based on the finite difference method with an automatically adjustable rectangular mesh. The linear equations set up by the finite-difference method are solved by the Incomplete Cholesky Conjugate Gradient method (ICCG). The combination of the automatic adjustment of mesh and the speed of ICCG makes the capacitance and inductance extraction very versatile [15].

3.2 Simulation Results

Anti-pad diameters of 0.65 mm, 0.92 mm, 1.3 mm were tested for a fixed number of two ground VIAs, S- parameters S11, S21 and VIA impedance.

18

3.2.1 The impedance of the VIA with various anti-pad diameters.

Figure 10: Impedance of the VIA for various anti-pad diameter

As the anti-pad (clearance) decreases, the inductance increases due to the longer path for the return current generated by increasing the clearance, which in turn affects the VIA impedance given by the formula [4].

Z

=√ ^𝐿

𝐶

From figure 10, it's clear that when the clearance increases the impedance of the VIA increases, which satisfies the impedance equation.

19

3.2.2 S11 for various anti-pad diameters.

Figure 11: S11 of the VIA for anti-pad diameter

When the VIA impedance differs from 50Ω this causes reflection of the radio frequency signal which is expressed by the formula of the Reflection coefficient.

S

= ^(Z−𝑍

⁾

(Z+𝑍

)

Where,

S11 is the reflection coefficient, Z is the impedance of the VIA, Z0 is characteristics impedance(50Ω)

From figure 11, it’s clear that the reflection coefficient changes when the clearance changes.

As shown in figure 12, the increased clearance causes an increase in the discontinuity in the ground plane under the trace. In this case, the longer path for the return current is caused. Here the colors showing are field intensity of EM(Electromagnetic) waves.

20 Figure 12: Loop area (ADS)

3.3 Various values for Via pads:

The impedance of VIA changes according to its capacitive characteristics which are related to VIA-pads figure 13.

Figure 13: VIA Pad in 3D(ADS)

21 For fixed anti-pad Diameter 1 mm and 2 ground VIAs and for 0.65mm,0.92mm, and 1.3mm pad diameters.

3.3.1 Impedance

Figure 14: VIA Impedance for various Pad-diameters(Z1)

The capacitance increases as the pad radius increases, this is since the surface area of the VIA is increasing and capacitance is proportional to the surface area of the conductors, which in turn affects the impedance of the VIA given by the formula:

Z

=√ ^𝐿

𝐶

From figure 14, it’s clear that when the Pad-diameter increases the impedance of the VIA decreases, which satisfies the impedance equation.

22

3.3.2 S11

Figure 15: S11 for various Pad-diameters

The discontinuity in impedance causes reflection of the radio frequency signal which is given by the formula of the Reflection coefficient [4].

S

= ^(Z−𝑍

⁾

(Z+𝑍

)

Where,

S11 is the reflection coefficient, Z is the impedance of the VIA, Z0 is characteristics impedance(50Ω)

From figure 15, it’s clear that when the Pad-diameter changes the impedance of the VIA changes, which affect the reflection coefficient.

23

3.4 PCB with coplanar waveguide

The design was developed by adding coplanar waveguides on the outer layers of PCB as shown in figure 16. Here conductor strip separated by a pair of ground planes on the top of the dielectric medium. The main advantage of using this coplanar waveguide is that active device can be mounted on the top of the surface and it provides a high-frequency response (100GHz) and it does not contain parasitic discontinuity in the ground plane [3]. Comparing both the figures of coplanar waveguide figures 16 and 17.

Figure 16: coplanar waveguide on the outer layer [3]

Determining the dimensions of the coplanar waveguide and calculating for perfect matching impedance of 50Ω. An online calculator has been used to determine the values of trace width and gap for a coplanar waveguide with the ground.

At relative dielectric constant 𝜀_𝑟= 3.95 Dielectric thickness(h): 0.089mm

These values lead to characteristics impedance Z0= 50.22Ω at Trace Width(S)= 0.2mm

Gap width(W)=0.38mm

24 Figure 17: coplanar waveguide calculator [13]

3.5 Various values for ground VIAs offset

The return current should find a way to go back to the source, hence the closer the ground VIA, the smaller the inductance is.

The ground VIA offset is the distance between the center of the signal VIA and the center of the ground VIA figure 18.

S11, S21, and impedance (Z) have been tested for Various values for ground VIA offset such as 0.855mm, 0.895mm, 0.915mm.

Figure 18: Ground VIA offset (ADS)

25

3.5.1 Impedance

The following equation of impedance has been inserted into the ADS simulator to extract the value of the impedance from S11.

Z=⌈ ^1+𝑆(1,1)

1−𝑆(1,1) ⌉*50

At 0.915mm of ground VIA offset, the values for impedance have been achieved as shown in below graph

Figure 19: impedance at 0.915mm for ground VIA offset

It's clear from figure 19 that the impedance at 2.4 and 5 GHz is very close to matching impedance (50Ω).

Then various values for the impedance were extracted for various values for Ground VIAs offset shown in figure 19.

26 Figure 20: various values for the impedance for different ground VIAs offset

Figure 20 shows that the impedance increases when the offset increases, which is due to the increased inductance resulted from the longer return path. The increase in impedance happens at higher frequencies due to the skin effect.

3.5.2 S21

At 0.915mm of ground, VIA offset, values for S21 have been achieved as shown in figure 21 for both frequencies 2.4 and 5 GHz.

27 Figure 21: S21 for different frequencies

Figure 21 shows very low attenuation at this offset for both frequencies 2.4 and 5 GHz.

3.5.3 S11

At 0.915mm of ground, VIA offset, values for S11 have been achieved as shown in figure 22 for both frequencies, in other words, a minimized reflection.

Figure 22: S11 for different frequency

28

3.5.4 Various vales of S11

After simulating S11 for various values of ground-VIAs offset like 0.915, 0.895, 0.855, it was noticed that decreasing the distance between the signal VIA and the Ground VIA increases the frequency at which the best value for S11 is obtained as shown in the figure 22, that is due to the increased capacitive fraction resulted from the accumulated charge by the alteration of the RF signal, which in turn leads to the match case at a certain frequency where the combination of the capacitive fraction and the inductance fraction results in a 50 ohm impedance.

Figure 23: S11 various ground VIAs offset

In figure 23 shows that tuning the ground VIA offset could be the key to tune the impedance thus, the reflection coefficient for the multi-layer PCB at a certain frequency.

29

30

4 Experimental: Test result

CAD (Computer aided design) designing tool that used for precision drawings or technical illustrations of 2D or 3D models. Using this we design the structures of the PCB layout shown in figure 24. Measuring the RF signal requires the use of a scattering parameter. VNA uses the origin to sweep between an interval and a test device connected to ports 1 and port 2. It tests the reflected and transmitted waves, and this is necessary to present the s-parameters.VNA Showing how well the impedance matched port on the test device is used (port 1 and port 2).

The network analyzer will present results in a Smith chart diagram by measuring different parameters changing different pads and ground VIA diameter. To be able to calculate with VNA, the test system connected to the ports is mounted on the PCBs with two 50Ω coaxial cables. The VNA provides possible accurate measurements for the test of scattering parameters. Here total 6 test structure and all are similar test design.

Figure 24: Measurement setup: PCB testing on VNA

31

4.1 PCB testing S11 for all test:

Figure 25: S11 for all test from test 1 to test 6

In figure 25, all six test results are inferred. We clearly see that the value of S11 at 2.45 GHz frequency is around -15 dB, which means low reflected waves relative to other frequencies.

However, for 5GHz frequency S11 goes through more reflection and thus more signal attenuation.

4.1.1 PCB testing Smith-chart for all test:

Figure 26: Smith-chart for all test from test 1 to test 6

32

4.1.2 PCB testing S21 for all test:

Figure 27: S21 for all test from test 1 to test 6

4.1.3 S11 for 2b test

Figure 28 shows that the value of S11 for the test 2b is -17.503 dB, which is comparatively less return loss than the other test structure.

Figure 28: S11 for all test from test 2b

33

4.1.4 S21 for test 2b

Figure 29 shows that less attenuation at 2.45 GHz for test 2b which is -1.718dB.

Figure 29: S21 for all test from test 2b

Above all test results for 5GHz frequency showing that more reflection and attenuation of the signal. The reason behind this issue is manufacturing defects and not an appropriate SMA connector pad that is connected to the signal trace shown in figure 30. The port's diameter is greater than the trace, resulting in impedance transformation and increased losses due to the SMA Footprint pad.

In order to validate this result in ADS, we can see from the figure 30 that the pad at connectors and trace size has a significant impact on impedance and result for S11 and S21 shown in the figure (28,29). Its graph proof if we use the same diameter as the SMA (Subminiature version A) connector used in the ADS simulator, it is possible to obtain the same result.

PCB output is more sensitive to high-frequency power and ground plane noise, and here VIA plays a key role in enforcing issues related to signal integrity such as interference crosstalk and mismatch impedance [16].

34 Figure 30: VIA’s SMA connector and its pad

In this HMS Network Six-layer design, we need to do an exact 5mm VIA hole and above the SMA connector problem arises more and losses increase in the Hardware.

The RF pad of the SMA footprint gives a large reflection, which is why S11 measures between -10 to -20 dB. This pad creates a capacitance since it has a large surface compared to the distance to the underlying reference plane in the cross-section shown in figure 31, which is captured by using a microscope. Specification of the layers is shown in table 1 and figure 9 shows different material of the layers of the PCB. The middle two copper layers are not visible in the figure because they etched away. The thickness of the PCB is 1216 µm.

35 Figure 31: Cross-section of PCB layers

The main reason for the increased measurement uncertainty is that the calculations are done after the logarithmic conversion in the measurement receiver. When the raw measured reflection values from the logarithmic receiver (both the calibration values and the actual measurements) are fairly high (maybe only a few dB lower than the transmitted test signal) and the difference between those raw measured signals is what is displayed as the final result on the logarithmic diagram on the screen. The smallest detectable difference may manifest itself as fluctuations in the range between of 10 or 20 dB on the lower end of the scale on the screen. Any difference between the calibration reflection and the measurement reflection (both in terms of amplitude and phase) will raise the final presented dB value, so most measured frequency points are likely to have some difference in either phase or amplitude, compared to the calibration value. That will prevent the final result from going down any further than -10 to -20 dB. We activated the trace smoothing, which probably is just an averaging between adjacent measurement points on the frequency scale. The graph(S11) was more "hairy", because a few measurement points happened to give more or less the same amplitude and phase in the reflection as was detected during calibration, thus letting a few final measurement points drop further down on the dB scale.

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5 Conclusion and future work

In high-speed multi-layer PCB, VIAs play a considerable role in the transferring of the RF signals between different layers. The precise and appropriate design of VIA will improve the overall performance of the PCB reducing costs and radiation, giving better transition quality, less electromagnetic interference and so on.

The different parts of the VIA affect its impedance, thus, affect the reflection and radiation of the RF signal passing through it.

Increasing the radius of VIA pads increases the capacitance as it adds more surface.

Increasing the radius of the clearance around the VIA increases the inductance and the radiation because it creates a current loop for the return current.

Tuning the distance between ground VIAs and signal VIA enables the designer to tune the frequency response of the VIA

So, we can say that the validity and reliability in high-speed multi-layer PCB will be improved by an accurate design of VIAs in the PCB.

In PCB design the main reason why the result of the S11 measurements is between -10 to -20 dB is that there is a large reflection from the RF pad of the SMA footprint. This pad creates a capacitance since it has a large surface compared to the distance to the underlying reference plane shown in the cross-section of the PCB.

We look forward to improving our design and selecting a suitable connector to reduce losses and increase the PCB's performance. The design of an eight-layer PCB with low loss is another interesting project.

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6 REFERENCES

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[3] https://www.microwaves101.com/encyclopedias/coplanar-waveguide

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41 [11]https://www.electronics-notes.com/articles/antennas-propagation/vswr-return-loss/reflection- coefficient.php

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(2010). Signal Integrity Design for High-Speed Digital Circuits: Progress and Directions.

Electromagnetic Compatibility, IEEE Transactions on. 52. 392 - 400. 10.1109/TEMC.

PO Box 823, SE-301 18 Halmstad Phone: +35 46 16 71 00

E-mail: registrator@hh.se www.hh.se

Leza Hlele

Master of Science, Electronics Design Bachelor of Engineering,

Electronics and Communication Engineering

Bachelor of Engineering,

Electronics and Communication Engineering